Lab 2 Pn JFET Characteristics 2 1112
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COURSE CODE: EXPERIMENT NO: 2 COURSE INSTRUCTOR: DATE: TITLE: MARKS OBJECTIVE: PRELAB : 1 /2 2 /3 / 5 EXPERIMENT RESULT: Table 2-1 /4 Table 2-2 /1 / 5 POST LAB: 1 /3 2 /2 3 /3 4 /1 / 9 CONCLUSION: / 1 INSTRUCTOR COMMENTS: TOTAL / 20 UNIVERSITI TENAGA NASIONAL Dept of Electronics and Communication Engineering College of Engineering EEEB141 pn JFET Characteristics The objectives of this laboratory experiment is to study the characteristics related to pn JFETs Semester: 2 Academic Year: 2011 / 2012 TIME: STUDENT NAME: STUDENT ID: SECTION: WORKBENCH NO: GROUP MEMBER: STUDENT ID:
description
JFET
Transcript of Lab 2 Pn JFET Characteristics 2 1112
COURSE CODE: EXPERIMENT NO: 2
COURSE INSTRUCTOR: DATE:
TITLE: MARKS
OBJECTIVE:
PRELAB :
1 /22 /3
/ 5
EXPERIMENT RESULT:
Table 2-1 /4Table 2-2 /1
/ 5
POST LAB:
1 /32 /23 /34 /1
/ 9
CONCLUSION: / 1
INSTRUCTOR COMMENTS: TOTAL
/ 20
UNIVERSITI TENAGA NASIONALDept of Electronics and Communication Engineering
College of Engineering
EEEB141
pn JFET Characteristics
The objectives of this laboratory experiment is to study the characteristics related to pn JFETs
Semester: 2 Academic Year: 2011 / 2012
TIME:
STUDENT NAME: STUDENT ID:
SECTION: WORKBENCH NO:
GROUP MEMBER: STUDENT ID:
EEEB141 ELECTRONICS DESIGN LAB, Lab 2 1
LAB 2 PN JUNCTION FIELD EFFECT TRANSISTOR (JFET) – CHARACTERISTICS
LEARNING OBJECTIVES By the end of this experiment, you should be able to:
1. Determine the effect of drain-to-source voltage VDS on drain current ID and reverse gate-to-source bias voltage VGS.
2. Determine and plot the family of drain characteristics of a pn JFET. 3. Determine and plot a pn JFET transfer curve.
MATERIALS Transistor: 1 × 2N3819 (JFET) EQUIPMENT
• Tektronix PS280 DC Power Supply • Fluke 45 Dual Display Multimeter
PRE-LAB ASSIGNMENT
1. Draw the cross section area of an n-channel pn JFET. Label
the source, drain, gate, and depletion regions.
2. Describe the relationship between the drain current, ID and the depletion region
(space-charge region) as the gate to source voltage, VGS is varied. Draw the appropriate figures.
EEEB141 ELECTRONICS DESIGN LAB, Lab 2 2
BACKGROUND There are two principle types of transistors, which are the bipolar junction transistors (BJTs) and Field Effect Transistors (FETs). In this experiment however, we will limit the study to FETs (particularly pn JFETs) and BJTs will be discussed in the next experiments. A FET is a straight forward device. The basic idea of a FET is to control the charge density of a channel by means of a bias controlled electric field. To minimize the leakage current of the input signal, the bias voltage is connected to a contact that is isolated from the channel, named a gate. Two types of FETs are the Metal-Oxide-Semiconductor FET (MOSFET) and Junction FET (JFET). Two general categories of JFETs are the pn JFET and the Metal-Semiconductor FET (MESFET). pn-JFET utilizes a pn-junction for the gate isolation, while MESFET utilizes Schottky barrier. Typical transistors have three leads, and in case of JFETs, a voltage on one lead (called the gate) is used to control a current between two other leads (called drain and source). The figure below illustrated the circuit symbol of n-channel and p-channel JFET where G, D and S refers to gate, drain and source, respectively. n-channel p-channel IN-LAB ACTIVITIES
Gate Short-Circuited To Source
1. Construct the circuit as shown in Figure 3-1.
Figure 2-1: Gate short-circuited to source circuit
D
G
S
ID
VDS
+
- +
VGS -
S
G
D
+
VGS -
VSD
+
-
ID
EEEB141 ELECTRONICS DESIGN LAB, Lab 2 3
2. Set VDD = 0.0V. Note that VDD = VDS. Measure and record the drain current ID for VDS = 0V, and VGS = 0V.
3. Increase VDD to 1.0V. By using the DMM, measure and record ID for VDS = 1.0V,
and VGS = 0V.
4. Repeat for each value of VDS as listed in Table 2-1.
5. Reset VDD to zero, and POWER OFF.
Gate Is Reverse-Biased
6. Remove the short circuit between the gate and the source and connect voltage source VGG as shown in Figure 2-2.
Figure 2-2: Reverse-biased gate circuit
7. Set VGG = -0.2V (note: VGG = VGS), at VDD = VDS = 0V. Measure and record the
drain current ID.
8. Maintain VGG at -0.2V. Repeat step 7, for each value of VDS as listed in Table 2-1.
9. Reset all the voltage sources back to zero.
10. Repeat for each value of VGS and VDS listed in Table 2-1.
11. Reset all the voltage sources back to zero and POWER OFF.
Transfer Characteristic
12. Set VDD = 15V, and VGG = -2.5V. Measure and record the drain current ID.
13. Repeat step 12 for each value of VGS listed in Table 2-2, at VDD = 15V.
EEEB141 ELECTRONICS DESIGN LAB, Lab 2 4
RESULTS
VGS (V)
0 -0.2 -0.5 -0.8 -1.0 -1.2 -1.5 -1.8 -2.0 -2.5
VDS (V) ID (mA)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
Table 2-1
VGS (V) -2.5 -2.0 -1.8 -1.5 -1.2 -1.0 -0.8 -0.5 -0.2 0
ID (mA)
Table 2-2
EEEB141 ELECTRONICS DESIGN LAB, Lab 2 5
POST LAB DISCUSSIONS
1. Plot drain characteristics graph (ID (mA) versus VDS (V)) for this JFET (all VGS in one graph).
2. Describe the characteristic curve by its VGS value. Is it what you expected?
3. Plot a transfer characteristic graph (ID (mA) versus VGS (V)) for this JFET. 4. Identify VP (pinch-off voltage) and IDSS (saturation current) in the graph of question 3.
(VP = VGS, when ID = 0mA. IDSS = ID, when VGS = 0V)
STUDENT’S CONCLUSION
Free Plain Graph Paper from http://incompetech.com/graphpaper/plain/
Free Plain Graph Paper from http://incompetech.com/graphpaper/plain/
