L3 Data Object

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8/6/2019 L3 Data Object http://slidepdf.com/reader/full/l3-data-object 1/15 1 Data Object Object Types A VHDL object consists of one of the following:  ±Signal, Which represents interconnection wires that connect component instantiation ports together.  ±Variable, Which is used for local storage of temporary data, visible only inside a process.  ±Constant, which names specific values.

Transcript of L3 Data Object

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    Data Object

    Object Types

    A VHDL object consists of one of the

    following:Signal, Which represents interconnection wires

    that connect component instantiation ports

    together.

    Variable, Which is used for local storage of

    temporary data, visible only inside a process.

    Constant, which names specific values.

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    Objects Objects are used to represent & store the data in

    the system being described in VHDL.

    Object contains a value of a specific type.

    The name given to object is called identifier.

    Each object has a type & class.

    Class indicates how the object is used in the model &what can be done with the object.

    Type indicates what type of data the object contains.

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    Every data object belongs to one of the following

    three classes:

    1. Constant: An object of constant cla^s can hold a singlevalue of a given type. This value is assigned to the object

    before simulation starts and the value cannot be changedduring the course of the simulation.

    2. Variable: An object of variable class can also hold a singlevalue of a given type. However in this case, differentvalues can be assigned to the object at different times usinga variable assignment statement.

    3. Signal: An object belonging to the signal class has a pasthistory of values, a current value, and a set of futurevalues. Future values can be assigned to a signal objectusing a signal assignment statement.

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    Signal objects can be regarded as wires in a

    circuit while variable and constant objectsare analogous to their counterparts in a

    high-level programming language like C or

    Pascal. Signal objects are typically used to model

    wires and flip-flops while variable and

    constant objects are typically used to model

    the behavior of the circuit.

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    Signal Signal objects are used to connect entities

    together to form models.

    Signals are the means for communication ofdynamic data between entities.

    A signal declaration looks like this:

    Signal Signal_name : Signal_type [:= initial_value]

    The Keyword SIGNAL is followed by one or more signalnames.

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    Each Signal name creates a new signal.

    Separating the signal names from the signaltype is colon.

    Signal type specifies the data type of theinformation that the signal contains.

    The signal can contain an initial valuespecifier so that the signal value mayinitialized.

    Signals can be declared in entity declarationsections, architecture declarations andpackage declarations.

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    Signals in package declaration are alsoreferred to as global signals because they

    can be shared among entities.

    Each signal has a history of values I.e. holdsa list of values which include current value

    of signal & set of possible future values

    that are to appear on the signal.

    Computed value is assigned to signal after

    delay called delta delay.

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    SignalDec

    larations

    Here are some examples of signal

    declarations.

    signal CLOCK: BIT;

    signal DATA_BUS: BIT_VECTOR(0 to 7);

    signal GATE_DELAY: TIME := 10 ns;

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    Variable Variable are used for local storage in

    process statements and subprograms.

    All assignment to variable occur

    immediately.

    A variable declaration looks like this:

    Variable variable_name: variable_type [: value]

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    The keyword VARIABLE is followed by one or

    more variable names.

    Each name creates a new variable.

    The construct variable_type defines the data type

    of the variable, and an optional initial value can

    be specified.

    Variable can be declared in the process declaration

    and subprogram declaration sections only.

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    Variable are inherently more efficientbecause assignments happen immediately,

    while signals must be scheduled to occur.

    Variables take less memory, while signals

    need more information to allow for

    scheduling and signal attributes.

    Using a Signal would have required a

    WAIT statement to synchronize the signalassignment to the same execution iteration

    as the usage.

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    Variable DeclarationsExamples of variable declarations are

    variable CTRL_STATUS: BIT_VECTOR(10 downto 0);

    variable SUM: INTEGERrange Oto 100 := 10;

    variable FOUND, DONE: BOOLEAN;

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    Signal vs Variables A Signal has three properties attached to it: type, value and

    time.

    while a variable has only two properties attached to it typeand value.

    Use signals as channels of communication betweenconcurrent statement. In non-synthesizeable models, avoidusing signals to describe storage elements. Use variableinstead.

    Signals occupy about two orders of magnitude morestorage than variable during simulation. Signals also cost aperformance penalty due to the simulation overheadnecessary to maintain the data structures representingsignals.

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    Constants Constant objects are names assigned to

    specific values of a type.

    Constants give the designer the ability to

    have a better-documented model, and a

    model that is easy to update.

    Constant declaration :

    Constant constant_name : type_name [:value];

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    Constant Declarations

    Examples of constant declarations are

    constant RISE_TIME: TIME := 10ns;

    constant BUS_WIDTH: INTEGER := 8:

    An example of another form of constant declarationis

    constantNO_OF_INPUTS: INTEGER;

    The value of the constant has not been specified in

    this case. Such a constant is called a deferredconstantand it can appear only inside a packagedeclaration.