L25-InstructCyclePipelining

8/6/2019 L25-InstructCyclePipelining

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Indirect Cycle

May require memory access to fetch operands Indirect addressing requires more memory

accesses

Can be thought of as additional instructionsubcycle


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Instruction Cycle with Indirect cycle


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Instruction Cycle State Diagram


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Data Flow (Instruction Fetch)

Depends on CPU design In general:

Fetch

PC contains address of next instruction Address moved to MAR

Address placed on address bus

Control unit requests memory read Result placed on data bus, copied to MBR, then to

IR

Meanwhile PC incremented by 1


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Data Flow (Fetch Cycle)


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Data Flow (Data Fetch)

IR is examined, to determine if the operanduses indirect addressing.

If so, indirect cycle is performed

Right most N bits of MBR transferred to MAR Control unit requests memory read

Result (address of operand) moved to MBR


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Data Flow (Indirect Cycle)


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Data Flow (Interrupt)

Simple Predictable

Current PC saved to allow resumption after interrupt

Contents of PC copied to MBR

MBR written to memory

PC loaded with address of interrupt handling routine

Next instruction (first of interrupt handler) can be

fetched


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Data Flow (Interrupt Cycle)


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Instruction Pipelining


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Prefetch Fetch involves accessing main memory

Execution usually does not access main

memory

So we can fetch next instruction during

execution of current instruction

Called instruction prefetch


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Two Stage Instruction Pipeline


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Improved Performance But not doubled:

Fetch usually shorter than execution

Prefetch more than one instruction?

Any jump or branch means that prefetched

instructions are not the required instructions

Add more stages to improve performance


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Fetch instruction

Decode instruction

Calculate operands

Fetch operands

Execute instructions

Write result

Overlap these operations

Pipelining


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Timing Diagram for

Instruction Pipeline Operation


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The Effect of a Conditional Branch on

Instruction Pipeline Operation


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Six Stage

Instruction Pipeline


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Dealing with Branches

Multiple Streams Prefetch Branch Target

Loop buffer

Branch prediction Delayed branching


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Multiple Streams

Replicates the initial portions of pipeline & allowpipeline to fetch both the instructions of branchinstruction

Have two streams

Prefetch each branch into a separate streams

Leads to bus & register contention

Multiple branches lead to further pipelines being

needed Despite these drawbacks, this strategy can improve

performance

Used by IBM 3033 and IBM 370/168


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Prefetch Branch Target

Target of branch is prefetched in addition toinstructions following branch

Keep target until branch instruction is

executed Used by IBM 360/91


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Loop Buffer

It is a small, Very high speed memory Maintained by instruction fetch stage of

pipeline

Contains n most recently fetched instruction,in sequence.

If branch is to be taken, h/w first checks for

the branch target in the buffer

Very good for small loops or jumps

Similar to a cache dedicated to instructions

Used by CRAY-1


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Branch Prediction

Predict never taken Assume that jump will not happen

Always fetch next instruction

68020 & VAX 11/780

Predict always taken Assume that jump will happen

Always fetch from the branch target instruction

Predict by Opcode Processor assumes that branch will be taken for

certain branch opcodes and not for others

Can get up to 75% success


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Taken/Not taken switch Based on previous history

One or more bits can be associated with each CBI thatreflect the recent history of the instruction

Good for loops

Branch History Table

A small table is maintained for recently executed branch

instructions with one or more bits in each entry

Good for loops

Delayed Branch Pipeline performance may be improved by rearranging

instructions within program, so that branch instructions

occur later.


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Branch Prediction Flowchart


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Branch Prediction State Diagram


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Dealing With

Branches

L25-InstructCyclePipelining

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