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Assignment

write a short notes on1. Manufacturing Testing.2. Functional Testing.3. Files and Text I/O.4. Differentiate the cpld and fpga

architecture.

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Test Benches

Testing a design by simulationUse a test bench model

an architecture body that includes an instanceof the design under test

applies sequences of test values to inputs monitors values on output signals

either using simulator or with a process that verifies correct operation

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Test Bench Exampleentity test_bench isend entity test_bench;

architecture test_reg4 of test_bench issignal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;

begindut : entity work.reg4(behav)

port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );stimulus : process isbegin

d0

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IntroductionWhat is a VHDL test bench?Test bench structures

Examples

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What Is The VHDL Test Bench (TB)?VHDL test bench (TB) is a piece of VHDL code, which

purpose is to verify the functional correctness of HDL model.

The main objectives of TB is to: Instantiate the design under test (DUT)

Generate stimulus waveforms for DUT Generate reference outputs and compare them with

the outputs of DUT Automatically provide a pass or fail indication

Test bench is a part of the circuits specification.Its a good idea to design the test bench before the

DUT, why?

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S timulus and ResponseThree ways how TB can generate the stimulus:

Generate them on-the-fly Read vectors stored as constants in an array Read vectors stored in a separate system file

Response is produced in the test bench.Response can be stored into file for further

processing.

Example:

S timulus can be generated with Matlab and TB feedsit into DUT.

DUT generates the response and TB stores it into file. Result can be compared to Matlab simulations.

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Test Bench S tructuresTB should be reusable without difficult modifications.The structure of the TB should be simple enough sothat other people understand its behaviour.Good test bench propagates all the generics and

constants into DUT.Question: How to verify that the function of the testbench is correct?

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S imple Test BenchOnly the DUT is instantiated into test bench.S timulus is generated inside the test benchPoor reusability.S uitable only for relatively simple designs.