CSE464 Digital Systems EngineeringL0: Logistics and Introduction

David M. ZarComputer Science and Engineering

Washington Universitydzar@wustl.edu

(Based on Original Work of Fred Rosenberger)

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Logistics EE464, Spring 2009Lectures: MW 2:30-4:00 in Urbauer 116Textbook: Dally and Poulton, Digital Systems EngineeringGrading: Approximate weighting for grade determination

25% Homework (exams based on homework)35% First midterm exam 45% Final exam

Collaboration: Academic integrity will be taken seriously. You may collaborate on homework with other students, use solutions from last year, or get help from anyone but you are to state who you worked with or got help from, and give an estimate of contribution from other sources to what you submit. This is just acknowledgement of source of material, and recognition of the work contributed by others, it has no effect on your grade. Exceptions to this rule will be specified in the assignments. Tests and projects are to be entirely your own work.

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More LogisticsExams: Closed book. One handwritten (no photocopies) sheet (both

sides) allowed on first exam, two sheets final exam.

Homework: Usually due in class (2:30 p.m.) one week after assignment

Instructor: David M. ZarBryan 307C GPS: N38 38.979' W90 18.360' Elevation: 550' Office Hours: by appointment.dzar@wustl.edu (best contact method)http://www.cse.wustl.edu/~dzar

Attendance: Class attendance is important, material willcovered in class that is not in text. You willwish to get copies of notes from classmate ifyou miss class.

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Discussion Topics

Class attendanceClass participation (please!)Dally (Dally, not Daily) lecture notesTextbook cost, errata, etcHomework length and styleEE314: Engineering Electromagnetics 1: FundamentalsGoal: Extremely practical backed up by theory and analysis

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Interesting Links and Sources– Links

http://www.signalintegrity.com/ (recommended by Fred)http://www.nesa.com/http://www.sigrity.com/http://www.ultracad.com/ (careful here)http://www.automata.com/ (careful here, some calculations are wrong)http://groups.yahoo.com/group/si-list (this is the signal integrity mailing list archive; lots here, good and bad)

– Books– High-Speed Digital Design, A Handbook of Black Magic, Howard W. Johnson

and Martin Graham, Prentice Hall, ISBN 0-13-395724-1, 1993.– High-Speed Signal Propagation, Advanced Black Magic, Howard W. Johnson

and Martin Graham, ISBN 0-13-084408-X, 2003– Brooks, Bogatin, Ritchey, Granberg, ...– Transmission Lines with Pulse Excitation, Georges Metzger and Jean-Paul

Vabre, Academic Press, New York, NY, 1969. (Bergeron Diagrams)

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Today’s AssignmentReading» Complete before Wednesday, Jan 21 class

– Preface, Chapter 1» Complete before Monday, Jan 26 class

– Chapter 2» Complete before Wednesday, Jan 28 class

– Chapter 3, Sections 3.1 through 3.3.3

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Digital Systems EngineeringFrom Dally

» noise management– keeping signals clean

» signaling– moving bits from here to there

» timing– how we know when a new bit is here

» power distribution– DC voltage with AC current

» Signal integrity– High-Speed signals– low speed signals– reset– …– All Signals

» Signaling (electrical representationof signals)

» Timing/Clocking» Power distribution» Cooling/Packaging as part of

aboveRules of Thumb (e.g.: C/inch, L/inch)

Analytical/Calculation

Simulation (HSPICE)

Measurement

Tools (don’t be a “tool driver”):

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WiresAdvanced components: WiresCare and feeding of wiresWires can be expensive, even if it’s a scam» http://www.monstercable.com» http://www.jpslabs.com/aluminata.shtml (they claim

“Pricing- If you have to ask.”)– "The shear mass of the particle shield alone proves that JPS has the

transfer of noise taken care of- Nothing gets through this cable's shield and into the conductors beneath- NOTHING... "

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Why is Digital Systems Engineering/Design Harder Now Than Previously?

Wires are not ideal (never were, but valid approximation sometimes) !!!Gross Simplification here:

Long wires or High-Speed Design (delay ~> 0.1 Clock Period)» 1968 1 MHz; >40 ft» 1978 10 Mhz; >4 ft» 1988 100 Mhz; >5 inches» 1998 1 GHz; >0.5 inch» 2008 10 GHz??? >0.05 inch» 2018 ????? » Overall size of system? approximately constant

Ad hoc methods that worked in the past now failTo paraphrase Roy Jewell, President of TMA: “The rules of physics don’t change for high-speed design, they are just more strictly enforced”.The fact that long wires are harder to deal with does not imply short ones are easy, nor that they can be ignored.The fact that high-speed signals are harder to deal with does not imply that slow ones are easy, nor that they can be ignored (e.g. Reset).EMI: Even harder, we will not deal with this in CSE464.

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Outrageous StatementsPropagation delay to closer device is longerSlower is better (and faster)A capacitor is an inductor unless you want inductor» Converse for inductor (or resistor)

Short wire is worse than long one (e.g. probe)Negative characteristic impedance?Square corners on PC traces are bad?Vias on PC traces are bad?Resistor networks: Bad?We could not use perfect logic (Midas touch)!Tune your absurdity detector!!!

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Thoughts to Remember (Models)A model is an artifice to make you think you understand a problem better than you actually do.All models are wrong, but some models are useful.Make everything as simple as possible, but no simpler (A. Einstein).In theory there is no difference between practice and theory, but in practice there is!An approximate answer to the right question is worth a good deal more than the exact answer to an approximate problem. John Tukey (FFT Fame)Models are a really dangerous (and necessary) toolExample: ground, ideal ground, logic ground, safety ground, …

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Ground is FictionAt low frequency and low accuracy ground is a convenient modelBe very carefulWhat is “ideal ground” (see si-list)?: “What you draw with chalk on a blackboard!”

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Bonus: Safety Ground

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What is Wrong Here?

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Lots!!!

Try to avoid surprises!!!

What worked last time may not work this time!

What is Wrong Here?

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SurprisesInvalid AssumptionsIndividual effects don’t add linearlyConsider effects one at a time, not the sum» Coupling from multiple sources (lines)» PS noise» Reflection noise» Component tolerances» Temperature» Process» PC board noise» Package noise» Connectors» Vias

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More SurprisesMultiple backward xtalk coupling, increased VUnaccounted for parasitics» Inductance» Resistance» Capacitance» ESR, ESL

Nonlinearities» Series termination with Capacitance load» Driver resistance when switching (1/4 wave)

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Still MoreTransmission line Manufacturer data sheetsStubsSplit load and standing waveLayout rules/communication/slip-upTolerancesT-line traces, return currentsR and C functions of frequency

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Last of Surprises?System cost

Vs. Design timeVs. Manufacturing timeVs. Reliability

Metastability

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Digital Systems EngineeringDesigning systems that work by design, not by trial and error, with reasonable cost (dollars, time, effort, …). Using appropriate tools (analysis, simulation, measurement) to insure correct operation. Avoiding surprises.Question: which is better?» Guess/Estimate?» Analysis (e.g. equations and calculation)?» Simulation (e.g. HSPICE)?» Measurement (e.g. oscilloscope, TDR)?