Kyungsoo LEE, Hideki TAKASE and Tohru ISHIHARA1.2V 1.2V PLL 100MHz CPU GBI core DMAC Level Shifter...
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Results: 20~70% Reduction of power loss Charger DC-DC DC-DC … Load Load Energy harvesting … DC-DC Energy Harvesting Board Application Board 2. Simple control with MPPT - Power pass configuration - Amount of charge/discharge control 1. The voltage of energy source - Dynamic array configuration - Solar cell and supercapacitor array 3. I/O aware task scheduling A Holistic Approach to Power Management for Energy Harvesting Embedded Systems Kyungsoo LEE, Hideki TAKASE and Tohru ISHIHARA Multiple-Performance Processor • Dynamic Voltage and Frequency Scaling • Dynamic Reconfigurable Cache Structure Grant: Japan Cabinet Funding Program for Next Generation World-Leading Researchers Target: Embedded computer system Goal: Battery-less operation of the system Approach: improving the efficiency of energy generation, transfer and consumption, MPP (multi-performance processor) Project Overview Research Topics Onodera-Laboratory OS-based Energy Management PV VI curve Efficiency of DC-DC converter Output voltage (V) Output current (mA) IV curve PV curve Output power (mW) 400 0 100 200 300 500 80 0 20 40 60 100 MPP (5.08V, 81.8mA) Power loss (mW) Voltage di↵erence (V in - V out ) Efficiency (%) 100 75 50 25 0 100 75 50 25 0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 Power loss at 10 mA output Power loss at 100 mA output Efficiency at 10 mA output Efficiency at 100 mA output Energy Harvesting System • High efficiency by concerning the transferring efficiency Reduce voltage difference by the array reconfiguration I/O aware task scheduling GBI DMAC Global Bus 8KB 4KB D-SPM I-SPM I-cache 4-way 50MHz Tag 2KB 2KB 2KB 2KB 4KB 200MHz CPU core 8KB 0.7V (based on AHB) 1.2V 1.2V PLL 100MHz CPU core GBI DMAC Level Shifter 1.2V Low-power CPU : 1.65μs High-speed CPU : 1.48μs 0 6.25 12.50 18.75 25.00 1 101 201 301 401 501 601 701 801 901 1001 1101 1201 1301 1401 0.7V core(mW) 1.2V core (mW) 3.3V IO(mW) Nonmanage Static Dynamic Policy 0.7V CPU 1.2V CPU 3.3V I/O Total (mW) Nonmanage 0.38 11.80 8.26 20.45 Static 0.58 9.50 5.80 15.88 Dynamic 0.73 7.47 2.66 10.87 31.6% 23.3% Processor Operation DVFS time Transmeta Crusoe 1.1V – 1.65V 300μs AMD Mobile K6 0.9V – 2.0V 200μs Intel PXA250 0.85V – 1.3V 500μs TI TMS320C55x 1.1V – 1.6V 3.2ms (1.6V → 1.1V) 300μs (1.1V → 1.6V) UCB [1] 1.2V – 3.8V 520μs *from Shin, D. and Kim, J., IEEE Trans. on CAD, 2005. [1] Burd, T. and Brodersen, R. W., ISLPED, 2000. • Proposed MPP architecture Configurat tion Power (m mW) Core Cache Low voltage High voltage 3.3V I/O Total 1.2V, 200MHz 4-way 1.68 34 5.89 41.96 1.2V, 200MHz 1-way 1.65 16.2 6.11 23.93 0.7V, 100MHz 4-way 2.65 18 5.88 26.4 0.7V, 100MHz 1-way 2.51 10.0 6.12 18.65 0.48V, 6MHz 1-way 0.04 0.18 0.66 0.88
Transcript of Kyungsoo LEE, Hideki TAKASE and Tohru ISHIHARA1.2V 1.2V PLL 100MHz CPU GBI core DMAC Level Shifter...
Results: 20~70% Reduction of power loss
Charger DC-DC
DC-DC
… Load
Load
Energy harvesting
…
DC-DC
Energy HarvestingBoard
Application Board
2. Simple control with MPPT - Power pass configuration - Amount of charge/discharge control
1. The voltage of energy source - Dynamic array configuration - Solar cell and supercapacitor array
3. I/O aware task scheduling
A Holistic Approach to Power Managementfor Energy Harvesting Embedded Systems
Kyungsoo LEE, Hideki TAKASE and Tohru ISHIHARA
Multiple-Performance Processor• Dynamic Voltage and Frequency Scaling• Dynamic Reconfigurable Cache Structure
Grant: Japan Cabinet Funding Program for Next Generation World-Leading Researchers
Target: Embedded computer systemGoal: Battery-less operation of the system
Approach: improving the efficiency of energy generation, transfer and consumption, MPP (multi-performance processor)
Project Overview
Research Topics
Onodera-Laboratory
OS-based Energy Management
PV VI curve Efficiency of DC-DC converter
0 2 4 6 8Output voltage (V)
Out
put c
urre
nt (m
A)
IV curve
PV curve
Out
put p
ower
(mW
)400
0
100
200
300
500
80
0
20
40
60
100 MPP (5.08V, 81.8mA)
Pow
er lo
ss (m
W)
Voltage di↵erence (Vin
� Vout
)
Effic
ienc
y (%
)
100
75
50
25
0
100
75
50
25
00
25
50
75
100
-1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5
Power loss at 10 mA outputPower loss at 100 mA outputEfficiency at 10 mA outputEfficiency at 100 mA output
Energy Harvesting System• High efficiency by concerning the transferring efficiency Reduce voltage difference by the array reconfiguration I/O aware task scheduling
GBIDMAC
Glob
al B
us
8KB
4KB
D-SPM
I-SPM
I-cache4-way
50MHz
Tag2KB2KB2KB2KB
4KB
200MHzCPUcore
8KB
0.7V
(bas
ed o
n AH
B) 1.2V
1.2V
PLL
100MHzCPUcoreGBI
DMAC
Level Shifter
1.2V Low-power CPU : 1.65µs High-speed CPU : 1.48µs
0
6.25
12.50
18.75
25.00
1 101 201 301 401 501 601 701 801 901 1001 1101 1201 1301 1401
0.7V core(mW)1.2V core (mW)3.3V IO(mW)
Nonmanage Static Dynamic
Policy 0.7V CPU 1.2V CPU 3.3V I/O Total (mW)
Nonmanage 0.38 11.80 8.26 20.45
Static 0.58 9.50 5.80 15.88
Dynamic 0.73 7.47 2.66 10.87 31.6%
23.3%
Processor Operation DVFS timeTransmeta Crusoe 1.1V – 1.65V 300μs
AMD Mobile K6 0.9V – 2.0V 200μs
Intel PXA250 0.85V – 1.3V 500μs
TI TMS320C55x 1.1V – 1.6V 3.2ms (1.6V → 1.1V)300μs (1.1V → 1.6V)
UCB[1] 1.2V – 3.8V 520μs
*from Shin, D. and Kim, J., IEEE Trans. on CAD, 2005.[1] Burd, T. and Brodersen, R. W., ISLPED, 2000.
• Proposed MPP architecture
ConfigurationConfiguration Power (mW)Power (mW)Power (mW)Power (mW)Core Cache Low voltage High voltage 3.3V I/O Total
1.2V, 200MHz 4-way 1.68 34 5.89 41.961.2V, 200MHz 1-way 1.65 16.2 6.11 23.930.7V, 100MHz 4-way 2.65 18 5.88 26.40.7V, 100MHz 1-way 2.51 10.0 6.12 18.650.48V, 6MHz 1-way 0.04 0.18 0.66 0.88
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