KM3NeT CLBv2
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Transcript of KM3NeT CLBv2
![Page 1: KM3NeT CLBv2](https://reader030.fdocuments.in/reader030/viewer/2022032612/568132f0550346895d99ab72/html5/thumbnails/1.jpg)
April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
1
KM3NeT CLBv2
![Page 2: KM3NeT CLBv2](https://reader030.fdocuments.in/reader030/viewer/2022032612/568132f0550346895d99ab72/html5/thumbnails/2.jpg)
April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Done:◦ Add AES sources to top level schematic
Newest sources from Antonio in place
◦ Inspect I2C timing issue with Octopus Done and understood (I2C abort command didn’t check for
completion)
◦ Add Multi boot sources to LM32_2nd and test SPI Flash Added (had issue with ICAPE2 optimization for Precision)
Currently:◦ Solve 4 ns issue
Solved but not completely understood…
◦ Clock stability test (in cooperation with University of A’dam)
◦ Get experience with measuring calibration parameters (in cooperation with Mar van der Hoek)
◦ Ethernet flow control (PAUSE frames) discussion with 7-Solutions and Athenes.
To do list:
2
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Soon:◦ Add StMachine, TDC sources to top level schematic◦ Prepare for system test◦ EMI test
Shouldn’t the registers of ICAPE2 in multiboot be readable and writeable in a generic way (mapped on the wishbone bus)? This opens the possibility to use all:
1. Warm Boot Start Address (mboot)2. Watchdog Timer3. Boot History Status
To do list:
3
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Clock stability tests (cooperate with UVA)
4
10 MHzreference
PPS
200 mbps
PPS
Other data
generators
Other data
generators
Measure long term stability
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Actual asymmetry measurement using WR
(measure unknown calibration parameters in cooperation with Mar van der Hoek)
Measurement 1
5
Round Trip Time (Rtt from WR GUI):◦ Rtt(f1) = D + df1
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3
df1 (= dMS + dSM)
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Measurement 2
6
Round Trip Time (Rtt from WR GUI):◦ Rtt(f1) = D + df2
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3
df2 (= dMS + dSM)
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Measurement 3
7
Round Trip Time (Rtt from WR GUI):◦ Rtt(f1) = D + df1 + df2
3 equations, 3 unknown => Now calculate:◦ D
◦ df1
◦ df2
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3
df1+ df2
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Measurement 4
8
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3df2
Knowing , D df1 and df2, => calculate lSC delay
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Measurement 5
9
Knowing , D df1 and df2, => calculate lDC delay
EDFA assymetry = lDC - lSC
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3df2
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
EMScan:EHX-42 150kHz-4GHz
EMC/EMI problems diagnostic tool
Ordered ½ MarchLead time 4-6 weeks=> Expected beginning of
May
CLBv2 EMI
10
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Discussion with 7 Solutions (and Athens).Pause implementation on layer-2 using
unicast MAC addresses instead of multicast.
An important item that popped up:◦ A DOM that requests pause will halt the broadcast
link if PAUSE is implemented on layer-2 (MAC).◦ This is a “feature” thanks to the broadcast
architecture.◦ DOM pause request should be maskable.
Pause request
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Backup slides
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April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
13
Accumulated hardware delays◦ D=DTXM+DRXS+DTXS+DRXM
Accumulated fiber delays◦ d= dMS + dSM
Asymmetry set to 0 for the time being… Trick: 3 Round Trip Time (Rtt from WR GUI) measurement, 2 fibers
◦ Rtt(f1) = D + df1
◦ Rtt(f2) = D + df2
◦ Rtt(f1+f2) = D + df1 + df2
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3
dMS
dSM
Rtt
Actual asymmetry measurement using WR(measure one of the unknown calibration parameters in
cooperation with Mar van der Hoek)
![Page 14: KM3NeT CLBv2](https://reader030.fdocuments.in/reader030/viewer/2022032612/568132f0550346895d99ab72/html5/thumbnails/14.jpg)
April 30, 2014 CLBv2, Vidyo
Peter JansweijerNikhefAmsterdamElectronics- Technology
Actual asymmetry measurement using WR(measure one of the unknown calibration parameters)
14
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3
KC705+SoftPLL KC705+SoftPLL
WR master WR slave
t1
DTXM DRXS
t2
DRXM DTXS
t4 t3
KC705+SoftPLL KC705+SoftPLL
WR master WR slave
Two measurements on the EDFAs in the node
Get hands-on experience