February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2...

February 26, 2014 CLBv2, Vidyo

Peter JansweijerNikhefAmsterdamElectronics- Technology

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KM3NeT CLBv2



White Rabbit SPEC-NIC (= “one-port switch”)

WR-Timing and Ethernet

WR-NIC

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PPS

Use SPEC with NIC firmware/software in Grand Master mode: http://www.ohwr.org/projects/wr-nic/wiki

PPS10MHz

PPSGPS Timing Reference

(Grand Master Mode)

http://www.ohwr.org/projects/wr-nic/wiki

http://www.ohwr.org/projects/wr-nic/wiki



Jumbo frames are not received…◦ This is also an issue for the WR switch V3.3!

Not all UDP packets are received:

According to Miguel Jiménez López this is a speed issue and we should look forward to a DMA core in wr-nic design

WR-NIC issues

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All 15 received by intel PRO/1000 PFOnly first 8 received by SPEC-NIC



WR-Timing and Ethernet (multi-port)

WR Switch

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PPSPPS

10MHzPPS

Use switch as is:◦ no broadcast (yet)◦ Standard firmware/software

Timing Reference

Grand Master Mode



NIKHEF has a pioneer switch that was not up to date.

We were not able to do the Flash procedure with out Ubuntu 12.04 machines (tried two)

Switch Core Board was returned to 7_Sols for flashing.

No problem found. Flashing okay.Flashing via laptop Ubuntu 13.04 sometimes

failed => cause unknown…According to 7-Sols there is a procedure

found to successfully flash 100% of the time.Received the SCB back just yesterday…

WR Switch

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Firmware integration

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Adding TDC, Hydrophone, connection to IPMUX, Multiboot => Still a lot of work to be done!

Empty State machine, David is working on it◦ => TDC and AES are optimized away by the synthesis

tool!

TDC sources in place

(Valencia)

AES sources in place

(Genova)

Empty place holder, (Valencia)



Firmware integrationother issues

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IPMUX UDP Channel connections:0: TDC1: AES2: Packet generator

15 UDP packets (data payload 2,4,6,… 30 bytes)

3: Packet generator 2 Jumbo UDP packets (data payload 8972 bytes)

◦ Note that Channel 2 and 3 connect to a push-button/dip-switch packet generator for test purposes.

Added a ref_clk_lock signal◦ Note that clk_sys is always running (62.5 MHz for LM32

and wishbone)◦ Ref_clk_62_5, ref_clk_125, ref_clk_250 may be

interrupted during WR startup. Pay attention to the ref_clk_lock signal!



Firmware integration

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Fruitful Vidyo: David, Vladimir, Antonio, Peter◦ But… still some confusion to solve!

StMachine:◦ Chops data into UDP packet size chunks. Packets

get Time-Slice info and index number◦ StMachine does not know the data type (although

it should know the data word size (n*16-bits)AES Frame = all audio for one Time-Slice

◦ First UDP packet of a Time Slice contains the AES-Info word.

◦ This is the most straightforward implementation!◦ If first packet gets lost you lose Audio for one

Time-Slice (although audio samples can still be re-processed offline). Is this acceptable?



Thermal Pictures CLBv2-Proto

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Running WR PTP in TRACK_PHASE◦Ambient ~ 23 degrees ◦FPGA ~ 36 degrees◦“Hot Spot” ~ 37 degrees (Clock driver U4)



Thermal Pictures CLBv2-Proto

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Running WR PTP in TRACK_PHASE



Thermal Pictures PBv2.1

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Ambient ~ 23 degrees Fully loaded:

◦ 1V0 => 3A◦ 1V8 => 1A◦ 2V5 => 1A◦ 3V3 => 3A◦ 3V3 PMT => 1A◦ 5V => 1A

“Hot Spot” switchers ~ 38 degrees



Thermal Pictures PBv2.1

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Questions?

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Backup SlidesMore details…

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February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2...

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