Kamath Pole Zero

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1/6

IEEEJOURNAL OF SOLID STATECIRCUITS VOL. SC Q NO. 6 DECEMBER1974

[51 R. A. Stehlin and G. W. Niemann, “Complementary tran-

sistor-transistor logic CTzL —an approach to high-speed

micropower logic,” I EEE J . Sol id State Ci rcu i ts vol . SC 7

p p. 153–160, Apr . 1972.

Paul C. Davis S’64 -M’61 wa s born in

G lenville, W. Vs., on Ma rch 14, 1937. He

received the B .S .E E . degree from West

Virginia U niversity , Morga nt ow n, in 1959,

th e M.S . degree from Ma ssa chuset t s Inst i-

t ut e of Tech nology , C am br idge, in 1961, a nd

th e P h.D . degree in elect r ica l engineer ing

from Lehigh U niversit y, B et hlehem, P a., in

1968.

He ha s been a Tea ching Assista nt a t

M.I .T. a nd served tw o yea rs a s a n a rmy

officer in t he Ordna nce G uided Missile S chool, H unt sville, Ala .

In 1962 he became a Member of the Technical Staff Bell Labora

tories Reading Pa. He has been engaged in characterization

and modeling of transistors and in the design of linear and digital

integrated circuitry.

Dr. Davis is a member of Eta KapDa Nu and Tau Beta Pi and

a n a ssocia t e member of Sigma Xi. “ -

Rela t ion sh ip B etween

7

Stanley F. Moyer wa s born in Hamburg,

P a., on Sept ember 8, 1931. He gra dua ted

from Ca pit ol Ra dio E ngineer ing Inst it ute,

Wa shington, D .C. in 1956. He ha s a lso a t-

t ended Albright College, Rea ding, P a .j a nd

La fa yet te C ollege, E aston, P a.

I n 1956 h e join ed B ell L abora tories, R ea d-

ing, P a ., w here he ha s worked on the

development of germa nium diffused ba se

t ra nsistors, silicon tra nsistors, a nd field-

effect

transistors. Since 1966 he has worked

on the development of silicon monolithic integrated circuits.

Veikko R. Saari

w a s bor n in B rooklyn , N.Y.,

on April 24, 1928. He received the B .S . a nd

M.S . degr ees in ph ysics fr om t he U niver sit y

of Minnesot a , Minnea polis, in 1951 a nd

1956, respectively.

S ince 1956 he ha s been working on the

design of solid-sta te circuit s a t B ell La b-

or at or ies, H olm del, N .J .

Mr. Sa a ri is a member of t he America n

Associa t ion of P h ysics Tea ch er s.

Freq uency Response a nd

Settl ing

‘Time of Oper ;t ion~ Amplifiers

B. YESHWANT KAMATH, STUDENTMEMBER, IEEE, ROBERT G. MEYER, MEMBER, IEEE, AND

PAUL R. GRAY, MEMBER, IEEE

Abstracf—The

effect s of pole-zer o pa ir s doublet s on t he fr e-

quency response a nd set t ling t ime of opera tiona l a mplifiers a re

explored using a na lyt ica l t echniques a nd comput er simula tion. I t

is sh ow n t ha t doublet s w hich prod uce on ly m in or ch an ges in circuit

fr eq uen cy r es pon se ca n pr od uce m a jor ch a ng es in set tlin g t im e. Th e

impor t a nce of doublet spa cing a nd frequency a re exa mined. I t is

show n tha t set t ling t ime a lwa ys improves a s doublet spa cing is

reduced w herea s the effect of. doublet frequency is different for

0.1 a nd 0.01 percent error ba nds. Fina lly it is show n tha t simple

a na lyt ica l formula s ca n be used to est ima te the influence of fre-

q uen cy d ou blet s on am plifier s et tlin g t im e.

I. INTRODUCTION

I

~ MANY

applications of operational amplifiers, the

settling time is an important parameter [1]. The

settling time is the time taken for the output of the

amplifier to settle to within 0.1 or 0.01 percent after the

Manuscript received May 13 1974; revised August 8 1974. This

work was supported by the Joint Services Electronics Program

under Contract F44620 71 C @187.

The authors are with the Department of Electrical Engineering

and Computer Sciences and the Electronics Research Laboratory

IJniversity of Cal ifornia Berkeley Calif . 9472Y3.

application of an input step. This test is usually done in

a unity-gain configuration with a 1O-V step input and

thus the error bands on the output are 10 and 1 mV, re-

spectively, for 0.1 and 0.01 percent accuracy. These tests

are important in specifying the operational amplifier for

use in such applications as A/D and D/A converters.

The settling time of an amplifier is composed of two

distinct periods [1]. The first period is called the slew

time during which the amplifier output makes the transi-

tion from the original output voltage to the vicinity of

the new value. During this period the amplifier acts in a

grossly nonlinear fashion and the length of this period

is generally determined by the current available to charge

the amplifier compensation capacitance. The second por-

tion of the settling time is the period after slew limiting

when the amplifier output is near its final value and the

circuit acts in a quasi-linear fashion. It has been shown

[2], [3] that this period is significantly affected by the

presence of pole-zero pairs called doublets in the am-

plifier transfer function. In high-speed operational ampli-

fiers, the slew time can be very short and this second


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348

IEEE JOURNAL OF SOLID STATECIRCUITS DECEMBER1974

F ig Oper at ion al a mplifier m od el for ca lcula tion of t ra nsien t

response

period in the quasi-linear region can dominate the set-

tling time of the amplifier.

The circuit behavior clescribed above is difficult to

evaluate in practice. Direct measurements of these as-

pects of amplifier performance are clifficult to perform

and the effects of different parameters in the circuit are

difficult to isolate. In this paper the effect of cloublets on

the frequency response and settling time of a fast opera-

tional amplifier is investigated using analytical tech-

niques and computer simulation.

II.

THEORY

Doublets in an amplifier transfer function can arise

from a number of causes. For example, bypassing one

side of an active loacl at high frequencies

[ ]

leads to

the introduction of a pole-zero pair with an octave sepa-

ration. The use of a feedforward capacitor to bypass a

lateral p-n-p transistor [2] can cause the creation of a

doublet with 30 percent mismatch between pole and

zero frequencies.

Previous analyses of the effects of a doublet have as-

sumed linear operation of the circuit in question [1] –

[3]. However, the application of a 1O-V step to an opera-

tional amplifier results in quite nonlinear operation dur-

ing the slewing period, and a linear analysis cannot be

justified for this case. A model which represents the situ-

ation in a practical amplifier is shown in Fig. 1. The am-

plifier is connected in a unity-gain feedback loop. The

differential input stage is modeled as shown with maxi-

mum available current 10 and a transfer characteristic

slope of g,m for values of ]V~l less than 10/0,,, }. For

values of IV~I > lO/g,~ , the input stage limits at a cur-

rent l.. This is the major source of nonlinearity in the

circuit during the transient response. A doublet is as-

sumed present in the amplifier frequency response to-

gether with the dominant pole produced by the compen-

sation capacitor. These are shown schematically in Fig. 1.

Since this portion of the circuit is assumed to act linearly,

the precise cletails of the circuit arrangement are not

critical, However, to conform to the practical example

considered later, a current II is assumed fed from the

input stage to the circuit producing the doublet, and a

current Iz is assumed fed from this circuit to the output.

The use of voltage variables does not change the results

of the analysis.

In this analysis, the higher frequency poles near ancl

beyond crossover have been neglected. These poles are

certainly important since they limit the bandwidth and

slew rate of the amplifier through the compensation

capacitor. They can also have a very strong effect on

settling time if the phase margin is allowed to become

too small. However, in an optimum design, these poles

will produce only a slightly underdamped response, and

this response will be short in duration compared to the

transients introduced by the doublet. A closely spaced

doublet is assmnecl and the doublet frequency is assumed

much less than the amplifier unity-gain frequency.

The circuit of Fig. 1 is analyzed in the Appendix

where it is shown that the response to a step input of

amplitude V is:

V.., t =

V l – k, exp [–co.ot] + k, exp [– t/r,)]),

for t

T, 1

where

2

1

‘r2?— 3)

Q.

T,

slewing period

W. doublet zero frequency

UP doublet pole frequency

COCOA X amplifier dominant pole) s unity-gain

bandwidth

A open-loop low frequency gain.

Equation 1) indicates the presence of a slow settling

component in the output with a time constant l/~,) and

a magnitude

kzV.

Equation 2) indicates that for a given

fractional doublet spacing for example, ~. = 1.3 Or) the

magnitude of the slow settling component is proportional

to the doublet frequency, and the magnitude of the input

step. However, 3) indicates that the time constant of

the slow settling component is inversely proportional to

the doublet frequency. Thus lower frequency doublets

will give a response which persists for a longer period

but with a smaller amplitude. Higher frequency doublets

will give a response which dies out faster but has a

larger amplitude. The relative importance of these trends

will depend on the particular situation. If settling to 0.1

percent only is important, a lower frequency doublet may

give a slow-settling component which is always within

the error band and thus does not degrade performance.

For settling to 0.01 percent the same doublet may cause

great increases in settling time. A higher frequency

doublet is likely to produce settling time degradation in

all cases but its effect will die away much sooner [3].

III. COMPUTER SIMULATION

The analytical expressions derived above use a greatly

simplified model of the operational amplifier. In order

to check the validity of these approximations and to

further investigate these effects, computer simulations

were performed on the PA 772 operational amplifier [2].

This amplifier was chosen because it is a high speed

amplifier with a fast settling time and the effects of


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I M TH et FREQUEN YRESPONSEAND SETTLING T1i f1

artificially introduced doublets are easy to distinguish.

The amplifier itself has a doublet due to the use of feed-

forward but a doublet compression scheme which is an

integral part of the amplifier makes the effect of this

doublet undetectable. In order to observe the effect of a

doublet on the response of the amplifier, one half of the

active load was bypassed with a capacitor in a similar

fashion to the LM 118 [4]. By varying the magnitude

of the capacitor and a resistor in series with it, doubleti

were introduced at different frequencies with different

pole-zero separations. The open-loop unity-gain fre-

quency was kept constant in all cases at OJCO 6.1 MHz

by small adjustments in the value of the compensation

capacitor. The compensation capacitor used was larger

Lhan the one in the original ,pA 772 to allow for these

adjustments.

The program used was the SPICE program developed

at the University of California, Berkeley. SPICE has a

general nonlinear transient analysis capability with com-

prehensive large-signal device models. The computed

open-loop gain and phase response for the basic ampli-

fier are shown in Fig. 2 a and b together with the

response when a doublet at 18 kHz is included. Even

with the addition of such a doublet with 32 percent mis-

match between pole and zero frequencies, the change in

the frequency response is small. For a smaller doublet

such as 8 percent pole-zero mismatch the effect on

frequency response is indiscernible on these scales. In

Fig. 2 c an expanded graph is shown of phase versus

frequency for the amplifier with and without doublets.

The doublets used here were at 18 kHz with pole-zero

mismatches of 32, 20, and 8 percent. It is apparent that

the 8 percent doublet has very little effect on the fre-

quency response, but it will be shown to have a signifi-

cant effect on the settling time.

In Fig. 3 a the computed transient response is shown

with a 1O-V input step –5 to +5 V for the original

circuit in a unity-gain voltage follower configuration. On

this scale, the addition of doublets produces an almost

imperceptible change in response. In Fig, 3 b , this re-

sponse is shown on an expanded scale to allow observa-

tion of 0.1 percent 10 mV settling time. This is seen

to be about 0.43 ,ps for the case of no doublet, with about

0.2 ps of this being slewing time and the rest being

caused by overshoot. Because of the neglect of higher

frequency poles, this overshoot is not predicted by the

analysis in the Appendix.

Also shown in Fig. 3 b are response curves with dou-

blets added to the amplifier. It is apparent that the

doublet at 180 kHz with 32 percent spacing produces the

worst degradation of settling time with a value of 1.56 ps.

The 32 percent doublet at 18 kHz gives a settling time of

0.80 ~s, even though it persists much longer due to its

longer time constant. The much smaller initial value of

the slow settling component due to the 18 kHz doublet

results in its decaying below 10 mV sooner than is the

case for the 180 kHz doublet.

9

120-

Gain

dB

1.32 Doublet

o t 18kHz

NO doublet

80-

40-

0

I

I

IHz IkHz 1MHz IO MHZ

Frequen t y

a

I iz

-90

Phase

1

degree

-954

-1oo“1

Ikiiz ‘

I MHz hlHz

Frequency

b

No doublet

T

1.08

1.2

Doublet Ot 18kHz

1 32

Ooublet spacing

1

IH: ‘

I I ’Hz

I M Hz 10idHz

Frequency

c )

Fig. 2. Computed open-loop frequency response of the amplifier

with and without doublets. a Gain versus frequency. b

Phase versus frequency. c Expanded Pha* versus freWencY.

The graphs

of

Fig. 3 b are shown even further ex-

panded in Fig. 3 c so that 0.01 percent 1 mV settling

times can be determined. In this case, for any given

fractional doublet spacing, the lower frequency doublet

has by far the worst effect on settling time. This possi-

bility was pointed out in Section II. Even though the

higher frequency doublets give larger initial amplitudes

of the slow settling component, the very slow decay for

the lower frequency doublets makes them much more

significant for l-mV settling time, The worst case is for

the 32 percent doublet separation at a frequency of 18

kHz giving a l-mV settling time of 14.14 ps.

These results are illustrated in Fig. 4 where computed

settling times are shown as a function of doublet spacing


4/6

5Q

IEEE JOURNAL OF SOLID STATECIRCUITS DECEMBER1974

I

5.0

L

0.0

1.32 Do,blel al 180kHz

1 .3 2 D oubl et o f 1 8k Hz

\

0.5 No d~~bl~, 1.0

1,5 2,0

T ime ~sec

a

No doublet

I

\

L

1

1

1.5 2.0

Time [pee}

c

Fig. 3. C omput ed unit y-ga in t ra nsien t response of t he a mpI ifier

to a 1O-V input st ep from —5 to + 5 V, a Linea r volt a ge

sca le. b a nd c E xpa nded volt age sca J e.

Doublet at 18

z

Settlhg to

I mV

180 kHz

180 kHz

10mV

18kHz

1

r

1.1 1.2

1

1.3

b)

Doublet spacing , @z I Up

F ig. 4. C om put ed u ty g ain set tlin g t im e ver su s dou blet s pa cin g

for t wo differ en t doublet fr eq uen cies a nd set tlin g a ccur acies,

Input st ep from –5 t o + -5 V.


5/6

KAMATH f?Ctl FREQUENCYRESPONSEAND SETTLINGTIME

351

TAB LE I

Doublet

ktv,

10-mV Settling Time

Spacing

l -mV Se t t ling Time

(2) (mV)

(J s)

(W)

computer

predicted

computer

predicted

computer

predicted

computer

predicted

Doubl et a t

1.08 8.09 8.14

2.46

2.28

18 kHz 1.2

0.44

6.53

0,47

7.29

7.3

6.7

6.25

5.81 0.48

1.32 6.15

0.51

6.88

12.0

9.97

12.8

9.19 0.80 0.57 14.2 15.2

Doubl et a t

1.08 0.825 0.812

24.6

24.2

180 kHz 1.2

0.77

0.708

0.72

0.726

2.62

67.2

2.59

62.9

1.32

1.34

0.654

1.34

0.683

3.01 3.01

106 98.7 1,56

No Doublet

1.56 3.05 3.14

0.43

0.56

for t w o d iffer en t doublet fr eq uen cies (18 a nd 180 kH z).

Th is sh ow s clea rly t ha t for 10-mV set tling, t he 180-kH z

doublet gives the w orst degra da tion w herea s for l-mV

set tling t he long t ime consta nt a ssocia ted w it h t he 18-

kH z doublet ca uses t his t o be t he w or st ca se. These t est s

w ere repea ted for nega t ive st eps from + 5 to –5 V a nd

sim ila r r es ult s w er e obt a in ed .

Th e compu ted r esu lt s a re summ ar ized in Ta ble I . Th e

consist ent t rend tow ards sma ller set t ling t ime is a p-

pa rent a s t he doublet spa cing is reduced. Also show n in

Table I a re va lues of ., a nd

k2V

ca lcula ted fr om (2)

a nd (3) t oget her w it h va lues det erm ined from t he com-

puted responses. The va lues of ~ z w ere simply det er-

mined from the t a il of the exponent ia l deca y a nd the

va lu es of

k2V

w ere det ermined by ext ra pola ting ba ck

from the region of the exponent ia l deca y. Quite close

a gr eem en t is seen in t he va lu es d et ermin ed fr om t he t w o

methods.

Fina lly , Ta ble I show s ca lcula ted va lues of set t ling

t ime using (1). These show good a greement w ith the

computed v a lues .

IV. CONCLUS IONS

I t ha s been shown tha t frequency doublet s in the

t ra nsfer funct ion of a n opera tiona l a mplifier ma y ca use

severe degra da tion of set tling t ime w hile only ca using

minor cha nges in the frequency response of the a mpli-

fier . The effect of t he doublet depends bot h on it s fre-

q uen cy a n d t he pole-zer o spa cin g. R ed uct ion of t he pole-

zero spa cing of the doublet reduces it s effect , but

pole-zero freq uency m isma tches a s sm all a s 8 percent

ca n ca u se sig nifica nt in cr ea ses in set t lin g t im e.

The effect of t he doublet freq uency on set tling t ime is

more complex. For 0.01 percent set t ling, a low er fre-

q uen cy d ou blet ca n pot en tia lly ca u se t he w or st per form-

a n ce d eg ra da t ion b eca u se of it s lon g t im e con st a nt . H ow -

ever, for 0.1 percent set tling, t he sma ller a mplit ude of a

lower frequency doublet ma y mea n tha t it is a lw a ys

w ithin t he error ba nd a nd ha s lit t le effect . In t ha t ca se a

‘h ig her fr eq uen cy d ou blet w ou ld ca u se mor e set t lin g t im e

d eg ra da t ion beca u se of it s la r ger amplit ud e, even t hou gh

it d eca y ed f a st er .

Fina lly , it ha s been show n quite genera lly tha t the

simple formula s derived here ca n be used t o predict t he

in flu en ce of fr eq uen cy d ou blet s on oper a tion a l amplifier

s et t li ng t ime.

APPENDIX

The circuit of Fig. 1 is to be a na lyzed for a st ep input

of ma gn it ude

V

wher e in g en er a l

v > I ,/g..

(4)

I n t his sit ua tion , t he init ia l volt age Vd a pplied t o t he

d iffer en tia l in pu t st a ge is s ufficien t t o ca u se lim it in g a n d

a const ant current 10 is supplied t o t he doublet a nd out -

put st age. C om put er simula tion show s t ha t in pra ct ice

t his occurs. The period w hen t he input st age is limit ing

represent s t he slew ing period of the a mplifier a nd t he

feedba ck loop is effect ively open during this period.

When t he out put volt age

Vo,,t

a ppr oa ch es w it h in

I o/ gm

of

V,

t he different ia l st age ent ers it s linea r region a nd

t he a mplifier set tles t o it s fina l va lue w it h t he feedba ck

loop closed. Assumpt ions ma de a re t ha t the doublet is

closely spa ced a nd the doublet frequency is much less

t ha n t he amplifier unit y-ga in fr eq uen cy , i.e., ~ .


6/6

352

IEEEJOURNALOFSOLID-STATEIRCUITS,ECEMBER

1974

t he d iffer en tia l in put st a ge en ter s it s lin ea r r egion . The

w hole amplifier t hen begins set tling a s a lin ea r feedba ck

loop w it h in it ia l cond it ion s d et ermined a s follow s.

11(7’ ) = 10

(lo)

V.”,(Z’J = v – :.

(11)

Using

exp [—oJ,z’.] 1 — COOT,

(12)

a nd

exp

[–m../ A)T ,] N

1 – ‘~ ~

T ,,

(13)

in (9) we ha ve

(14)

~, ~

/ 6 )= )– 1

2

1- JiJ ‘1 + ““T’ ”

24)

For t ypica l componen t v a lu es wf iT .

Kamath Pole Zero

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