IXP Lab 2012: Part 3

IXP Lab 2012: Part 3

Programming Tips

Outline

• Memory Independent Techniques– Instruction Selection– Task Partition

• Memory Dependent Techniques– Reducing Overhead• Reduce the number of memory accesses• Reduce average access latency

– Hiding Overhead

NCKU CSIE CIAL Lab 2

Memory Independent Techniques

• Instruction Selection– General Coding Skill– Use Hardware Instruction

• Task Partition– Multi-Processing– Context-Pipelining


General Coding Skill

• Remove loop• Shift Operation– Avoid using multiply and divide

• Inline Function– __inline & __forceinline

• Branch Prediction– Branch Prediction Penalty


Hardware Instruction

• POP_COUNT• FFS• Multiply• CRC• Hashing• CAM


POP_COUNT--Brief

• Population Count• Report number of bit set in a 32-bit register• 3 cycles latency• Example:– pop_count( 0x3121 ) = ?– 0011 0001 0010 0001– Result = 5


POP_COUNT--Naïve Implementation

unsigned int pop_count_for (unsigned int x){ unsigned int y=0; unsigned int i;

for(i=0; i<32; i++) { if( (x&1)==1 ) y++; x=x>>1; } return y;}


POP_COUNT--Faster Implementation

unsigned int pop_count_agg(unsigned int x){

x -= ((x >> 1) & 0x55555555); x = (((x >> 2) & 0x33333333) + (x & 0x33333333)); x = (((x >> 4) + x) & 0x0f0f0f0f); x += (x >> 8); x += (x >> 16); return(x & 0x0000003f);}}

Reference http://aggregate.org/MAGIC/


http://aggregate.org/MAGIC/

POP_COUNT--Hardware Instruction

unsigned int pop_count_hardware(unsigned int x)

{return pop_count (x);

}


POP_COUNT--Additional Information

• Bitmap-RFC (Liu, TECS 2008)


FFS

• Find the first bit set in data and return its position• Example:– ffs ( 0x3121 ) = 0

• 0011 0001 0010 0001

– ffs ( 0x3120 ) = 5• 0011 0001 0010 0000

– ffs ( 0x3100 ) = 8• 0011 0001 0000 0000


Multiply

• Specific Multiply Instruction– Multiply_24x8()– Multiply_16x16()– Multiply_32x32_hi()– Multiply_32x32_lo()


CRC

• 14 cycles latency• Example of CRC operation

crc_write( 0x42424242);crc_32_be( source_address, bytes_0_3 );crc_32_be( dest_address, bytes_0_3 );…

Cache_index = crc_read();


Hash

• hash_48()• hash_64()• hash_128()

• Example:SIGNAL sig_hash;hash48(data_out, data_in, count, sig_done, &sig_hash);__wait_for_all(&sig_hash);


CAM--Brief

• Content Addressable Memory• Each ME has 16 32-bit CAM entries• The CAM is private to other MEs• With lookup operation, each entries is

searching in parallel• With a success lookup, the index of matched

entries will be returned• Else, the index of entries to be replaced will be

returnedNCKU CSIE CIAL Lab 15

CAM--Structure

• cam_lookup_t


CAM--Usage

cam_lookup_t cam_result;cam_result = cam_lookup( data );if( cam_result.hit == 1 ) {

Access Entry cam_result.entry_num;…

}else {……cam_write( cam_result.entry_num, data, 15 );

}


Task Partition

• Multi-Processing– More Computing Power– Easy to implement

• Context-Pipelining– More Useable Resource– Hard to balance


Memory Relative Techniques--Reducing Overhead

• Reduce the number of memory accesses– Wide-word Accesses– Result Caches

• Reduce average access latency– Multi-level Memory Hierarchy– Data Cache


Wide-Word Accesses--Brief

• Batch Access the needed data• Reduce the necessary accesses• Useful when the data stored

contiguously


MEM_ADDR+0 ……+4 ……+8 ……

+12 ……+16 ……+20 ……+24 ……+28 ……

Wide-Word Accesses--Usage (One Node per Access)

__declspec(sram_read_reg) UINT32 A;SIGNAL sig_read;

sram_read( &A, MEM_ADDR+(i*4), 1, sig_done, &sig_read);__wait_for_all( &sig_read );

Access A ......----------------------------------------------Result: 8 Accesses are needed


Wide-Word Accesses--Usage (Two Node per Access)

__declspec(sram_read_reg) UINT32 A[2];SIGNAL sig_read;




Wide-Word Accesses--Usage (Four Node per Access)

__declspec(sram_read_reg) UINT32 A[4];SIGNAL sig_read;




Wide-Word Accesses--Experiment

• Platform: IXP2800• Total Accesses: 8 LW (8*4 Byte)

Case Total Cycle Average Cycles/ LW

1LW * 8 Time 1211 151.38

2LW * 4 Time 725 90.63

4LW * 2 Time 460 57.50

8LW * 1 Time 387 48.38


Wide-Word Accesses--Limitation

• Data must be contiguous– Suitable for linear search– Not support random accesses

• Number of Transfer Registers are fixed– Each thread has 16 read / write registers– The Tx-Regs may be reserved by others


Resulting Cache--Brief

• Caching the result of application• If same fields appear again, the cached result

is returned• Memory accesses are reduced when cache

hit.• Depends on temporal locality of the traffic


Result Cache--IXP2400

• No hardware cache is supported in IXP2400 ME

• Not easy to implement set-associative cache• Replacement policy will also be an overhead


Result Cache--Design Consideration

• Shared or Private Cache ?• Size of Cache ?• Works with specific Hardware ?• Miss penalty handling ?


Result Cache--Example


Multi-Level Memory Hierarchy--Brief

• Reduce the average access latency• Number of accesses remained unchanged• If data can fit in faster memory, then do it


Multi-Level Memory Hierarchy--Data Placement

• Size smaller while read-only– Hard Code

• Size smaller while need updating– Local Memory

• Size larger– Scratchpad

• Size largest– SRAM


Multi-Level Memory Hierarchy--Packet Data Type

• Packet related data– Temporary Data– Valid with specific packet– Local Memory

• Flow related data– Related to specific flow– Spatial Locality– Wide-Word Access

• Application related data– Valid with specific application– Temporal Locality– Result Cache


Split-Cache (Z. Liu, IET-COM 2007)

• Two separate hardware for application data and flow data


Data Cache--Brief

• Hardware Cache Mechanism that cached the data for packet processing– App-Cache– Flow-Cache

• However, not supported by IXP2400 (Need additional hardware)


Data Cache--CAM + Local Memory

• CAM works with Local Memory acts like hardware cache

• However, number of CAM entries is limited• Each CAM entry may co-worked with several

Local Memory Cache entry


Memory Relative Techniques--Hiding Overhead

• Not really reduce the overhead, but overlapped it– Hardware Multi-Threading– Asynchronous Memory


Hardware Multi-Threading

• Swap out itself and let another thread to execute while access memory

• Each thread kept its own set of registers, thus no stack are needed for thread swapping

• Round Robin Scheduling• No thread preemptive


Asynchronous Memory--Brief

• Thread will not be blocked when issue a memory request

• Thus, thread can issues multiple memory requests at a time


Asynchronous Memory--Example (1 Issue)

Read X__wait_for_all ( &sig_x )Read Y__wait_for_all ( &sig_y )

// Use X and Y …


Asynchronous Memory--Example (2 Issues)

Read XRead Y__wait_for_all ( &sig_x, &sig_y )

// Use X and Y …


Wide-Word Access + Multiple Issues

MEM_ADDR+0……

+4 ……

+8 ……

+12 ……

+16 ……

+20 ……

+24 ……

+28 ……NCKU CSIE CIAL Lab 41

Wide-Word Access +Multiple Issues (1LW, 2 Issue)

MEM_ADDR+0……

+4 ……

+8 ……

+12 ……

+16 ……

+20 ……

+24 ……



MEM_ADDR+0……

+4 ……

+8 ……

+12 ……

+16 ……

+20 ……

+24 ……


Wide-Word Access +Multiple Issues (Experiment)

Scheme Total Cycles Average Cycles / LW

1 LW * 1 Issue 1211 151.38

2 LW * 1 Issue 725 90.63

4 LW * 1 Issue 460 57.50

8 LW * 1 Issue 387 48.38

1 LW * 2 Issue 716 89.50

2 LW * 2 Issue 445 55.63

4 LW * 2 Issue 364 45.50

1 LW * 4 Issue 396 49.50

2 LW * 4 Issue 320 40.00

1 LW * 8 Issue 318 39.75NCKU CSIE CIAL Lab 45

Reference (1)

• Jayaram Mudigonda, Harrick M. Vin, Raj Yavatkar, “Overcoming the memory wall in packet processing: hammers or ladders?”, Proc. ANCS 2005.

• Duo Liu, Zheng Chen, Bei Hua, Nenghai Yu, Xinan Tang, “High-Performance Packet Classification Algorithm for Multireaded IXP Network Processor”, ACM TECS 2008.


Reference (2)

• Z. Liu, K. Zheng, B. Liu, “Hybrid cache architecture for high-speed packet processing”, IET-COM 2007.


IXP Lab 2012: Part 3

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