S-A. Yu

ISSCC 2007 / SESSION 17 / ANALOG TECHNIQUES AND PLLs / 17.2

Offset frequency [MHz]

Phas

e no

ise

[dB

c/H

z]

Loop Filter(off-chip)

TCXO(off-chip)

VCO

50Driver

DataClock

LE

16MHz

0.5V

1V

0V

VGD can be close to 2VDD

2VDD

VDD

Circuit node voltages exceed VDD

0V

2VDD

~0V time

Thick oxide VDD

Thin oxide VDD

Thin oxide VT

Technology node [nm]

[ITRS'04]

– – High Perf.– –Low Standby– –Low Power

0.5V

0V

VDD

½ VDD

0V

All circuit node voltages between VSS & VDD

0.25V

time

See Digest page 304

17.2 A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS

Columbia University, New York, NY

A 2.5GHz fractional-N synthesizer is realized in a digital 90nm CMOS technology. The RF dividers operate at 0.65V while the remainder ofthe PLL operates at 0.5V; no special devices or voltage boosting is used to achieve the 0.5V operation. The synthesizable range covers 2.4to 2.6GHz with a phase noise of -55dBc/Hz in band and -120dBc/Hz at a 3MHz offset. The synthesizer dissipates 7mW and occupies0.14mm2.

Shih-an Yu, Peter Kinget

242 • 2007 IEEE International Solid-State Circuits Conference 1-4244-0852-0/07/$25.00 ©2007 IEEE.

Continued on Page 634

CVAR

VSGVTUNE

-50200 500

250

CVAR

(mV)

VTUNE

To TankVDD

RVT PMOS with L=0.4um has VT = 150mV

Depletion Inversion

W/L=20/0.4

~60% Tunability90fF

20fF CKIN

CKOUT

CtrlOUTCtrlIN

MODIN

Power is scaled by 0.7 over the SCL divider chain

FromVCO

FromVCO

CKIN

CtrlOUT

MODIN

CKOUT

Modulus translation and extension logic

Operates up to 200MHz @0.5V VDD (Simulated)

7 stages Implemented in standard cells

Tuning Voltage (mV)

Osc

illat

ion

Freq

uenc

y (M

Hz)

Measured VTUNE in lock = 320mV~480mV

Control00000001

••••••

11101111

CKCKb

D Db

QQb

CK CKb

D Db

Q

QbD Qb

CK

VDD =0.65V140-160MHz

2.4-2.6GHz

16MHz

0.65V

0.5V

0.5V

0.5VCK

CKb

D Db

QQb

© IEEE / ISSCC 2007 VISUALS SUPPLEMENT • 243

17

634 • 2007 IEEE International Solid-State Circuits Conference 1-4244-0852-0/07/$25.00 ©2007 IEEE.

VDD =0.5V

VDD =0.65V

Dithering Step = 1

P/FD

P/FD

Dithering Step = 4

P/FD

0.65V

0.5V

0.5V

0.5V

0.3V

0.2VCK

CKb

D Db

QQb

M1:VT=125mV

M2:VT=200mV

V T(m

V)

Gate Length (nm)

V T(m

V)

Forward Body Bias (mV)

AP

CP

CN

BP

AN

BN

QNQP

ISSCC 2007 / PAPER 17.2 Continued from page 243

DNb

UP

IOUT

IREF

0.7mm0.2m

m

Phas

e no

ise

(dB

c/H

z)

Frequency (MHz)

Con

trol

wor

d

– – @10kHz– – @1MHz– – @3MHz

ctrl word

© IEEE / ISSCC 2007 VISUALS SUPPLEMENT • 635

-52dBc

Phas

e no

ise

(dB

c/H

z)

Chip Number

@0.45V@0.50V

@1MHz offset

@0.55V

@3MHz offset

636 • 2007 IEEE International Solid-State Circuits Conference 1-4244-0852-0/07/$25.00 ©2007 IEEE.

-52dBc @16MHzSpurs

FractionalIntegerN=162.7131N=162

Phase Noise [dBc/Hz]

TechnologyChip Area

Power ConsumptionInt. Phase Err. [deg]

Tuning Range

Supply Voltage[V]

700 um x 200 um90nm Digital CMOS

3.5mW2.5mW

3.9

-123-120-113-68

DVDD

AVDD

4.41kHz to100MHz

-121@3MHz-117@2MHz-111@1MHz-70@10kHz

225MHz0.65DVDD

0.5AVDD

• 0.65V 2.4-2.6GHz Fractional-N synthesizer in 90nm CMOS.

• Ultra low voltage circuit design techniques:• 0.5V top-biased VCO with all node voltages

within power rails.• VT reduction using forward body biasing & and

device length optimization

• Shifted dithering divider control bits to avoid substrate noise injection.