ISLISL

David Stuart,UC Santa Barbara

May 11, 2006

David Stuart,UC Santa Barbara

May 11, 2006

ISLISL

David Stuart,UC Santa Barbara

May 11, 2006

David Stuart,UC Santa Barbara

May 11, 2006

Formerly known as Intermediate Radius Silicon

Formerly known as Intermediate Radius Silicon

I’ll review the motivation for the detector

and give a tour of its design and construction

I’ll review the motivation for the detector

and give a tour of its design and construction

The motivation is best shown by looking at an event display from Run 1.

The motivation is best shown by looking at an event display from Run 1.

The motivation is best shown by looking at an event display from Run 1.

Tracks are obviously missed and obviously easy to find.

Actual size

Unused hits from:

1. Low pT

2. > 1

Using forward silicon hits in Run 1

1. Stand-alone silicon pattern recognition• Fit for 0, d0, pT (curvature) with 4 hits, <=1 dof.• It worked, but was limited by

• lever arm (L2)• Too few hits• Poor curvature resolution degraded impact parameter resolution• 4% relative increase in b-tagging for

top

Using forward silicon hits in Run 1

2. Calorimeter-seeded tracking for electronsi.e., Phoenix

eeET event

eeET event

ISL designed to extend lever arm

SVX’ (Run 1)L00SVXII

ISL

Design goalsFine granularity at large radius for

Low occupancytypical jet has ~10 tracks in a <0.2 cone, covers 1000 channels

Resolution and lever arm (BL2)

100 m pitch = 30 m resolution sufficient forNegligible effect on d0 resolutionPointing into COT

< hit resolution at high pT

< hit width at low pT

2trk

COTres

Portcard scattering is a real complication

Design requirements

Big (5 m2)

Cheap

Fast

Design requirements

Big (5 m2) simple

Cheap simple

Fast simple

Piggybacking on SVX-II infrastructure important

Sensor Design

Big- used max possible sensor size per wafer.

HPK only had 4” wafersMicron had 6”, and they were cheaper (in both senses of the word).

Layer 6 built with HPK at FermilabLayer 7 built with Micron at Pisa Different geometries, mechanics, & quality

Readout Hybrid

Double sided and spaciousPitch adapterTransceiver

Half ladder

Full ladder

Ganging

Not in trigger, but don’t preclude, so r-phi read first.16 chips total--max FIB can handle.Note up-down reverses hall effect and readout direction.

Joel dropped them in place

Supported by carbon fiber spaceframeContaining cable and cooling

and gang card mounts

Notable differences from SVXII• Because rad damage is less of a concern, and no direct silicon heating

– ISL operates ~10 deg warmer than SVXII

• Layer 6 has the implant on the z-side

• IB0,1,4,5 (forward region)– L0,L2,L4 are layer seven (Micron sensors)– L1,L3 are layer six (Hamamatsu sensors)

• IB2,3 (central region)– Everything is layer six

• Within a given layer, IBxWyLz, y and z denote phi position of ganged readout pair

• Forward tracking

Recall Design goals

• Forward tracking ?

Recall Design goals