IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G · Integrated Silicon Solution, Inc. — 3 Rev....
Transcript of IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G · Integrated Silicon Solution, Inc. — 3 Rev....
IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G
Integrated Silicon Solution, Inc. — www.issi.com 1Rev. F12/9/2013
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:a.) the risk of injury or damage has been minimized;b.) the user assume all such risks; andc.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
FEATURES• Clockfrequency:200,166,143MHz
• Fullysynchronous;allsignalsreferencedtoapositive clock edge
• Internalbankforhidingrowaccess/precharge
• SinglePowersupply:3.3V+0.3V
• LVTTLinterface
• Programmableburstlength –(1,2,4,8,fullpage)
• Programmableburstsequence: Sequential/Interleave
• AutoRefresh(CBR)
• SelfRefresh
• 8Krefreshcyclesevery32ms(A2grade)or 64ms(commercial,industrial,A1grade)
• Randomcolumnaddresseveryclockcycle
• ProgrammableCAS latency (2, 3 clocks)
• Burstread/writeandburstread/singlewrite operations capability
• Burstterminationbyburststopandprechargecommand
OPTIONS• Package:
54-pinTSOP-II 54-ballBGA
• OperatingTemperatureRange: Commercial (0oC to +70oC) Industrial(-40oCto+85oC) AutomotiveGradeA1(-40oCto+85oC) AutomotiveGradeA2(-40oC to +105oC)
OVERVIEWISSI's256MbSynchronousDRAMachieveshigh-speeddata transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The256MbSDRAMisorganizedasfollows.
32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM
DECEMBER 2013
IS42S83200G IS42S16160G
8Mx8x4Banks 4Mx16x4Banks
54-pinTSOPII 54-pinTSOPII
54-ballBGA 54-ballBGA
Parameter 32M x 8 16M x 16Configuration 8M x 8 x 4
banks4M x 16 x 4 banks
Refresh Count Com./Ind.
A1A2
8K/64ms8K/64ms8K/32ms
8K/64ms8K/64ms8K/32ms
Row Addresses A0-A12 A0-A12Column Addresses A0-A9 A0-A8Bank Address Pins BA0, BA1 BA0, BA1Auto Precharge Pins A10/AP A10/AP
ADDRESS TABLE
KEY TIMING PARAMETERS
Parameter -5 -6 -7 Unit
ClkCycleTime CASLatency=3 5 6 7 nsCASLatency=2 10 10 7.5 ns
ClkFrequency CASLatency=3 200 166 143 Mhz CASLatency=2 100 100 133 Mhz
AccessTimefromClock CASLatency=3 5 5.4 5.4 nsCASLatency=2 5 5.4 5.4 ns
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DEVICE OVERVIEWThe 256Mb SDRAM is a high speed CMOS, dynamicrandom-accessmemorydesignedtooperatein3.3VVdd and3.3VVddq memorysystemscontaining268,435,456bits.Internallyconfiguredasaquad-bankDRAMwithasynchronousinterface.Each67,108,864-bitbankisorga-nizedas8,192rowsby512columnsby16bitsor8,192rowsby1,024columnsby8bits.
The256MbSDRAMincludesanAUTOREFRESHMODE,andapower-saving,power-downmode.Allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK.AllinputsandoutputsareLVTTLcompatible.
The256MbSDRAMhastheabilitytosynchronouslyburstdataatahighdataratewithautomaticcolumn-addressgeneration, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.
Aself-timedrowprechargeinitiatedattheendoftheburstsequenceisavailablewiththeAUTOPRECHARGEfunctionenabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless,high-speed,random-accessoperation.
SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. Theregistration of an ACTIVE command begins accesses,followedbyaREADorWRITEcommand.TheACTIVEcommand in conjunction with address bits registered are usedtoselect thebankandrowtobeaccessed(BA0,BA1selectthebank;A0-A12selecttherow).TheREADor WRITE commands in conjunction with address bitsregistered are used to select the starting column location for the burst access.
ProgrammableREADorWRITEburstlengthsconsistof1,2,4and8locationsorfullpage,withaburstterminateoption.
CLKCKECSRASCASWE
A9A8A7A6A5A4A3A2A1A0
BA0BA1
A10A12
COMMANDDECODER
&CLOCK
GENERATOR MODEREGISTER
REFRESHCONTROLLER
REFRESHCOUNTER
SELF
REFRESH
CONTROLLER
ROWADDRESS
LATCH MU
LTIP
LEX
ER
COLUMNADDRESS LATCH
BURST COUNTER
COLUMNADDRESS BUFFER
COLUMN DECODER
DATA INBUFFER
DATA OUTBUFFER
DQML DQMH
DQ 0-15
VDD/VDDQ
Vss/VssQ
13
13
9
13
13
9
16
16 16
16
512(x 16)
8192
8192
8192
RO
W D
EC
OD
ER 8192
MEMORY CELLARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROWADDRESSBUFFER
A11
2
FUNCTIONAL BLOCK DIAGRAM (FOR 4Mx16x4 BANKS SHOWN)
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VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
PIN CONFIGURATIONS54 pin TSOP - Type II for x8
PIN DESCRIPTIONSA0-A12 RowAddressInput
A0-A9 ColumnAddressInput
BA0,BA1 BankSelectAddress
DQ0toDQ7 DataI/O
CLK SystemClockInput
CKE ClockEnable
CS Chip Select
RAS RowAddressStrobeCommand
CAS Column Address Strobe Command
WE WriteEnable
DQM DataInput/OutputMask
Vdd Power
Vss Ground
Vddq PowerSupplyforI/OPin
Vssq GroundforI/OPin
NC No Connection
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PIN CONFIGURATIONS54 pin TSOP - Type II for x16
PIN DESCRIPTIONSA0-A12 RowAddressInput
A0-A8 ColumnAddressInput
BA0,BA1 BankSelectAddress
DQ0toDQ15 DataI/O
CLK SystemClockInput
CKE ClockEnable
CS Chip Select
RAS RowAddressStrobeCommand
CAS Column Address Strobe Command
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
DQMH
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
WE WriteEnable
DQML x16LowerByte,Input/OutputMask
DQMH x16UpperByte,Input/OutputMask
Vdd Power
Vss Ground
Vddq PowerSupplyforI/OPin
Vssq GroundforI/OPin
NC No Connection
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PIN CONFIGURATION54-ball TF-BGA for x8 (TopView)(8.00mmx8.00mmBody,0.8mmBallPitch)packagecode:B
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
VSS
A12
A8
VSS
NC
CLK
A11
A7
A5
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS
BA0
A0
A3
DQ0
RAS
BA1
A1
A2
VDD
WE
CS
A10
VDD
PIN DESCRIPTIONSA0-A12 RowAddressInput
A0-A9 ColumnAddressInput
BA0,BA1 BankSelectAddress
DQ0toDQ7 DataI/O
CLK SystemClockInput
CKE ClockEnable
CS Chip Select
RAS RowAddressStrobeCommand
CAS Column Address Strobe Command
WE WriteEnable
DQM DataInput/OutputMask
Vdd Power
Vss Ground
Vddq PowerSupplyforI/OPin
Vssq GroundforI/OPin
NC No Connection
NC
NC
NC
NC
DQM
DQ7
DQ6
DQ5
DQ4
NC
NC
NC
NCNC
DQ1
DQ2
DQ3
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IS42S83200G, IS42S16160GIS45S83200G, IS45S16160GPIN CONFIGURATION54-ball TF-BGA for x16 (TopView)(8.00mmx8.00mmBody,0.8mmBallPitch)packagecode:B
PIN DESCRIPTIONSA0-A12 RowAddressInputA0-A8 ColumnAddressInputBA0,BA1 BankSelectAddressDQ0toDQ15 DataI/OCLK SystemClockInputCKE ClockEnableCS Chip SelectRAS RowAddressStrobeCommandCAS Column Address Strobe Command
WE WriteEnableDQML x16LowerByteInput/OutputMaskDQMH x16UpperByteInput/OutputMaskVdd PowerVss GroundVddq PowerSupplyforI/OPinVssq GroundforI/OPinNC No Connection
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
VSS
DQ14
DQ12
DQ10
DQ8
DQMH
A12
A8
VSS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
DQML
RAS
BA1
A1
A2
VDD
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
VDD
Integrated Silicon Solution, Inc. — www.issi.com 7Rev. F12/9/2013
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PIN FUNCTIONS Symbol Type Function (In Detail)
A0-A12 Input Pin AddressInputs:A0-A12aresampledduringtheACTIVEcommand(row-addressA0-A12)andREAD/WRITEcommand(columnaddressA0-A9(x8),orA0-A8(x16);with A10 defining auto precharge) to select one location out of the memory array in therespectivebank.A10issampledduringaPRECHARGEcommandtodetermineifallbanksaretobeprecharged(A10HIGH)orbankselectedbyBA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOADMODEREGISTERcommand.
BA0,BA1 Input Pin BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE,READ,WRITEorPRECHARGEcommandisbeingapplied.
CAS Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the "CommandTruthTable"fordetailsondevicecommands.
CKE Input Pin TheCKEinputdetermineswhethertheCLKinputisenabled.ThenextrisingedgeoftheCLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW.WhenCKEisLOW,thedevicewillbeineitherpower-downmode,clocksuspendmode,orselfrefresh mode. CKEisan asynchronous input.
CLK Input Pin CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdeviceare acquired in synchronization with the rising edge of this pin.
CS Input Pin TheCS input determines whether command input is enabled within the device. Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.Thedevice remains in the previous state when CSisHIGH.
DQML, Input Pin DQMLandDQMHcontrolthelowerandupperbytesoftheI/Obuffers.Inread
DQMH mode,DQMLandDQMHcontroltheoutputbuffer.WhenDQMLorDQMHisLOW,thecorrespondingbufferbyteisenabled,andwhenHIGH,disabled.TheoutputsgototheHIGHimpedancestatewhenDQML/DQMHisHIGH.ThisfunctioncorrespondstoOEinconventionalDRAMs.Inwritemode,DQMLandDQMHcontroltheinputbuffer.WhenDQMLorDQMHisLOW,thecorrespondingbufferbyteisenabled,anddatacanbewrittentothedevice.WhenDQMLorDQMHisHIGH,inputdataismaskedandcannotbewrittentothedevice.ForIS42S16160Gonly.
DQM InputPin ForIS42S83200Gonly.
DQ0-DQ7 or Input/Output DataontheDataBusislatchedonDQpinsduringWritecommands,andbufferedfor DQ0-DQ15 outputafterReadcommands.
RAS Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the "Com-mandTruthTable"itemfordetailsondevicecommands.
WE Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the "Com-mandTruthTable"itemfordetailsondevicecommands.
Vddq Power Supply Pin Vddq is the output buffer power supply.
Vdd Power Supply Pin Vdd is the device internal power supply.
Vssq Power Supply Pin Vssq is the output buffer ground.
Vss Power Supply Pin Vss is the device internal ground.
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GENERAL DESCRIPTION
READTheREADcommandselectsthebankfromBA0,BA1inputsand starts a burst read access to an active row. Inputs A0-A9(x8);A0-A8(x16)providesthestartingcolumnloca-tion.WhenA10isHIGH,thiscommandfunctionsasanAUTOPRECHARGEcommand.Whentheautoprechargeis selected, the row being accessed will be precharged at theendoftheREADburst.TherowwillremainopenforsubsequentaccesseswhenAUTOPRECHARGEisnotselected.DQ’sreaddataissubjecttothelogiclevelontheDQMinputs twoclocksearlier.WhenagivenDQMsignalwasregisteredHIGH,thecorrespondingDQ’swillbeHigh-Z twoclocks later.DQ’swillprovidevaliddatawhentheDQMsignalwasregisteredLOW.
WRITEA burst write access to an active row is initiated with the WRITEcommand.BA0,BA1inputsselectsthebank,andthestartingcolumnlocationisprovidedbyinputsA0-A9(x8);A0-A8(x16).WhetherornotAUTO-PRECHARGEisused is determined by A10.
TherowbeingaccessedwillbeprechargedattheendoftheWRITEburst, ifAUTOPRECHARGE isselected. IfAUTOPRECHARGEisnotselected,therowwillremainopen for subsequent accesses.
A memory array is written with corresponding input data onDQ’sandDQMinputlogiclevelappearingatthesametime.DatawillbewrittentomemorywhenDQMsignalisLOW.WhenDQMisHIGH,thecorrespondingdatainputswillbeignored,andaWRITEwillnotbeexecutedtothatbyte/column location.
PRECHARGEThePRECHARGEcommand isused todeactivate theopen row in a particular bank or the open row in all banks. BA0,BA1canbeusedtoselectwhichbankisprechargedor they are treated as “Don’t Care”. A10 determinedwhether one or all banks are precharged. After execut-ing this command, the next command for the selected bank(s) is executed after passage of the period tRP, which istheperiodrequiredforbankprecharging.Onceabankhas been precharged, it is in the idle state and must be activatedpriortoanyREADorWRITEcommandsbeingissued to that bank.
AUTO PRECHARGETheAUTOPRECHARGEfunctionensuresthatthepre-charge is initiated at the earliest valid stage within a burst. Thisfunctionallowsforindividual-bankprechargewithoutrequiringanexplicitcommand.A10toenabletheAUTO
PRECHARGEfunctioninconjunctionwithaspecificREADorWRITEcommand.ForeachindividualREADorWRITEcommand, auto precharge is either enabled or disabled. AUTOPRECHARGEdoesnotapplyexceptinfull-pageburst mode. Upon completion of the READ or WRITEburst, a precharge of the bank/row that is addressed is automatically performed.
AUTO REFRESH COMMANDThiscommandexecutestheAUTOREFRESHoperation.Therowaddressandbanktoberefreshedareautomaticallygeneratedduringthisoperation. Thestipulatedperiod(trc) is required for a single refresh operation, and no other com-mandscanbeexecutedduringthisperiod. Thiscommandisexecutedatleast8192timesforeveryTref.DuringanAUTOREFRESHcommand,addressbitsare“Don’tCare”.ThiscommandcorrespondstoCBRAuto-refresh.
BURST TERMINATETheBURSTTERMINATEcommand forcibly terminatesthe burst read and write operations by truncating either fixed-length or full-page bursts and the most recentlyregisteredREADorWRITEcommandpriortotheBURSTTERMINATE.
COMMAND INHIBITCOMMANDINHIBITpreventsnewcommandsfrombeingexecuted.Operationsinprogressarenotaffected,apartfromwhethertheCLKsignalisenabled
NO OPERATION WhenCSislow,theNOPcommandpreventsunwantedcommands from being registered during idle or wait states.
LOAD MODE REGISTERDuringtheLOADMODEREGISTERcommandthemoderegisterisloadedfromA0-A12.Thiscommandcanonlybe issued when all banks are idle.
ACTIVE COMMANDWhen the ACTIVE COMMAND is activated, BA0, BA1inputs selects a bank to be accessed, and the address inputsonA0-A12selectstherow.UntilaPRECHARGEcommand is issued to the bank, the row remains open for accesses.
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IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
CKE
Function n-1 n DQMH DQML
Datawrite/outputenable H × L L
Datamask/outputdisable H × H H
Upperbytewriteenable/outputenable H × L ×
Lowerbytewriteenable/outputenable H × × L
Upperbytewriteinhibit/outputdisable H × H ×
Lowerbytewriteinhibit/outputdisable H × × H
CKE A12, A11
Function n – 1 n CS RAS CAS WE BA1 BA0 A10 A9 - A0
Devicedeselect(DESL) H × H × × × × × × ×
Nooperation(NOP) H × L H H H × × × ×
Burststop(BST) H × L H H L × × × ×
Read H × L H L H V V L V
Readwithautoprecharge H × L H L H V V H V
Write H × L H L L V V L V
Writewithautoprecharge H × L H L L V V H V
Bankactivate(ACT) H × L L H H V V V V
Prechargeselectbank(PRE) H × L L H L V V L ×
Prechargeallbanks(PALL) H × L L H L × × H ×
CBRAuto-Refresh(REF) H H L L L H × × × ×
Self-Refresh(SELF) H L L L L H × × × ×
Moderegisterset(MRS) H × L L L L L L L V
COMMAND TRUTH TABLE
DQM TRUTH TABLE
Note:H=Vih,L=Vilx=VihorVil,V=ValidData.
Note:H=Vih,L=Vilx=VihorVil,V=ValidData.
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CKE
CurrentState/Function n–1 n CS RAS CAS WE Address
ActivatingClocksuspendmodeentry H L × × × × ×
AnyClocksuspendmode L L × × × × ×
Clocksuspendmodeexit L H × × × × ×
AutorefreshcommandIdle(REF) H H L L L H ×
SelfrefreshentryIdle(SELF) H L L L L H ×
PowerdownentryIdle H L × × × × ×
Selfrefreshexit L H L H H H × L H H × × × ×
Powerdownexit L H × × × × ×
Note:H=Vih,L=Vilx=VihorVil,V=ValidData.
CKE TRUTH TABLE
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Current State CS RAS CAS WE Address Command Action
Idle H X X X X DESL NoporPowerDown(2)
L H H H X NOP NoporPowerDown(2)
L H H L X BST NoporPowerDown
L H L H BA,CA,A10 READ/READA ILLEGAL(3)
L H L L A,CA,A10 WRIT/WRITA ILLEGAL(3)
L L H H BA,RA ACT Rowactivating
L L H L BA,A10 PRE/PALL Nop
L L L H X REF/SELF AutorefreshorSelf-refresh(4)
L L L L OC,BA1=L MRS Moderegisterset
RowActive H X X X X DESL Nop
L H H H X NOP Nop
L H H L X BST Nop
L H L H BA,CA,A10 READ/READA Beginread(5)
L H L L BA,CA,A10 WRIT/WRITA Beginwrite(5)
L L H H BA,RA ACT ILLEGAL(3)
L L H L BA,A10 PRE/PALL Precharge
Precharge all banks(6)
L L L H X REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
Read H X X X X DESL Continuebursttoendto Rowactive
L H H H X NOP ContinuebursttoendRow Rowactive
L H H L X BST Burststop,Rowactive
L H L H BA,CA,A10 READ/READA Terminateburst, begin new read (7)
L H L L BA,CA,A10 WRIT/WRITA Terminateburst, begin write (7,8)
L L H H BA,RA ACT ILLEGAL(3)
L L H L BA,A10 PRE/PALL Terminateburst Precharging
L L L H X REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
Write H X X X X DESL Continuebursttoend Writerecovering
L H H H X NOP Continuebursttoend Writerecovering
L H H L X BST Burststop,Rowactive
L H L H BA,CA,A10 READ/READA Terminateburst,startread: DetermineAP(7,8)
L H L L BA,CA,A10 WRIT/WRITA Terminateburst,newwrite: DetermineAP(7)
L L H H BA,RA RAACT ILLEGAL(3)
L L H L BA,A10 PRE/PALL TerminateburstPrecharging(9)
L L L H X REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
FUNCTIONAL TRUTH TABLE
Note:H=Vih,L=Vilx=VihorVil,V=ValidData,BA=BankAddress,CA+ColumnAddress,RA=RowAddress,OC=Op-Code
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Current State CS RAS CAS WE Address Command Action
Readwithauto H × × × × DESL Continuebursttoend,PrechargePrecharging
L H H H x NOP Continuebursttoend,Precharge
L H H L × BST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL(11)
L H L L BA,CA,A10 WRIT/WRITA ILLEGAL(11)
L L H H BA,RA ACT ILLEGAL(3)
L L H L BA,A10 PRE/PALL ILLEGAL(11)
L L L H × REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
WritewithAuto H × × × × DESL Continuebursttoend,Write Precharge recovering with auto precharge
L H H H × NOP Continuebursttoend,Write recovering with auto precharge
L H H L × BST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL(11)
L H L L BA,CA,A10 WRIT/WRITA ILLEGAL(11)
L L H H BA,RA ACT ILLEGAL(3,11)
L L H L BA,A10 PRE/PALL ILLEGAL(3,11)
L L L H × REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
Precharging H × × × × DESL Nop,EnteridleaftertRP
L H H H × NOP Nop,EnteridleaftertRP
L H H L × BST Nop,EnteridleaftertRP
L H L H BA,CA,A10 READ/READA ILLEGAL(3)
L H L L BA,CA,A10 WRIT/WRITA ILLEGAL(3)
L L H H BA,RA ACT ILLEGAL(3)
L L H L BA,A10 PRE/PALL NopEnteridleaftertRP
L L L H × REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
RowActivating H × × × × DESL Nop,EnterbankactiveaftertRCD
L H H H × NOP Nop,EnterbankactiveaftertRCD
L H H L × BST Nop,EnterbankactiveaftertRCD
L H L H BA,CA,A10 READ/READA ILLEGAL(3)
L H L L BA,CA,A10 WRIT/WRITA ILLEGAL(3)
L L H H BA,RA ACT ILLEGAL(3,9)
L L H L BA,A10 PRE/PALL ILLEGAL(3)
L L L H × REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
FUNCTIONAL TRUTH TABLE Continued:
Note:H=Vih,L=Vilx=VihorVil,V=ValidData,BA=BankAddress,CA+ColumnAddress,RA=RowAddress,OC=Op-Code
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Current State CS RAS CAS WE Address Command Action
WriteRecovering H × × × × DESL Nop,EnterrowactiveaftertDPL
L H H H × NOP Nop,EnterrowactiveaftertDPL
L H H L × BST Nop,EnterrowactiveaftertDPL
L H L H BA,CA,A10 READ/READA Beginread(8)
L H L L BA,CA,A10 WRIT/WRITA Beginnewwrite
L L H H BA,RA ACT ILLEGAL(3)
L L H L BA,A10 PRE/PALL ILLEGAL(3)
L L L H × REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
WriteRecovering H × × × × DESL Nop,EnterprechargeaftertDPL
withAuto L H H H × NOP Nop,EnterprechargeaftertDPL
Precharge L H H L × BST Nop,EnterrowactiveaftertDPL
L H L H BA,CA,A10 READ/READA ILLEGAL(3,8,11)
L H L L BA,CA,A10 WRIT/WRITA ILLEGAL(3,11)
L L H H BA,RA ACT ILLEGAL(3,11)
L L H L BA,A10 PRE/PALL ILLEGAL(3,11)
L L L H × REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
Refresh H × × × × DESL Nop,EnteridleaftertRC
L H H × × NOP/BST Nop,EnteridleaftertRC
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10 WRIT/WRITA ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PALL ILLEGAL
L L L H × REF/SELF ILLEGAL
L L L L OC,BA MRS ILLEGAL
ModeRegister H × × × × DESL Nop,Enteridleafter2clocks
Accessing L H H H × NOP Nop,Enteridleafter2clocks
L H H L × BST ILLEGAL
L H L × BA,CA,A10 READ/WRITE ILLEGAL
L L × × BA,RA ACT/PRE/PALL ILLEGAL REF/MRS
FUNCTIONAL TRUTH TABLE Continued:
Note:H=Vih,L=Vilx=VihorVil,V=ValidData,BA=BankAddress,CA+ColumnAddress,RA=RowAddress,OC=Op-Code
Notes: 1.AllentriesassumethatCKEisactive(CKEn-1=CKEn=H).2.Ifbothbanksareidle,andCKEisinactive(Low),thedevicewillenterPowerDownmode.AllinputbuffersexceptCKEwillbe
disabled.3.Illegaltobankinspecifiedstates;FunctionmaybelegalinthebankindicatedbyBankAddress(BA),dependingonthestateof
that bank.4.Ifbothbanksareidle,andCKEisinactive(Low),thedevicewillenterSelf-Refreshmode.AllinputbuffersexceptCKEwillbe
disabled.5.IllegaliftRCDisnotsatisfied.6.IllegaliftRASisnotsatisfied.7.Mustsatisfyburstinterruptcondition.8.Mustsatisfybuscontention,busturnaround,and/orwriterecoveryrequirements.9.Mustmaskprecedingdatawhichdon’tsatisfytDPL.10.IllegaliftRRDisnotsatisfied.11. Illegal for single bank, but legal for other banks.
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CKE RELATED COMMAND TRUTH TABLE(1)
CKE Current State Operation n-1 n CS RAS CAS WE AddressSelf-Refresh(S.R.) INVALID,CLK(n-1)wouldexitS.R. H X X X X X X Self-RefreshRecovery(2) L H H X X X X Self-RefreshRecovery(2) L H L H H X X Illegal L H L H L X X Illegal L H L L X X X MaintainS.R. L L X X X X XSelf-RefreshRecoveryIdleAftertrc H H H X X X X Idle After trc H H L H H X X Illegal H H L H L X X Illegal H H L L X X X Beginclocksuspendnextcycle(5) H L H X X X X Beginclocksuspendnextcycle(5) H L L H H X X Illegal H L L H L X X Illegal H L L L X X X Exit clock suspend next cycle(2) L H X X X X X Maintainclocksuspend L L X X X X XPower-Down(P.D.) INVALID,CLK(n-1)wouldexitP.D. H X X X X X — EXITP.D.-->Idle(2) L H X X X X X Maintainpowerdownmode L L X X X X XAllBanksIdle RefertooperationsinOperativeCommandTable H H H X X X — RefertooperationsinOperativeCommandTable H H L H X X — RefertooperationsinOperativeCommandTable H H L L H X — Auto-Refresh H H L L L H X RefertooperationsinOperativeCommandTable H H L L L L Op-Code RefertooperationsinOperativeCommandTable H L H X X X — RefertooperationsinOperativeCommandTable H L L H X X — RefertooperationsinOperativeCommandTable H L L L H X — Self-Refresh(3) H L L L L H X RefertooperationsinOperativeCommandTable H L L L L L Op-Code Power-Down(3) L X X X X X XAnystate RefertooperationsinOperativeCommandTable H H X X X X Xotherthan Beginclocksuspendnextcycle(4) H L X X X X Xlistedabove Exitclocksuspendnextcycle L H X X X X X Maintainclocksuspend L L X X X X X
Notes:1.H:Highlevel,L:lowlevel,X:Highorlowlevel(Don’tcare).2.CKELowtoHightransitionwillre-enableCLKandotherinputsasynchronously.Aminimumsetup
timemustbesatisfiedbeforeanycommandotherthanEXIT.3. Power down and Self refresh can be entered only from the both banks idle state.4.MustbelegalcommandasdefinedinOperativeCommandTable.5. Illegal if txsr is not satisfied.
Integrated Silicon Solution, Inc. — www.issi.com 15Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
ModeRegister
SetIDLE
SelfRefresh
CBR (Auto)Refresh
RowActive
ActivePowerDown
PowerDown
WRITEWRITE
SUSPENDREAD
READSUSPEND
WRITEASUSPEND
WRITEA READAREADA
SUSPEND
POWERON
Precharge
Automatic sequence
Manual Input
SELF
SELF exit
REFMRS
ACT
CKE
CKE
CKE
CKE
BST
Read
Write
Write
Precharge
RR
E (Precharge termination) PR
E (P
rech
arge
term
inat
ion)
Writ
e w
ithA
uto
Pre
char
ge Read w
ith
Auto P
recharge
Read
Write
BST
CKE
CKECKE
CKE
CKE
CKECKE
CKE
Read
STATE DIAGRAM
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vdd max MaximumSupplyVoltage –0.5to+4.6 V Vddq max MaximumSupplyVoltageforOutputBuffer –0.5to+4.6 V Vin InputVoltage –0.5toVdd+0.5 V Vout OutputVoltage –1.0toVddq+0.5 V Pd max AllowablePowerDissipation 1 W Ics output Shorted Current 50 mA Topr operatingTemperature Com. 0 to +70 °C Ind. –40to+85 A1 –40to+85 A2 –40to+105 Tstg StorageTemperature –65to+150 °C
DC RECOMMENDED OPERATING CONDITIONS (Ta=0oC to +70oCforCommercialgrade.Ta=-40oCto+85oCforIndustrialandA1grade.Ta=-40oC to +105oC for A2 grade.)
Symbol Parameter Min. Typ. Max. Unit
Vdd SupplyVoltage 3.0 3.3 3.6 V Vddq I/OSupplyVoltage 3.0 3.3 3.6 V Vih(1) InputHighVoltage 2.0 — Vddq +0.3 V Vil(2) InputLowVoltage -0.3 — +0.8 V
CAPACITANCE CHARACTERISTICS (AtTa=0to+25°C,Vdd=Vddq =3.3±0.3V)
Symbol Parameter Min. Max. Unit
Cin1 InputCapacitance:CLK 2.5 3.5 pF Cin2 InputCapacitance:Allotherinputpins 2.5 3.8 pF CI/O DataInput/OutputCapacitance:DQS 4.0 6.0 pF
Note: 1.Vih (overshoot): Vih (max)=Vddq +1.2V (pulse width < 3ns).2.Vil (undershoot): Vih (min)=-1.2V (pulse width < 3ns).3. AllvoltagesarereferencedtoVss.
Notes:1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamageto
thedevice.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabove those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. AllvoltagesarereferencedtoVss.
THERMAL RESISTANCE (AtTa=0to+25°C,Vdd=Vddq =3.3±0.3V)
Package Substrate Theta-ja(Airflow = 0m/s)
Theta-ja(Airflow = 1m/s)
Theta-ja(Airflow = 2m/s)
Theta-jc Units
Alloy42 TSOP2 (54) 4-layer 70.6 62.0 58.3 13.0 C/WCopper TSOP2 (54) 4-layer 46.0 40.9 38.3 8.9 C/W
BGA (54) 4-layer 33.6 28.8 27.1 6.9 C/W
Integrated Silicon Solution, Inc. — www.issi.com 17Rev. F12/9/2013
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DC ELECTRICAL CHARACTERISTICS 1(1,3) (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol Parameter Test Condition -5 -6 -7 Unit
idd1 (1) OperatingCurrent Onebankactive,CL=3,BL=1, 150 130 110 mA
tclk=tclk (min), trc=trc (min)
idd2p PrechargeStandbyCurrent CKE≤ Vil (max), tck=15ns 4 4 4 mA (InPower-DownMode)4
idd2ps PrechargeStandbyCurrent CKE≤ Vil (max),CLK≤ Vil (max) 4 4 4 mA (InPower-DownMode)
idd2n (2) Precharge Standby Current CS ≥ Vcc-0.2V,CKE≥ Vih (min) 25 25 25 mA
(InNonPower-DownMode) tck=15ns
Idd2ns Precharge Standby Current CS ≥ Vcc-0.2V,CKE≥ Vih (min) 20 20 20 mA
(InNonPower-DownMode) or CKE≤ Vil (max), All inputs stable
idd3p ActiveStandbyCurrent CKE≤ Vil (max), tck=15ns 9 9 9 mA
(Power-DownMode)
idd3ps ActiveStandbyCurrent CKE≤ Vil (max),CLK≤ Vil (max) 9 9 9 mA
(Power-DownMode)
idd3n (2) Active Standby Current CS ≥ Vcc-0.2V,CKE≥ Vih (min) 30 30 30 mA
(InNonPower-DownMode) tck=15ns
Idd3ns Active Standby Current CS ≥ Vcc-0.2V,CKE≥ Vih (min) 15 15 15 mA
(InNonPower-DownMode) or CKE≤ Vil (max), All inputs stable
idd4 OperatingCurrent Allbanksactive,BL=4,CL=3, 180 160 130 mA
tck=tck (min)
idd5 Auto-RefreshCurrent trc=trc (min), tclk=tclk(min) 180 160 130 mA
idd6 Self-RefreshCurrent CKE≤ 0.2V 5 5 5 mA
Notes:1. Idd (max) is specified at the output open condition.2. Input signals are changed one time during 30ns.3.ForA2temperaturegradewithTa >85oC: idd1, idd3p, idd3ps, and idd4are derated to 10% above these values; idd2p, idd2ps, and
idd6are derated to 25% above these values.
DC ELECTRICAL CHARACTERISTICS 2 (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol Parameter Test Condition Min Max Unit
iil InputLeakageCurrent 0V≤Vin≤Vcc,withpinsotherthan -5 5 µA
thetestedpinat0V
iol OutputLeakageCurrent Outputisdisabled,0V≤Vout≤Vcc, -5 5 µA
Voh OutputHighVoltageLevel Ioh=-2mA 2.4 — V
Vol OutputLowVoltageLevel Iol=2mA — 0.4 V
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AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5 -6 -7 Symbol Parameter Min. Max. Min. Max. Min. Max. Units tck3 ClockCycleTime CASLatency=3 5 — 6 — 7 — ns tck2 CASLatency=2 10 — 10 — 7.5 — ns
tac3 AccessTimeFromCLK CASLatency=3 — 5 — 5.4 — 5.4 ns tac2 CASLatency=2 — 5 — 5.4 — 5.4 ns
tch CLKHIGHLevelWidth 2 — 2.5 — 2.5 — ns
tcl CLKLOWLevelWidth 2 — 2.5 — 2.5 — ns
toh3 OutputDataHoldTime CASLatency=3 2.7 — 2.7 — 2.7 — ns toh2 CAS Latency=2 2.7 — 2.7 — 2.7 — ns
tlz OutputLOWImpedanceTime 0 — 0 — 0 — ns
thz3 OutputHIGHImpedanceTimeCASLatency=3 2.7 5 2.7 5.4 2.7 5.4 ns
thz2 CAS Latency=2 2.75 2.75.4 2.75.4 ns
tds InputDataSetupTime(2) 1.5 — 1.5 — 1.5 — ns
tdh InputDataHoldTime(2) 0.8 — 0.8 — 0.8 — ns
tas AddressSetupTime(2) 1.5 — 1.5 — 1.5 — ns
tah AddressHoldTime(2) 0.8 — 0.8 — 0.8 — ns
tcks CKESetupTime(2) 1.5 — 1.5 — 1.5 — ns
tckh CKEHoldTime(2) 0.8 — 0.8 — 0.8 — ns
tcms CommandSetupTime(CS, RAS, CAS, WE,DQM)(2) 1.5 — 1.5 — 1.5 — ns
tcmh CommandHoldTime(CS, RAS, CAS, WE,DQM)(2) 0.8 — 0.8 — 0.8 — ns
trc CommandPeriod(REFtoREF/ACTtoACT) 60 — 60 — 60 — ns
tras CommandPeriod(ACTtoPRE) 45 100K 42 100K 37 100K ns
trp CommandPeriod(PREtoACT) 15 — 18 — 15 — ns
trcd ActiveCommandToRead/WriteCommandDelayTime 15 — 18 — 15 — ns
trrd CommandPeriod(ACT[0]toACT[1]) 10 — 12 — 14 — ns
tdpl InputDataToPrecharge 10 — 12 — 14 — ns CommandDelaytime
tdal InputDataToActive/Refresh 25 — 30 — 30 — ns CommandDelaytime(DuringAuto-Precharge)
tmrd ModeRegisterProgramTime 10 — 12 — 14 — ns
tdde PowerDownExitSetupTime 5 — 6 — 7 — ns
txsr exitSelf-RefreshtoActiveTime(4) 65 — 66 — 70 — ns
tt TransitionTime 0.3 1.2 0.3 1.2 0.3 1.2 ns
tref RefreshCycleTime(8192) Ta ≤ 70oCCom.,Ind.,A1,A2 — 64 — 64 — 64 ms Ta ≤85o CInd.,A1,A2 — 64 — 64 — 64 ms Ta >85oCA2 — — — 32 — 32 ms
Notes:1. Thepower-onsequencemustbeexecutedbeforestartingmemoryoperation.2. measured with tt =1ns.Ifclockrisingtimeislongerthan1ns,(tt/2-0.5)nsshouldbeaddedtotheparameter.3. Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming.RiseandfalltimesaremeasuredbetweenVih(min.)andVil(max).4.Self-RefreshModeisnotsupportedforA2gradewithTa>85oC
Integrated Silicon Solution, Inc. — www.issi.com 19Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER -5 -6 -7 UNITS
tCK ClockCycleTime CASLatency=3 5 6 7 ns CASLatency=2 10 10 7.5
Freq. OperatingFrequency CASLatency=3 200 166 143 MHz CASLatency=2 100 100 133
trcd ActiveCommandToRead/WriteCommandDelayTime CASLatency=3 3 3 3 cycle CASLatency=2 2 2 2
trac RASLatency(trcd + tcac) CASLatency=3 6 6 6 cycle CASLatency=2 4 4 4
trc CommandPeriod(REFtoREF/ACTtoACT) CASLatency=3 12 10 9 cycle CASLatency=2 6 6 8
tras CommandPeriod(ACTtoPRE) CASLatency=3 9 7 6 cycle CASLatency=2 5 5 6
trp CommandPeriod(PREtoACT) CASLatency=3 3 3 3 cycle CASLatency=2 2 2 2
trrd CommandPeriod(ACT[0]toACT[1]) 2 2 2 cycle
tccd ColumnCommandDelayTime 1 1 1 cycle (READ,READA,WRIT,WRITA)
tdpl InputDataToPrechargeCommandDelayTime 2 2 2 cycle
tdal InputDataToActive/RefreshCommandDelayTime CASLatency=3 5 5 5 cycle (DuringAuto-Precharge) CASLatency=2 4 4 4
trbd BurstStopCommandToOutputinHIGH-ZDelayTime CASLatency=3 3 3 3 cycle (Read) CASLatency=2 2 2 2
twbd BurstStopCommandToInputinInvalidDelayTime 0 0 0 cycle (Write)
trql PrechargeCommandToOutputinHIGH-ZDelayTime CASLatency=3 3 3 3 cycle (Read) CASLatency=2 2 2 2
twdl PrechargeCommandToInputinInvalidDelayTime 0 0 0 cycle (Write)
tpql LastOutputToAuto-PrechargeStartTime(Read) CASLatency=3 -2 -2 -2 cycle CASLatency=2 -1 -1 -1
tqmd DQMToOutputDelayTime(Read) 2 2 2 cycle
tdmd DQMToInputDelayTime(Write) 0 0 0 cycle
tmrd ModeRegisterSetToCommandDelayTime 2 2 2 cycle
Note:ThenumberofclockcyclesshowninthistableareexamplesbasedontCKvalues in this table and the timing limits from AC Electrical Characteristics table.
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AC TEST CONDITIONS
Input Load Output Load
Output Z = 50Ω
50 pF
1.4V
50Ω
3.0V
1.4V
0V
CLK
INPUT
OUTPUT
tCH
tCMH
tACtOH
tCMS
tCK
tCL
3.0V
1.4V
1.4V 1.4V
0V
AC TEST CONDITIONS
Parameter Rating ACInputLevels 0Vto3.0V InputRiseandFallTimes 1ns InputTimingReferenceLevel 1.4V OutputTimingMeasurementReferenceLevel 1.4V
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FUNCTIONAL DESCRIPTIONThe256MbSDRAMsarequad-bankDRAMswhichoperateat3.3Vandincludeasynchronousinterface(allsignalsare registered on the positive edge of the clock signal, CLK).Eachofthe67,108,864-bitbanksisorganizedas8,192rowsby512columnsby16bitsor8,192rowsby1,024columnsby8bits.
ReadandwriteaccessestotheSDRAMareburstoriented;accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC-TIVEcommandwhichisthenfollowedbyaREADorWRITEcommand.TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowto be accessed (BA0andBA1selectthebank,A0-A12selectthe row).TheaddressbitsA0-A9(x8);A0-A8(x16) registered coincidentwiththeREADorWRITEcommandareusedtoselect the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initial-ized.Thefollowingsectionsprovidedetailedinformationcovering device initialization, register definition, command descriptions and device operation.
InitializationSDRAMs must be powered up and initialized in a predefined manner.
The256MbSDRAMisinitializedafterthepowerisappliedtoVddandVddq (simultaneously) and the clock is stable withCKEHigh.
A 100µs delay is required prior to issuing any command other than a COMMANDINHIBIT or a NOP.TheCOMMANDINHIBITorNOPmaybeappliedduringthe200usperiodand should continue at least through the end of the period.
WithatleastoneCOMMANDINHIBITorNOPcommandhavingbeenapplied,aPRECHARGEcommandshouldbe applied once the 100µs delay has been satisfied. All banksmustbeprecharged.Thiswillleaveallbanksinanidle state after which at least two AUTOREFRESH cycles must be performed. After the AUTOREFRESH cycles are complete, the SDRAM is then ready for mode registerprogramming.
The mode register should be loaded prior to applyingany operational command because it will power up in an unknown state.
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INITIALIZE AND LOAD MODE REGISTER(1)
DON'T CARE
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCH tCLtCK
tCMS tCMH tCMS tCMH tCMS tCMH
tCKS tCKH
T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3
tMRDtRCtRCtRP
ROW
ROW
BANK
tAS tAH
tAS tAH
CODE
CODEALL BANKS
SINGLE BANK
ALL BANKS
AUTOREFRESH
AUTOREFRESH
Load MODEREGISTER
T = 100µs Min.
Power-up: VCC
and CLK stablePrechargeall banks
AUTO REFRESH Program MODE REGISTER
NOP PRECHARGE NOP NOP NOP ACTIVE
T
(2, 3, 4)AUTO REFRESH
At least 2 Auto-Refresh Commands
CODE
tAS tAH
Notes:1. If CSisHighatclockHightime,allcommandsappliedareNOP.2.TheModeregistermaybeloadedpriortotheAuto-Refreshcyclesifdesired.3.JEDECandPC100specifythreeclocks.4.OutputsareguaranteedHigh-Zafterthecommandisissued.
Integrated Silicon Solution, Inc. — www.issi.com 23Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
AUTO-REFRESH CYCLE
Notes:1. CASlatency=2,3
tRP tRC tRC
DON'T CARE
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tAS tAH
tCHtCLtCK
tCMS tCMH
tCKS tCKH
T0 T1 T2 Tn+1 To+1
ALL BANKS
SINGLE BANK
BANK(s)
ROW
ROW
BANK
High-Z
PRECHARGE NOP NOP NOP ACTIVEAutoRefresh
AutoRefresh
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SELF-REFRESH CYCLE
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tAS tAH
BANK
tCLtCHtCK
tCMS tCMH
tCKS tCKH
ALL BANKS
SINGLE BANK
tCKS
Precharge allactive banks
CLK stable prior to exitingself refresh mode
Enter selfrefresh mode
Exit self refresh mode(Restart refresh time base)
T0 T1 T2 Tn+1 To+1 To+2
High-Z
AutoRefresh
AutoRefreshPRECHARGE NOP NOP NOP
tCKS
≥ tRAS
tRP tXSR
DON'T CARE
Notes:1.Self-RefreshModeisnotsupportedforA2gradewithTa>85oC.
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IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
REGISTER DEFINITION
Mode RegisterThemode register isused todefine thespecificmodeofoperationof theSDRAM.Thisdefinition includestheselection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODEREGISTERDEFINITION.
ThemoderegisterisprogrammedviatheLOADMODEREGISTERcommandandwillretainthestoredinformationuntil it is programmed again or the device loses power.
Mode register bitsM0-M2specify theburst length,M3specifies the type of burst (sequential or interleaved),M4-M6specifytheCASlatency,M7andM8specifytheoperatingmode,M9specifiestheWRITEburstmode,andM10,M11,andM12arereservedforfutureuse.
Themode registermustbe loadedwhenallbanksareidle, and the controller must wait the specified time before initiatingthesubsequentoperation.Violatingeitheroftheserequirements will result in unspecified operation.
MODE REGISTER DEFINITION
Latency Mode
M6 M5 M4 CAS Latency
0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved
1. To ensure compatibility with future devices,should program BA1, BA0, A12, A11, A10 = "0"
Write Burst Mode
M9 Mode
0 Programmed Burst Length
1 Single Location Access
Operating Mode
M8 M7 M6-M0 Mode
0 0 Defined Standard Operation — — — All Other States Reserved
Burst Type
M3 Type
0 Sequential 1 Interleaved
Burst Length
M2 M1 M0 M3=0 M3=1
0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved
Reserved
Address Bus (Ax)
Mode Register (Mx)
(1)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
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BURST DEFINITION
Burst Starting Column Order of Accesses Within a Burst
Length Address Type = Sequential Type = Interleaved
A 0
2 0 0-1 0-1
1 1-0 1-0
A 1 A 0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A 2 A 1 A 0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full n=A0-A8(x16) Cn,Cn+1,Cn+2 NotSupported Page n=A0-A9(x8) Cn+3,Cn+4... (y) (location0-y) …Cn-1, Cn…
BURST LENGTHReadandwriteaccessestotheSDRAMareburstoriented,with the burst length being programmable, as shown in MODEREGISTERDEFINITION.Theburstlengthdeter-mines the maximum number of column locations that can beaccessedforagivenREADorWRITEcommand.Burstlengthsof1,2,4or8locationsareavailableforboththesequentialandtheinterleavedbursttypes,andafull-pageburst is available for the sequential type.The full-pageburstisusedinconjunctionwiththeBURSTTERMINATEcommand to generate arbitrary burst lengths.
Reservedstatesshouldnotbeused,asunknownoperationor incompatibility with future versions may result.
WhenaREADorWRITEcommandisissued,ablockofcolumns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is reached.TheblockisuniquelyselectedbyA1-A8(x16)orA1-A9(x8)whentheburstlengthissettotwo;byA2-A8(x16)orA2-A9(x8)whentheburstlengthissettofour;andbyA3-A8(x16)orA3-A9(x8)whentheburstlengthissettoeight.Theremaining(leastsignificant)addressbit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if theboundary is reached.
BurstTypeAccesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the bursttypeandisselectedviabitM3.
Theorderingofaccesseswithinaburstisdeterminedbythe burst length, the burst type and the starting column address,asshowninBURSTDEFINITIONtable.
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DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ NOP NOP NOP
CAS Latency - 3
tAC
tOH
DOUT
T0 T1 T2 T3 T4
tLZ
CLK
COMMAND
DQ
READ NOP NOP
CAS Latency - 2
tAC
tOH
DOUT
T0 T1 T2 T3
tLZ
CAS LATENCY
CAS LatencyTheCAS latency is thedelay, inclockcycles,betweenthe registrationofaREADcommandandtheavailabilityofthefirstpieceofoutputdata.Thelatencycanbesettotwoorthree clocks.
IfaREADcommandisregisteredatclockedgen,andthe latency is m clocks, the data will be available by clock edge n + m.TheDQswillstartdrivingasaresultoftheclock edge one cycle earlier (n + m -1),andprovidedthatthe relevant access times are met, the data will be valid by clock edge n + m.Forexample,assumingthattheclockcycle time is such that all relevant access times are met, ifaREADcommandisregisteredatT0andthelatencyisprogrammedto twoclocks, theDQswillstartdrivingafterT1andthedatawillbevalidbyT2,asshowninCASLatency diagrams.The Allowable Operating Frequencytable indicates the operating frequencies at which each CAS latency setting can be used.
Reservedstatesshouldnotbeusedasunknownoperationor incompatibility with future versions may result.
CAS LatencyAllowable Operating Frequency (MHz)
Speed CAS Latency = 2 CAS Latency = 3
-5 100 200
-6 100 166
-7 133 143
Operating ModeThenormaloperatingmodeisselectedbysettingM7andM8tozero;theothercombinationsofvaluesforM7andM8arereservedforfutureuseand/ortestmodes.TheprogrammedburstlengthappliestobothREADandWRITEbursts.
Testmodesandreservedstatesshouldnotbeusedbe-cause unknown operation or incompatibility with future versions may result.
Write Burst ModeWhenM9=0,theburstlengthprogrammedviaM0-M2appliestobothREADandWRITEbursts;whenM9=1,theprogrammedburstlengthappliestoREADbursts,butwriteaccessesaresingle-location(nonburst)accesses.
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CLK
CKE
ROW ADDRESS
BANK ADDRESS
CS
RAS
CAS
WE
A0-A12
BA0, BA1
HIGH
ACTIVATING SPECIFIC ROW WITHIN SPE-CIFIC BANK
DON'T CARE
CLK
COMMAND ACTIVE NOP NOP
tRCD
T0 T1 T2 T3 T4
READ orWRITE
CHIP OPERATION
BANK/ROW ACTIVATIONBeforeanyREADorWRITEcommandscanbe issuedtoabankwithintheSDRAM,arowinthatbankmustbe“opened.”ThisisaccomplishedviatheACTIVEcommand,which selects both the bank and the row to be activated (see ActivatingSpecificRowWithinSpecificBank).
After opening a row (issuinganACTIVEcommand),aREADorWRITEcommandmaybeissuedtothatrow,subjecttothe trcdspecification.Minimumtrcd should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVEcommandonwhichaREADorWRITEcommandcanbeentered.Forexample,atrcd specification of 15ns with a 143MHzclock(7nsperiod)resultsin2.14clocks,roundedto3.Thisisreflectedinthefollowingexample,whichcov-ersanycasewhere2<[trcd(MIN)/tck] ≤3.(Thesameprocedure is used to convert other specification limits from time units to clock cycles).
AsubsequentACTIVEcommandtoadifferentrowinthesame bank can only be issued after the previous active rowhasbeen“closed”(precharged).TheminimumtimeintervalbetweensuccessiveACTIVEcommands to thesame bank is defined by trc.
AsubsequentACTIVEcommandtoanotherbankcanbeissued while the first bank is being accessed, which results inareductionoftotalrow-accessoverhead.TheminimumtimeintervalbetweensuccessiveACTIVEcommandstodifferent banks is defined by trrd.
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
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CLK
CKEHIGH
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
CS
RAS
CAS
WE
A0-A9
A10
BA0, BA1 BANK ADDRESS
A11, A12
READ COMMANDREADSREAD bursts are initiated with a READ command, asshownintheREADCOMMANDdiagram.
ThestartingcolumnandbankaddressesareprovidedwiththeREADcommand,andautoprechargeiseitherenabledordisabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericREADcommandsusedinthefol-lowing illustrations, auto precharge is disabled.
DuringREADbursts,thevaliddata-outelementfromthestarting column address will be available following the CASlatencyaftertheREADcommand.Eachsubsequentdata-outelementwillbevalidbythenextpositiveclockedge.TheCASLatencydiagramshowsgeneral timing for each possible CAS latency setting.
Uponcompletionofaburst,assumingnoothercommandshavebeeninitiated,theDQswillgoHigh-Z.Afull-pageburstwill continue until terminated. (At the end of the page, it will wrap to column 0 and continue.)
DatafromanyREADburstmaybetruncatedwithasub-sequentREADcommand,anddatafromafixed-lengthREADburstmaybeimmediatelyfollowedbydatafromaREADcommand.Ineithercase,acontinuousflowofdatacanbemaintained.Thefirstdataelementfromthenewburst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
ThenewREADcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.ThisisshowninConsecutiveREADBurstsforCASlatenciesoftwo and three; data element n + 3 is either the last of a burstoffourorthelastdesiredofalongerburst.The256MbSDRAMusesapipelinedarchitectureandthereforedoesnot require the 2n rule associated with a prefetch architec-ture.AREADcommandcanbeinitiatedonanyclockcyclefollowingapreviousREADcommand.Full-speedrandomread accesses can be performed to the same bank, as showninRandomREADAccesses,oreachsubsequentREADmaybeperformedtoadifferentbank.
DatafromanyREADburstmaybetruncatedwithasub-sequentWRITE command, and data from a fixed-lengthREADburstmaybeimmediatelyfollowedbydatafromaWRITEcommand(subjecttobusturnaroundlimitations).TheWRITEburstmaybeinitiatedontheclockedgeim-mediately following the last (or last desired) data element fromtheREADburst,providedthatI/Ocontentioncanbeavoided. In a given system design, there may be a pos-sibilitythatthedevicedrivingtheinputdatawillgoLow-ZbeforetheSDRAMDQsgoHigh-Z.Inthiscase,atleastasingle-cycledelayshouldoccurbetweenthelastreaddataandtheWRITEcommand.
TheDQMinputisusedtoavoidI/Ocontention,asshowninFiguresRW1andRW2.TheDQMsignalmustbeas-serted (HIGH)at least threeclocksprior to theWRITEcommand(DQMlatencyistwoclocksforoutputbuffers)tosuppressdata-out fromtheREAD.Once theWRITEcommandisregistered,theDQswillgoHigh-Z(orremainHigh-Z),regardlessofthestateoftheDQMsignal,providedtheDQMwasactiveontheclockjustpriortotheWRITEcommandthattruncatedtheREADcommand.Ifnot,thesecondWRITEwillbeaninvalidWRITE.Forexample,ifDQMwasLOWduringT4inFigureRW2,thentheWRITEsatT5andT7wouldbevalid,whiletheWRITEatT6wouldbe invalid.
TheDQMsignalmustbede-assertedpriortotheWRITEcommand(DQMlatencyiszeroclocksforinputbuffers)to ensure that the written data is not masked.
Afixed-lengthREADburstmaybefollowedby,ortruncatedwith, a PRECHARGE command to the same bank (provided that auto precharge was not activated),andafull-pageburstmaybetruncatedwithaPRECHARGEcommandtothesamebank.ThePRECHARGEcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minusone.ThisisshownintheREADtoPRECHARGE
Note:A9is"Don'tCare"forx16.
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diagram for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of alongerburst.FollowingthePRECHARGEcommand,asubsequent command to the same bank cannot be issued until trp is met. Note that part of the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed tocompletion, a PRECHARGE command issued at theoptimum time (as described above) provides the same operation that would result from the same fixed-lengthburstwithautoprecharge.ThedisadvantageofthePRE-CHARGEcommandisthatitrequiresthatthecommandand address buses be available at the appropriate time to issuethecommand;theadvantageofthePRECHARGEcommandisthatitcanbeusedtotruncatefixed-lengthorfull-pagebursts.
Full-pageREADburstscanbetruncatedwiththeBURSTTERMINATE command, and fixed-length READ burstsmaybetruncatedwithaBURSTTERMINATEcommand,providedthatautoprechargewasnotactivated.TheBURSTTERMINATEcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.ThisisshownintheREADBurstTerminationdiagramforeachpossible CAS latency; data element n + 3 is the last desired data element of a longer burst.
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DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
READ NOP NOP NOP NOP WRITE
BANK,COL n
BANK,COL b
DOUT n DIN b
tDS
tHZ
CAS Latency - 3
RW1 - READ to WRITE
RW2 - READ to WRITE
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP NOP NOP WRITE
BANK,COL n
DIN b
tDS
tHZ
BANK,COL b
CAS Latency - 2
DOUT n DOUT n+1 DOUT n+2
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP READ NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b
BANK,COL n
BANK,COL b
CAS Latency - 2
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP READ NOP NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b
BANK,COL n
BANK,COL b
CAS Latency - 3
CONSECUTIVE READ BURSTS
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
READ READ READ READ NOP NOP
DOUT n DOUT b DOUT m DOUT x
BANK,COL n
BANK,COL b
CAS Latency - 2
BANK,COL m
BANK,COL x
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ READ READ READ NOP NOP NOP
DOUT n DOUT b DOUT m DOUT x
BANK,COL n
BANK,COL b
CAS Latency - 3
BANK,COL m
BANK,COL x
RANDOM READ ACCESSES
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DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK a,COL n
CAS Latency - 2
x = 1 cycle
BURSTTERMINATE
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP NOP NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK,COL n
CAS Latency - 3
x = 2 cycles
BURSTTERMINATE
READ BURST TERMINATION
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ALTERNATING BANK READ ACCESSES
BANK 0 BANK 3 BANK 3 BANK 0
DON'T CARE
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tRCD - BANK 0 CAS Latency - BANK 0 tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tCHtCLtCK
tCMS tCMH
tCKS tCKH
ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE
ROW
ROW
BANK 0
ROW ROW
tRRD tRCD - BANK 3
tRP - BANK 0
COLUMN m(2) ROW COLUMN b(2) ROW
ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8
tAC
tOH tOH tOH tOH tOH
DOUT m DOUT m+1 DOUT m+2 DOUT m+3 DOUT b
tAC tAC tAC tAC tAC
tLZ
CAS Latency - BANK 3
Notes:1) CAS latency = 2, Burst Length = 42) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
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READ - FULL-PAGE BURST
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP
tAS tAH
tAS tAH
tAS tAH
ROW
ROW
BANK
COLUMN m(2)
tCHtCLtCK
tCMS tCMH
tCKS tCKH
BANK
tRCD CAS Latency
tAC tACtAC tACtAC tHZ
tLZ
tAC
tOH tOH tOH tOH tOH tOH
DOUT m DOUT m+1 DOUT m+2 DOUT m-1 DOUT m DOUT m+1
each row (x16) has512 locations(3)
Full pagecompletion
Full-page burst not self-terminating.Use BURST TERMINATE command.
T0 T1 T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4
Notes:1) CAS latency = 2, Burst Length = Full Page2) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"3) x8: Each row has 1,024 locations.
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READ - DQM OPERATION
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP READ NOP NOP NOP NOP NOP NOP
tAS tAH
tAS tAH
tAS tAH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
tRCD CAS Latency
DOUT m DOUT m+2 DOUT m+3
COLUMN m(2)
BANK
tCHtCLtCK
tCMS tCMH
tCKS tCKH
tOHtOHtOH tACtAC
tACtHZ tHZtLZ tLZ
T0 T1 T2 T3 T4 T5 T6 T7 T8
Notes:1) CAS latency = 2, Burst Length = 42) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
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DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP NOP ACTIVE NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK a,COL n
BANK a,ROW
BANK(a or all)
CAS Latency - 2
tRP
PRECHARGE
tRQL High-Z
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP NOP NOP ACTIVE
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK,COL n
BANK,COL b
CAS Latency - 3
tRP
tRQL
BANK a,ROW
PRECHARGE
High-Z
READ to PRECHARGE
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CLK
CKEHIGH
COLUMN ADDRESS
AUTO PRECHARGE
BANK ADDRESS
CS
RAS
CAS
WE
A0-A9
A10
BA0, BA1
NO PRECHARGE
A11, A12
WRITE COMMAND
ThestartingcolumnandbankaddressesareprovidedwiththeWRITEcommand,andautoprechargeiseitherenabledor disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericWRITEcommandsusedinthefollowing illustrations, auto precharge is disabled.
DuringWRITEbursts,thefirstvaliddata-in element will be registered coincident with the WRITEcommand. Subsequent data elements will be registered on each successive posi-tiveclockedge.Uponcompletionofafixed-lengthburst,assuming no other commands have been initiated, the DQswillremainHigh-Zandanyadditionalinputdatawillbeignored(seeWRITEBurst).Afull-pageburstwillcon-tinue until terminated. (At the end of the page, it will wrap to column 0 and continue.)
DataforanyWRITEburstmaybetruncatedwithasubse-quentWRITEcommand,anddataforafixed-lengthWRITEburstmaybe immediately followedbydata foraWRITEcommand.ThenewWRITEcommandcanbe issuedonanyclockfollowingthepreviousWRITEcommand,andthedata provided coincident with the new command applies to the new command.
AnexampleisshowninWRITEtoWRITEdiagram.Datan + 1 is either the last of a burst of two or the last desired ofa longerburst.The256MbSDRAMusesapipelinedarchitecture and therefore does not require the 2n rule as-sociatedwithaprefetcharchitecture.AWRITEcommandcan be initiated on any clock cycle following a previous WRITEcommand.Full-speedrandomwriteaccesseswithina page can be performed to the same bank, as shown in RandomWRITECycles,oreachsubsequentWRITEmaybe performed to a different bank.
DataforanyWRITEburstmaybetruncatedwithasubse-quentREADcommand,anddataforafixed-lengthWRITEburstmaybeimmediatelyfollowedbyasubsequentREADcommand.OncetheREADcommandisregistered,thedatainputswillbeignored,andWRITEswillnotbeex-ecuted.AnexampleisshowninWRITEtoREAD.Datan + 1 is either the last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followedby,or truncatedwith,aPRECHARGEcommandto thesame bank (provided that auto precharge was not acti-vated), anda full-pageWRITEburstmaybe truncatedwithaPRECHARGEcommand to thesamebank.ThePRECHARGEcommandshouldbeissuedtdpl after the clock edge at which the last desired input data element isregistered.Theautoprechargemoderequiresatdpl of at least one clock plus time, regardless of frequency. In addition,whentruncatingaWRITEburst,theDQMsignalmust be used to mask input data for the clock edge prior to,andtheclockedgecoincidentwith,thePRECHARGEcommand.AnexampleisshownintheWRITEtoPRE-CHARGEdiagram.Datan+1 is either the last of a burst oftwoorthelastdesiredofalongerburst.FollowingthePRECHARGEcommand,asubsequentcommandtothesame bank cannot be issued until trp is met.
Inthecaseofafixed-lengthburstbeingexecutedtocomple-tion,aPRECHARGEcommand issuedat theoptimumtime (as described above) provides the same operation that wouldresult fromthesamefixed-lengthburstwithautoprecharge.ThedisadvantageofthePRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantageofthePRECHARGEcommandisthatitcanbeusedtotruncatefixed-lengthorfull-pagebursts.
Fixed-lengthorfull-pageWRITEburstscanbetruncatedwiththeBURSTTERMINATEcommand.Whentruncat-ingaWRITEburst,theinputdataappliedcoincidentwiththeBURSTTERMINATEcommandwillbeignored.Thelastdatawritten(providedthatDQMisLOWatthattime)will be the input data applied one clock previous to the BURSTTERMINATEcommand.ThisisshowninWRITEBurstTermination,wheredatan is the last desired data element of a longer burst.
WRITESWRITEburstsareinitiatedwithaWRITEcommand,asshowninWRITECommanddiagram.
Note:A9is"Don'tCare"forx16.
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3
WRITE NOP NOP NOP
DIN n DIN n+1
BANK,COL n
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2
WRITE NOP WRITE
DIN n DIN n+1 DIN b
BANK,COL n
BANK,COL b
DON'T CARE
WRITE BURST
WRITE TO WRITE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3
WRITE WRITE WRITE WRITE
DIN n DIN b DIN m DIN x
BANK,COL n
BANK,COL b
BANK,COL m
BANK,COL x
RANDOM WRITE CYCLES
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DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
WRITE NOP READ NOP NOP NOP
DIN n DIN n+1 DOUT b DOUT b+1
BANK,COL n
BANK,COL b
CAS Latency - 2
WRITE to READ
WP1 - WRITE to PRECHARGE
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
WRITE NOP NOP NOP ACTIVE NOP
BANK a,COL n
BANK a,ROW
BANK(a or all)
tDPL
tRP
PRECHARGE
DIN n DIN n+1 DIN n+2
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2
WRITE
DIN n (DATA)
BANK,COL n
DON'T CARE
(ADDRESS)
BURSTTERMINATE
NEXTCOMMAND
WRITE Burst Termination
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
WRITE NOP NOP NOP NOP ACTIVE
BANK a,COL n
BANK a,ROW
BANK(a or all)
tDPL
tRP
PRECHARGE
DIN n DIN n+1
WP2 - WRITE to PRECHARGE
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DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
tAS tAH
tAS tAH
tAS tAH
tDS tDH tDS tDH tDS tDH
ROW
ROW
BANK
tRCD
DIN m DIN m+1 DIN m+2 DIN m+3 DIN m-1
COLUMN m(2)
tCHtCLtCK
tDS tDH tDS tDH tDS tDH
tCMS tCMH
tCKS tCKH
BANK
Full page completed
T0 T1 T2 T3 T4 T5 Tn+1 Tn+2
WRITE - FULL PAGE BURST
Notes:1) Burst Length = Full Page2) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
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DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP WRITE NOP NOP NOP NOP NOP
tAS tAH
tAS tAH
tAS tAH
tDS tDH tDS tDH tDS tDH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
tRCD
DIN m DIN m+2 DIN m+3
COLUMN m(2)
BANK
tCHtCLtCK
tCMS tCMH
tCKS tCKH
T0 T1 T2 T3 T4 T5 T6 T7
WRITE - DQM OPERATION
Notes:1) Burst Length = 42) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
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ALTERNATING BANK WRITE ACCESSES
BANK 0 BANK 1 BANK 1 BANK 0
DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tDS tDH tDS tDH tDS tDH
tRCD - BANK 0 tRCD - BANK 0tDPL - BANK 1
tRAS - BANK 0tRC - BANK 0
tCHtCLtCK
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
tCMS tCMH
tCKS tCKH
ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
DIN m DIN m+1 DIN m+2 DIN m+3 DIN b DIN b+1 DIN b+2 DIN b+3
ROW
ROW
BANK 0
ROW ROW
tRRD tRCD - BANK 1
tDPL - BANK 0 tRP - BANK 0
COLUMN m(2) ROW COLUMN b(2) ROW
ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Notes:1) Burst Length = 42) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
46 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
NOP WRITE NOP NOP
BANK a,COL n
DIN n DIN n+1 DIN n+2
INTERNALCLOCK
DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP NOP NOP
BANK a,COL n
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
INTERNALCLOCK
CLOCK SUSPENDClock suspend mode occurs when a column access/burst is inprogressandCKEisregisteredLOW.In theclocksuspendmode,theinternalclockisdeactivated,“freezing”the synchronous logic.
ForeachpositiveclockedgeonwhichCKEissampledLOW,thenextinternalpositiveclockedgeissuspended.Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data presentontheDQpinsremainsdriven;andburstcountersare not incremented, as long as the clock is suspended. (See following examples.)
ClocksuspendmodeisexitedbyregisteringCKEHIGH;the internal clock and related operation will resume on the subsequent positive clock edge.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Integrated Silicon Solution, Inc. — www.issi.com 47Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
CLOCK SUSPEND MODE
Notes:1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled.2) X16: A9, A11, and A12 = "Don't Care" X8: A11 and A12 = "Don't Care"
DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tCHtCLtCK
tCMS tCMH
tCKS tCKH
COLUMN m(2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
READ NOP NOP NOP NOP NOP WRITE NOP
tCKS tCKH
BANK BANK
COLUMN n(2)
tAC tAC
tOH
tHZ
DOUT m DOUT m+1
tLZ
UNDEFINED
DIN e+1
tDS tDH
DIN e
48 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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CLK
CKEHIGH
ALL BANKS
BANK SELECT
BANK ADDRESS
CS
RAS
CAS
WE
A0-A9, A11, A12
A10
BA0, BA1
DON'T CARE
CLK
CKE
COMMAND NOP NOP ACTIVE
≥ tCKStCKS
All banks idle
Enter power-down mode Exit power-down mode
tRCD
tRAS
tRC
Input buffers gated off
less than 64ms
PRECHARGE Command
POWER-DOWN
POWER-DOWNPower-downoccursifCKEisregisteredLOWcoincidentwithaNOPorCOMMANDINHIBITwhennoaccessesareinprogress.Ifpower-downoccurswhenallbanksareidle,thismodeisreferredtoasprechargepower-down;ifpower-downoccurswhenthereisarowactiveineitherbank, this mode is referred to as active power-down.Entering power-down deactivates the input and outputbuffers,excludingCKE,formaximumpowersavingswhileinstandby.Thedevicemaynotremaininthepower-downstatelongerthantherefreshperiod(64ms)sincenorefreshoperations are performed in this mode.
Thepower-downstateisexitedbyregisteringaNOPorCOMMANDINHIBITandCKEHIGHatthedesiredclockedge (meeting tcks). See figure below.
PRECHARGEThePRECHARGEcommand(seefigure)isusedtodeac-tivate the open row in a particular bank or the open row in allbanks.Thebank(s)willbeavailableforasubsequentrowaccess some specified time (trp)afterthePRECHARGEcommand is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only onebankistobeprecharged,inputsBA0,BA1selectthebank.Whenallbanksaretobeprecharged,inputsBA0,BA1aretreatedas“Don’tCare.”Onceabankhasbeenprecharged, it is in the idle state and must be activated priortoanyREADorWRITEcommandsbeingissuedtothat bank.
Integrated Silicon Solution, Inc. — www.issi.com 49Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
POWER-DOWN MODE CYCLE
DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tAS tAH
BANK
tCHtCLtCK
tCMS tCMH
tCKS tCKH
PRECHARGE NOP NOP NOP ACTIVE
ALL BANKS
SINGLE BANK
ROW
ROW
BANK
tCKStCKS
Precharge allactive banks
All banks idleTwo clock cycles Input buffers gatedoff while in
power-down modeAll banks idle, enterpower-down mode Exit power-down mode
T0 T1 T2 Tn+1 Tn+2
High-Z
50 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DOUT a DOUT a+1 DOUT b DOUT b+1
BANK n,COL a
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
tRP - BANK n tRP - BANK m
READ - APBANK n
READ - APBANK m
Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active READ with Burst of 4 Precharge
Internal States
BANK n,COL b
BURST READ/SINGLE WRITETheburstread/singlewritemodeisenteredbyprogrammingthe write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of theprogrammedburstlength.READcommandsaccess columns according to the programmed burst length and sequence,justasinthenormalmodeofoperation(M9=0).
CONCURRENT AUTO PRECHARGEAnaccesscommand(READorWRITE)toanotherbankwhile an access command with auto precharge enabled is executingisnotallowedbySDRAMs,unlesstheSDRAMsupports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMssupportCONCURRENTAUTOPRECHARGE.FourcaseswhereCONCURRENTAUTOPRECHARGEoccurs are defined below.
READ with Auto Precharge1.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankmwill interruptaREADonbankn,CAS latency later.The PRECHARGE to bank n willbeginwhentheREADtobankmisregistered.
2.InterruptedbyaWRITE(withorwithoutautoprecharge):AWRITEtobankmwillinterruptaREADonbanknwhenregistered.DQMshouldbeusedthreeclockspriortotheWRITEcommandtopreventbuscontention.ThePRECHARGEtobanknwillbeginwhentheWRITEtobank m is registered.
READ With Auto Precharge interrupted by a READ
READ With Auto Precharge interrupted by a WRITE
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DOUT a DIN b DIN b+1 DIN b+2 DIN b+3
BANK n,COL a
BANK m,COL b
CAS Latency - 3 (BANK n)
tRP - BANK n tDPL - BANK m
READ - APBANK n
WRITE - APBANK m
READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active WRITE with Burst of 4 Write-Back
Internal States Page Active
Integrated Silicon Solution, Inc. — www.issi.com 51Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DIN a DIN a+1 DOUT b DOUT b+1
BANK n,COL a
BANK m,COL b
CAS Latency - 3 (BANK m)
tRP - BANK ntRP - BANK m
WRITE - APBANK n
READ - APBANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active READ with Burst of 4 Precharge
Internal States tDPL - BANK n
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
BANK n,COL a
BANK m,COL b
tRP - BANK ntDPL - BANK m
WRITE - APBANK n
WRITE - APBANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active WRITE with Burst of 4 Write-Back
Internal States tDPL - BANK n
DIN a DIN a+1 DIN a+2 DIN b DIN b+1 DIN b+2 DIN b+3
WRITE with Auto Precharge3.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankmwillinterruptaWRITEonbanknwhenregistered, with the data-out appearing (CAS latency) later.ThePRECHARGEtobanknwillbeginaftertdpl is met, where tdplbeginswhentheREADtobankmisregistered.ThelastvalidWRITEtobanknwillbedata-inregisteredoneclockpriortotheREADtobankm.
4.InterruptedbyaWRITE(withorwithoutautoprecharge):AWRITE to bank m will interrupt a WRITE on bank n when registered.ThePRECHARGEtobanknwillbeginaftertdpl is met, where tdplbeginswhentheWRITEtobankmisregistered.ThelastvaliddataWRITEtobanknwillbedataregisteredoneclockpriortoaWRITEtobank m.
WRITE With Auto Precharge interrupted by a READ
WRITE With Auto Precharge interrupted by a WRITE
52 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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READ WITH AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
tAS tAH
tAS tAH
tAS tAH
ROW
ROW
BANK
COLUMN m(2)
tCHtCLtCK
tCMS tCMH
tCKS tCKH
BANK
tRCD
tRAS
tRC
CAS Latency
tAC tAC tAC tAC
tOH
tHZ
tOH
DOUT m
tOH
DOUT m+1
tOH
DOUT m+2 DOUT m+3
T0 T1 T2 T3 T4 T5 T6 T7 T8
tRP
ENABLE AUTO PRECHARGE
ROW
ROW
BANK
tLZ
Notes:1) CAS latency = 2, Burst Length = 42) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com 53Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
READ WITHOUT AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE
tAS tAH
tAS tAH
tAS tAH
ROW
ROW
BANK
COLUMN m(2)
tCHtCLtCK
tCMS tCMH
tCKS tCKH
BANK
tRCD CAS Latency
tAC tAC tAC tAC
tOH
tHZ
tOH
DOUT m
tOH
DOUT m+1
tOH
DOUT m+2 DOUT m+3
T0 T1 T2 T3 T4 T5 T6 T7 T8
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
tLZ
tRAS
tRC
tRP
ALL BANKS
SINGLE BANK
BANK
Notes:1) CAS latency = 2, Burst Length = 42) x16: A9, A11, A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
54 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
SINGLE READ WITH AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP
tAS tAH
tAS tAH
tAS tAH
ROW
ROW
BANK
COLUMN m(2)
tCHtCLtCK
tCMS tCMH
tCKS tCKH
BANK
tRCD
tRAS
tRC
CAS Latency
tAC
tHZ
tOH
DOUT m
T0 T1 T2 T3 T4 T5 T6 T7 T8
tRP
ENABLE AUTO PRECHARGE
ROW
ROW
BANK
Notes:1) CAS latency = 2, Burst Length = 12) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com 55Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
SINGLE READ WITHOUT AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP READ NOP NOP PRECHARGE NOP ACTIVE NOP
tAS tAH
tAS tAH
tAS tAH
ROW
ROW
BANK
COLUMN m(2)
tCHtCLtCK
tCMS tCMH
tCKS tCKH
BANK
tRCD
tRAS
tRC
CAS Latency
tAC
tHZ
tOH
DOUT m
T0 T1 T2 T3 T4 T5 T6 T7 T8
tRP
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
tLZ
ALL BANKS
SINGLE BANK
BANK
Notes:1) CAS latency = 2, Burst Length = 12) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
56 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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WRITE - WITH AUTO PRECHARGE
DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tRCD
tRAS
tRC
tCHtCLtCK
tCMS tCMH
tCKS tCKH
ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE
tDPL tRP
COLUMN m(2) ROW
BANK BANK
ENABLE AUTO PRECHARGEROW
ROW
ROW
BANK
tDS tDH tDS tDH tDS tDHtDS tDH
DIN m DIN m+1 DIN m+2 DIN m+3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Notes:1) Burst Length = 42) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com 57Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
WRITE - WITHOUT AUTO PRECHARGE
DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tRCD
tRAS
tRC
tCHtCLtCK
tCMS tCMH
tCKS tCKH
ACTIVE NOP WRITE NOP NOP NOP PRECHARGE NOP ACTIVE
tDPL(3) tRP
COLUMN m(2) ROW
DISABLE AUTO PRECHARGEROW
ROW
ROW
BANK
tDS tDH tDS tDH tDS tDHtDS tDH
DIN m DIN m+1 DIN m+2 DIN m+3
BANK BANK BANK
ALL BANKS
SINGLE BANK
T0 T1 T2 T3 T4 T5 T6 T7 T8
Notes:1) Burst Length = 42) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"3) tras must not be violated.
58 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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SINGLE WRITE WITH AUTO PRECHARGE
Notes:1) Burst Length = 12) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"
DON'T CARE
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tDS tDH
tRCD
tRAS
tRC
tCHtCLtCK
tCMS tCMH
tCKS tCKH
ACTIVE NOP NOP NOP WRITE NOP NOP NOP ACTIVE NOP
tDPL tRP
COLUMN m(2) ROW
BANK BANK
ENABLE AUTO PRECHARGE
ROW
ROW
ROW
BANK
DIN m
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Integrated Silicon Solution, Inc. — www.issi.com 59Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
SINGLE WRITE - WITHOUT AUTO PRECHARGE
DON'T CARE
CLK
CKE
COMMAND
DQM/DQMLDQMH
A0-A9, A11, A12
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tDS tDH
tRCD
tRAS
tRC
tCHtCLtCK
tCMS tCMH
tCKS tCKH
ACTIVE NOP WRITE NOP NOP PRECHARGE NOP ACTIVE NOP
tDPL(3) tRP
ROW
ROW
ROW
BANK
DIN m
COLUMN m(2) ROW
BANK BANK BANK
ALL BANKS
SINGLE BANK
T0 T1 T2 T3 T4 T5 T6 T7 T8
DISABLE AUTO PRECHARGE
Notes:1) Burst Length = 12) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care"3) tras must not be violated.
60 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to +70°C Frequency Speed (ns) Order Part No. Package
200MHz 5 IS42S83200G-5TL 54-PinTSOPII,Lead-free
IS42S83200G-5BL 54-BallBGA,Lead-free
166MHz 6 IS42S83200G-6TL 54-PinTSOPII,Lead-free
143MHz 7 IS42S83200G-7TL 54-PinTSOPII,Lead-free IS42S83200G-7BL 54-BallBGA,Lead-free
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS42S16160G-5TL 54-PinTSOPII,Lead-free
IS42S16160G-5BL 54-BallBGA,Lead-free
166MHz 6 IS42S16160G-6TL 54-PinTSOPII,Lead-free IS42S16160G-6BL 54-BallBGA,Lead-free
143MHz 7 IS42S16160G-7TL 54-PinTSOPII,Lead-free IS42S16160G-7BL 54-BallBGA,Lead-free
IS42S16160G-7B 54-BallBGA,Leaded
Industrial Range: -40°C to +85°CFrequency Speed (ns) Order Part No. Package
166MHz 6 IS42S83200G-6TLI 54-PinTSOPII,Lead-free
143MHz 7 IS42S83200G-7TLI 54-PinTSOPII,Lead-free IS42S83200G-7BLI 54-BallBGA,Lead-free
Frequency Speed (ns) Order Part No. Package
166MHz 6 IS42S16160G-6TLI 54-PinTSOPII,Lead-free IS42S16160G-6BLI 54-BallBGA,Lead-free
143MHz 7 IS42S16160G-7TLI 54-PinTSOPII,Lead-free IS42S16160G-7BLI 54-BallBGA,Lead-free
IS42S16160G-7BI 54-BallBGA,Leaded
Integrated Silicon Solution, Inc. — www.issi.com 61Rev. F12/9/2013
IS42S83200G, IS42S16160GIS45S83200G, IS45S16160G
Automotive Range A1: -40°C to +85°CFrequency Speed (ns) Order Part No. Package
166MHz 6 IS45S83200G-6TLA1 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
143MHz 7 IS45S83200G-7TLA1 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn IS45S83200G-7CTLA1 54-PinTSOPII,CuleadframeplatedwithmatteSn IS45S83200G-7BLA1 54-ballBGA,SnAgCuballs
Frequency Speed (ns) Order Part No. Package
166MHz 6 IS45S16160G-6TLA1 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn IS45S16160G-6BLA1 54-ballBGA,SnAgCuballs
143MHz 7 IS45S16160G-7TLA1 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn IS45S16160G-7CTLA1 54-PinTSOPII,CuleadframeplatedwithmatteSn IS45S16160G-7BLA1 54-ballBGA,SnAgCuballs
Automotive Range A2: -40°C to +105°CFrequency Speed (ns) Order Part No. Package
143MHz 7 IS45S83200G-7TLA2 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn IS45S83200G-7CTLA2 54-PinTSOPII,CuleadframeplatedwithmatteSn
Frequency Speed (ns) Order Part No. Package
166MHz 6 IS45S16160G-6CTLA2 54-PinTSOPII,CuleadframeplatedwithmatteSn
IS45S16160G-6BLA2 54-PinTSOPII,SnAgCuballs
143MHz 7 IS45S16160G-7TLA2 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS45S16160G-7CTLA2 54-PinTSOPII,CuleadframeplatedwithmatteSn IS45S16160G-7BLA2 54-ballBGA,SnAgCuballs
Notes: 1. Contact ISSI for leaded and copper lead frame parts support.2.Partnumberswith"L"areleadfree,andRoHScompliant.
62 Integrated Silicon Solution, Inc. — www.issi.com Rev. F
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