185

2006 IEEE Electrical Performance of Electronic Packaging

Accurate System Voltage and Timing Margin

Simulation in CDR Based High Speed Designs

Frank Lambrecht, Qi Lin, Sam Chang, DanOh, Chuck Yuan, and Vladimir StojanovicRambus Inc.

4438 El Camino Real, Los Altos, CA 94022Phone: (650)-947-5326, FAX: (650)-947-5001, frankli rambus.com

Abstract-Accurate analysis system timing and voltage margin at a target bit error rate across process, voltage, and temperature

variations is required for high volume production of high speed systems. This in turn requires a statistical simulation framework to

advanced signaling techniques such as transmitter equalization and receiver decision feedback.Furthermore, telecommunication networking serial links, one must also carefully model the clock-data recovery circuits

(CDR) impact on system voltage and timing margin. In this paper, we first present a stochastic simulation

modeling methodology for circuits. We then compare the simulation results based on modeling

simple method, quadrature sampling based timing recovery model. Finally, we correlate the simulation results to lab

measurements to validate the proposed approach.

I. INTRODUCTIONT

prediction is becoming increasingly important for high speed links at multi-gigahertz data rates. The

successfully prediction ofrate requires the complete consideration of the overall signaling architecture including

advanced circuit components these speeds. Due to the large channel inter-symbol interference, the eye diagram at

completely closed. For example, a statistical eye diagram is shown in Figure1 where the bit error rate is shown

voltage timing Within this figure we see the resultant statistical eye with and without considering the receiver

complex receiver architecture that includes adaptive decision feedback equalization [1]. This

including receiver processing effects requires signal integrity analysis to include more behavioral circuit

modeling than was needed in the past in order to accurately predict system performance.

Probabiity of Erorvs.g oltage Marginh at Different OD ROR f s Pr obabiIity of Erro|r Vs Voltage Margin at Differn t ODROffsetni E

2100 22 0

150 -2 ~~~~~~~~~~~~~~150-

100~~~~~~~~~~~ 1~~~00

-0E100 1 01-5 -10

Fig. IReceived eye with and without RX behavioral model post processing

Traditionally, the circuit effects have been taken into account in channel voltage and timing budget as a separate budgetitem. SimplifiedIO driver models simulated with passive network models have been used to characterize the channelperformance. Such an approach is no longer acceptable for analysis of high-speed designs. As a result, accurate systemsimulation of high speed links requires that we include increasingly more detailed models of these architectural blocks to fullycapture the voltage and timing effects. These details include discrete resolution such as quantization from transmitterequalization, decision feedback and feed forward equalization coefficients and modeling of the algorithms used to determinecoefficients. We need to model the effects of recovered clock sample point variation and other sources of circuit based variationinperformance. Typical clock recovery circuits are responsive to various contributors to edge timing movement which includedatapattern variations, inter-symbol interference characteristics of the channel, and random noise events on the channel. Inaddition, filtering is typically applied to the phase update decision. These recovered clocking effects must be considered within abroader framework for analysis of anI/O subsystem. Examples of such simulation toolsets are described in [2-5]. For thesimulations presented here we use the Rambus developed LinkLab signal integrity simulation toolset. We introduce theLinkLab's CDR modeling methodology in the next section. We then show that simplified assumptions about clock timing for

rec ver d cocksysemsdo otacc ratly redct yst m p rfrma ce ase onthesim latonto ab eas rem nt orrla10n

recovered clock systems do not accurately predict system performance based on the simulation to lab measurement correlation.

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II. MODELING METHODOLOGYThe LinkLab toolset statistically simulates high speed links in the time domain. A basic flowchart for such a simulation

methodology is shown in Fig. 2 below. The transmitter model captures the driver including equalizer covering differentequalization algorithms and quantization error as well as power constraints. The channel block integrates all the passive circuitcomponents including motherboard trace and device models such as Ri/Ci, package and connectors. The determination of ISIprobability density function can be obtained as in [6], when generalized to the data pattern set under consideration. After passingreceiver linear equalizer, the signal is processed by analog decision feedback equalizer (DFE). It selects from the variousschemes of DFE based on the circuit design under consideration. The last step is to feed the statistical description of the receivedwaveform into the CDR with the random and deterministic jitter components. Additional effects are also modeled includingtransmit and receive PLL phase variations due to noise effects and imperfect reference clock, termination thermal noise andother variation sources. The system voltage/timing margin calculation computes the bathtubs of bit error rate (BER) vs time andvoltage offsets as well as a statistical eye diagram.

Input Pulse Tx Equalizer TX Jitter Channel S- -N ISI Probability Density FunctionParameters

|System Voltage/Timing Margin DFE[1

|Crosstalk and RX Jitter

Fig. 2 Simulation flowchart

Within the flowchart of Fig. 2 we will be focusing on impact of accurate CDR behavioral modeling. Recovered clock phaseis most impacted by the timing and voltage noise distorted waveforms input to the phase recovery circuit. The major contributorsto timing and voltage noise can be broken in three sets: i) due to channel, package, and parasitic inter-symbol interference, ii)effective receiver referenced voltage noise distribution from transmitter and receiver jitter from thermal, power supply andreference clock noise sources, and iii) recovered clock sample point distribution. To these we also add the behavioral effects oftransmit and receive signal processing circuits which include both corrective and additional noise sources. Total received signalerror can be described by Eq. (1), where xjISI, xjitTx,XjitRx represent interference, and receiver voltage noise from transmitter andreceiver jitter, respectively. As seen in Fig. 3, data pulses are labeled as bk, edge jitter values asSk, channel pulse response

samples asPk, and channel impulse response samples as hk. Indexes sbS and sbE mark the beginning and end of the channelpulse/impulse response.

Xk= X7i+ +xitRX (1it)s bE

XkE bk-n p,n=-sbS

sbE

xJ.ItTx Z b X(n kXlgYX

k>

kn (hn-IEk-n+l hn£k Tn)n=-sbS

sbEk

=

kE

kn (hn- n-I

n=-sbS

bkbk ;(a) b T

T-1 (k+l)T >(b) + k + I)T

TX ~ ~ ~ ~ bTbkkk

Fig. 3 Jittered pulse decomposition. A symbol transmitted with jitter is converted to a symbol with no jitter (a), plus a noise term where the noise-symbol's widths (b) are equaltoEkTX andk+]TX.

We apply superposition principles to add the effects of residual ISI in generating an effective statistical eye description. Fromthese resultant distributions as sampled by the clock recovery circuits we are able to generate stochastic descriptions of thereceived clock timing. This is shown in Fig 4. This variation in receiver timing is then used to condition the incoming data eye

distributions to result in final bit error rate and margin predictions.

172

.HS

n 0.8-Accumulate-resz

X- filter, length 40.6-

0.4 p-earl

0.2-

P-UP p-dn

p-no-valid

transitions \ _,

Iy' p-late

-PholdiPdnli

9~ s _J '- -28I

%

p-hold

00 50 100 150 200 250

Phase count

Fig. 4 (left) The raw input probabilities (p-early, p-late, p-no-valid transition) are converted by a filter to state transition probabilities (p-up, p-dn, p-

hold) for each possible phase position; (right) First-order Markov chain phase-state model. Each state represents a different phase position, and the arcs

are the probability of transition, given that position.

This simulation framework can be extended to include additional design features for modeling and optimization. As in [7]where we model the impact of low power design techniques on the bit error rate of high speed links through delay variationmodeling and do sample trade-offs for a 15 Gbps link over 8" of FR4. These methods enable tradeoffs in speed, equalizationapproach, and power to be made while predicting the bit error rate of the link.

III. RESULTS AND DISCUSSIONFor the simulation and lab correlation in this paper we use 4-tap differential transmit equalization and receiver architecture

as shown in Figure 5. A random data pattern was simulated, where each bit is assumed to be independent of the previous bit. Forthe lab analysis we used a 2 31 PRBS data patterns. Given the limited time history of residual ISI for a passive link, this is a

valid comparison.

t Eqtializer Driverl

PLL Phs oto

f A i 4hase Detector

Fig. 5 I/O architecture

The 30" backplane channel used in this analysis is shown in Fig. 6. The backplane and paddle card designs are manufactured ina 14 layer FR4 PCB. The backplane trace used was located on an upper layer leaving approximately a 100 mil via stub on thisnet. On the paddle card a 60 mil via stub remained on the net. The connector pinset chosen used the longest length (GH on

HMZD connector). This length and transfer characteristic is typical for a long backplane serial link application, where thechannel has -18dB insertion loss at 2.5 GHz. For this channel to operate at 5 Gbps, one must use advanced signaling to recover

the data at the receiver.

I Hi=-L16 9 [dB] (Victim=n blue, FEXT=- green, NEXT= retd)

Short SMVA _=r Cable ~~~~~~~~~~~~Short SMVA ->lCable~~~ ~ ~ ~~~~~~~~~Cbl 1O

PaddleCard 1 _20 - -T T---20L=3aa . ~~~~~~~~~~~~~~PaddleCard m ,L=3" 4

Connector HMZD 0 1 2 3 4 5

Connector .GF

Fig. 6 Typical high speed backplane channel and its transfer function

Lab and LinkLab simulation results are shown in Fig. 7 below. In addition to the 30" backplane channel an additional resultis shown for a shorter 16" backplane trace. This (+/- mV) voltage margin is defined to be at the bit error rate of 10A-15. This can

173

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also be thought of as the positive or negative differential offset that can be applied to the receiver required to increase the biterror rate to the 10- 15 level.

250

200

16"- Sim 30"- Sim

16"- Lab - 30"- Lab

150

E100

50

2.9 3.4 3.9 4.4

Data Rate (Gbs)

4.9 5.4 5.9

Fig. 7 Lab vs. simulation comparison

Fig. 8 shows the system voltage margin result with additional simulation results using a receiver model which samples datain quadrature rather than using the more complete CDR behavioral model. As can be seen in this plot, the difference betweenincluding and not including the CDR model has an effect of (+/-) 5-19 mV or 10-38 mV peak-peak for these speeds and channel.We can see that this difference is not constant across frequency and also varies with channel choice, a simplified single offsetterm would lead to overly pessimistic simulation results for most channels.

BER Vs additional ItN offset, 4A4 Gbps160 0

Quadrature-140 With CDR Model

. . ~~~~~Lab Data120

w80 -m

E

0-

With CDR20 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Quad ratu re

Lab Data

3 3.5 4 4.5 5 5.5-5 -100 -50 0 50 100 150Data Rate (Gbps) additional voftd offset [mVJ

Fig. 8 (left) Margin Results vs Data Rate using Stochastic CDR model, using Simplified Quadrature Timing Model, and Lab Data (right) SampleVoltage Bathtub plot for same 3 data sets at 4.4Gbps frequency point.

As we have seen, the signal integrity analysis of high speed links is becoming more challenging. Additional complexity inthe behavioral modeling of JO circuits is required. Within this new framework is a strong interdependence between channel andcircuit design. This paper describes a general approach to such simulations and describes behavioral simulation of a clock datarecovery block. We show the accuracy benefits of such modeling for a sample long backplane channel at speeds of 3.4 -5.4Gbps.

RiEFERENCES

[1] J. Zerbe, Qi Lin, V. Stajonovic, A. Ho, R. Kollipara, F. Lambrecht, C. Werner, "Comparison of adaptive and non-adaptive equalizationmethods in high-performance backplanes", DesignCon '05

[2] V. Stojanovic, M. Horowitz, "Modeling and analysis of high-speed links", CICC '03, pp.589-94[3] V. Stojanovic, A. Amirkhany, M.A. Horowitz, "Optimal linear precoding with theoretical and practical data rates in high-speed serial-link

backplane communication", ICC '04, pp.2799-2806[4] B.K. Casper, M. Haycock, R. Mooney, "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes", IEEE

~Symposium on VLS,I Circuits, 2002[5] A. Sanders, M. Resso, J. D'Ambrosia, "Channel compliance testing utilizing novel statistical eye methodology", DesignCon '04[6] D. Oh, "Multiple Edge Responses for Fast and Accurate System Simulations", IEEE Electrical Performance ofElectronic Packages

Conference '06, submitted for publication.[7] H. Hatamkhani, F. Lambrecht, V. Stojanovic, C.K. Yang "Power Centric Design of High-Speed I/Os" 43rd Design Automation

Conference, 2006.Paper 50.4

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