Ipad2 Sch LamApple
42
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 8 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 3 B 7 ECN REV BRANCH DRAWING NUMBER REVISION SIZE D PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. DRAWING TITLE THE POSESSOR AGREES TO THE FOLLOWING: Apple Inc. SHEET R DATE D A C THE INFORMATION CONTAINED HEREIN IS THE 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. PAGE NOTICE OF PROPRIETARY PROPERTY: A C 3 4 5 6 D B 8 7 6 5 4 2 1 1 2 APPD CK DESCRIPTION OF REVISION DRAWING PVT K94 CHOPIN MLB REV. A PRODUCTION RELEASED 2011-01-10 A.0.0 1 OF 106 051-8962 0001052699 A 1 OF 42 LAST_MODIFIED=Mon Jan 10 13:11:06 2011 CHOPIN MLB JAMES 7 N/A AP: I/Os 5 AP: VIDEO BUFFER,BB USB MUXES 13 11 JAMES N/A CONSTRAINTS: RF RULES 106 N/A 42 MIKE VIDEO: MLC ALIASES MIKE 15 21 N/A SYNC MASTER PDF CONTENTS DATE CSA N/A POWER: ALIASES YOSH 73 32 33 N/A 75 YOSH POWER: BATTERY CONNECTOR 39 N/A MIKE 100 CONSTRAINTS: ASSIGNMENTS CONSTRAINTS: ASSIGNMENTS N/A MIKE 40 101 CONSTRAINTS: MLB RULES N/A 102 MIKE 41 38 N/A 93 FCT/ICT TEST/BRACKETS MIKE N/A 36 83 YOSH POWER: 3.3V VR N/A 19 36 LENG AUDIO: L63 CODEC POWER: PMU N/A YOSH 81 34 POWER: PMU YOSH N/A 82 35 N/A 6 8 JAMES AP: NAND JAMES 8 N/A 10 AP: PWR MIKE DEBUG AND MISC N/A 90 37 30 N/A 60 MIKE CONNECTOR: X23 WIFI/BT 9 AP: PWR 11 JAMES N/A IO FLEX: DOCK COMPONENTS N/A 57 JAMES 28 39 LENG 22 AUDIO: BLANK N/A VIDEO: MLC 14 N/A 20 MIKE ABBREV=DRAWING TITLE=BACH 23 N/A 42 LENG AUDIO: DETECT/MIC BIAS VIDEO: DISPLAY PORT 13 17 JAMES N/A 21 38 LENG N/A AUDIO: HEADPHONE OUT AP: MISC & ALIASES 10 N/A 12 JAMES 4 N/A 6 JAMES AP: MAIN CONNECTOR: X24 CELLULAR/GPS 31 N/A 61 MIKE 59 29 N/A JAMES IO FELX: B2B Connector CONNECTOR: SENSOR PANEL CONNECTOR MARK B. 27 N/A 56 55 CONNECTOR: CANADA FLEX FILTERS 26 N/A MARK B. LENG N/A 24 43 AUDIO: HP/MIC FILTERS AP: TV,DP,MIPI 7 N/A 9 JAMES N/A MIKE 3 5 BOM TABLE 18 RAMSIN N/A 31 GRAPE: Z1, Z2 GRAPE: GROUNDHOG,CONN,BOOST RAMSIN 30 N/A 17 22 16 ALEX N/A VIDEO: LVDS CONNECTOR JONATHAN 12 NAND 14 N/A MIKE 2 N/A 2 BLOCK DIAGRAM: SYSTEM 1 N/A 1 MIKE TABLE OF CONTENTS SYNC MASTER CSA PDF DATE CONTENTS 25 N/A 54 MARK B. CONNECTOR: CANADA FLEX CONN,SENSOR PANEL ALIASES AUDIO: SPEAKER AMP 20 N/A 37 LENG
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Transcript of Ipad2 Sch LamApple
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
3
B
7
ECNREV
BRANCH
DRAWING NUMBER
REVISION
SIZE
D
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
DRAWING TITLE
THE POSESSOR AGREES TO THE FOLLOWING:
Apple Inc.
SHEET
R
DATE
D
A
C
THE INFORMATION CONTAINED HEREIN IS THE
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
C
3456
D
B
8 7 6 5 4 2 1
12
APPDCK
DESCRIPTION OF REVISION
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
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PVTK94 CHOPIN MLB
REV. A
PRODUCTION RELEASED 2011-01-10
A.0.0
1 OF 106
051-8962
0001052699A
1 OF 42
LAST_MODIFIED=Mon Jan 10 13:11:06 2011
CHOPIN MLB
JAMES7 N/AAP: I/Os5
AP: VIDEO BUFFER,BB USB MUXES1311 JAMES N/A CONSTRAINTS: RF RULES106 N/A42 MIKE
VIDEO: MLC ALIASES MIKE15 21 N/A
SYNC MASTERPDF CONTENTS DATECSA
N/APOWER: ALIASES YOSH7332
33 N/A75 YOSHPOWER: BATTERY CONNECTOR
39 N/AMIKE100 CONSTRAINTS: ASSIGNMENTS
CONSTRAINTS: ASSIGNMENTS N/AMIKE40 101
CONSTRAINTS: MLB RULES N/A102 MIKE41
38 N/A93 FCT/ICT TEST/BRACKETS MIKE
N/A36 83 YOSHPOWER: 3.3V VR
N/A19 36 LENGAUDIO: L63 CODEC
POWER: PMU N/AYOSH8134
POWER: PMU YOSH N/A8235
N/A6 8 JAMESAP: NAND
JAMES8 N/A10 AP: PWR
MIKEDEBUG AND MISC N/A9037
30 N/A60 MIKECONNECTOR: X23 WIFI/BT
9 AP: PWR11 JAMES N/A
IO FLEX: DOCK COMPONENTS N/A57 JAMES28
39 LENG22 AUDIO: BLANK N/A
VIDEO: MLC14 N/A20 MIKE
ABBREV=DRAWINGTITLE=BACH
23 N/A42 LENGAUDIO: DETECT/MIC BIAS
VIDEO: DISPLAY PORT13 17 JAMES N/A
21 38 LENG N/AAUDIO: HEADPHONE OUT
AP: MISC & ALIASES10 N/A12 JAMES
4 N/A6 JAMESAP: MAIN
CONNECTOR: X24 CELLULAR/GPS31 N/A61 MIKE
5929 N/AJAMESIO FELX: B2B Connector
CONNECTOR: SENSOR PANEL CONNECTORMARK B.27 N/A56
55 CONNECTOR: CANADA FLEX FILTERS26 N/AMARK B.
LENG N/A24 43 AUDIO: HP/MIC FILTERS
AP: TV,DP,MIPI7 N/A9 JAMES
N/AMIKE3 5 BOM TABLE
18 RAMSIN N/A31 GRAPE: Z1, Z2
GRAPE: GROUNDHOG,CONN,BOOST RAMSIN30 N/A17
2216 ALEX N/AVIDEO: LVDS CONNECTOR
JONATHAN12 NAND14 N/A
MIKE2 N/A2 BLOCK DIAGRAM: SYSTEM
1 N/A1 MIKETABLE OF CONTENTS
SYNC MASTERCSAPDF DATECONTENTS
25 N/A54 MARK B.CONNECTOR: CANADA FLEX CONN,SENSOR PANEL ALIASES
AUDIO: SPEAKER AMP20 N/A37 LENG
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
AUDIO CODEC
REAR CAMERA
UART2
SGX543-MP
ARM A5 CPU
AUDIO
USB1.1
GROUNDHOG Z1
Z2
I2S0
LINEOUT
ASP
L63
XSP
AMP
AMP
VSP
DUAL-CORE IMG
UART1
BACKLIGHT
BATTERY
ISP_I2C1
DISPLAY/TOUCH PANEL
LVDS
I2C1
SPI2 IPC
GPSUMTSUSARTUSB1.1
X24
CELLULAR ANT
GPS ANT
BT_I2SUART3
GPU
MIPI0C
MIPI1C
WIFI/BTX23
WIFI/BT ANT
ALISONPMU
SPI1
FF CAMERA
ISP_I2C0
SDIOCORTEX-A9 W/ SMP
MLC
ALSACCELEROMETERGYROSD CARD READER
SPEAKER
HP
MIC
AE2
30-PINDOCK
I2C2
H4P
DUAL-CORE ARM
COMPASSPROX SENSOR
I2C0
AMP
USB2.0
UART4
NAND FLASHNAND FLASH
FMI3FMI2FMI1FMI0 HSIC0
I2S3
UART0
VIDEO DAC
I2S2
ICE3.0/GPS
CSA 60
CSA 36
CSA 58CSA 14 CSA 14
CSA 75
CSA 81
CSA 20
CSA 30 CSA 31
CSA 31
CSA 61
CSA 57
SENSOR PANEL SENSOR PANEL
SENSOR PANEL SENSOR PANEL CANADA FLEX
CANADA FLEX
SENSOR PANEL
DISPLAYPORT
850 MHZ
LPDDR2
400MHZ/800MB/S
2X32-BIT
MIPI0D
UART5
DWI
SYNC_MASTER=MIKE
BLOCK DIAGRAM: SYSTEMSYNC_DATE=N/A
2 OF 106
A.0.0
051-8962
2 OF 42
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
BOTTOM LABEL TYPE 1
BOTTOM LABEL TYPE 2
TOP BARCODE LABEL/EEE CODES(ONLY ONE IS USED PER BOM)
MLC_PROD
ADD DEVELOPMENT AND OTHER BOMS ONCE YOU GET BOM NUMBERS
MLC_DEV
K94K93
PORTRAIT_DOCK
SPEAKERINTERNAL_MIC
DEVELOPMENT_JTAGDEVELOPMENT_JTAG_TAPJTAG_DAPJTAG_TAP_NOT
BKLT_PLL
64GB_PROD32GB_PROD16GB_PROD
BOM OPTIONS PROGRAMMABLE PARTS
Power aliases required by this page:
Signal aliases required by this page:
ALL AVAIL BOM OPTIONS
(NONE)
ALTERNATECOMMON
BOM options provided by this page:
(NONE)
Page Notes
PD PARTS
SCH AND BOARD P/N
FENCE1806-1396 1 FENCE,GRAPE,MLB,K93/K94
EEEE_K94_16G825-7651 EEEE FOR 639-1112 (K94 16G) CRITICAL1 DFC4
BOM TABLESYNC_MASTER=MIKE SYNC_DATE=N/A
825-7651 EEEE FOR 639-1182 (K94 64G)1 EEEE_K94_64GCRITICALDFC6
825-7651 EEEE FOR 639-1430 (K95 16G) EEEE_K95_16GCRITICALDH3C1
825-7651 EEEE FOR 639-1426 (K93 32G) EEEE_K93_32GCRITICAL1 DH37
DH36825-7651 1 EEEE_K93_16GCRITICALEEEE FOR 639-1180 (K93 16G)
CRITICAL631- B/C LABEL825-7639 LBL11
639- B/C LABEL825-7639 LBL21 CRITICAL
EEEE FOR 639-1429 (K95 64G)1825-7651 EEEE_K95_64GCRITICALDG9C
825-7651 1 CRITICALEEEE FOR 639-1428 (K93 64G) EEEE_K93_64GDG99
825-7651 EEEE FOR 639-1181 (K94 32G) EEEE_K94_32G1 CRITICALDFC5
825-7651 CRITICALEEEE FOR 639-1427 (K95 32G) EEEE_K95_32GDH3D1
LBL4631- MATRIX LABEL825-7640 1 CRITICAL
LBL3MATRIX LABEL825-7640 1 CRITICAL
CAN2CAN,CPU,MLB,K93/K94 NOSTUFF1806-1399
FENCE,NAND,MLB,K93/K941806-1400 FENCE3
FENCE,CPU,MLB,K93/K941806-1398 FENCE2
COMMON,ALTERNATEBASIC
820-3069 PCBF,CHOPIN_AUDIO,MLB,K941 PCB1
051-8962 SCH,CHOPIN_AUDIO,MLB,K941 SCH1
CAN,GRAPE,MLB,K93/K94806-1397 NOSTUFF1 CAN1
806-1401 1 CAN,NAND,MLB,K93/K94 NOSTUFFCAN3
5 OF 106
A.0.0
051-8962
3 OF 42
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
JTAG_TRST*
PLL2_AVDD11
PLL3_AVDD11
PLL1_AVDD11
USB_VBUS
USB_ANALOGTEST
HSIC2_DATA
JTAG_TRTCK
JTAG_TMS
USB11_DM
USB11_DP
XO0
HSIC1_STB
HSIC1_DATA
MIPI1D_VDD11_PLL
MIPI_VSS_1
JTAG_TCK
JTAG_SEL
HSIC2_STB
HSIC_DVDD
PLL4_AVDD11
PLL_USB_AVDD11
MIPI0D_VDD11_PLL
USB_DVDD
USB_VDD330
HSIC_VDD122
HSIC_VDD121
PLL0_AVDD11
TESTMODE
FUSE1_FSRC
TST_STPCLK
FAST_SCAN_CLK
TST_CLKOUT
RESET*
HOLD_RESET
WDOG
XI0
USB_VSSAC
USB_VSSA0
MIPI_VSS_0
PLL_USB_AVSS11
USB_DVSS
PLL4_AVSS11
PLL3_AVSS11
PLL2_AVSS11
PLL1_AVSS11
PLL0_AVSS11
HSIC_VSS122
HSIC_VSS121
HSIC_DVSS
JTAG_TDI
USB_DM
USB_DP
USB_ID
USB_BRICKID
USB_REXT
DDR1_CKEIN
DDR0_CKEIN
CFSB
JTAG_TDO
SYM 1 OF 12
VSS VSS
SYM 11 OF 12
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
1 - DAISY-CHAIN (FOR USE WITH 5-WIRE JTAG)
PER RADAR #675523717MA
NEED TO ADD BOM TABLE FOR ALT P/N OF HYNIX (?)
28MA
5MA7MA
6.5MA
2.5MA
17MA
H4P UM V0.83PAGE 4608NOTE:
(FOR IC TESTER)
(0=NORMAL)
JTAGSEL
0 - PARALLEL
2.5MA EACH
0.01UF10%
01005
6.3VX5R
10%0.01UF
01005
6.3VX5R
01005
1/32WMF
10K1%
5%16VCERM
22PF
01005
1% MF1/32W
1.00M01005
01005
100K
1/32WMF
1%
1/32W
01005MF
1%42.2K
MF1/32W5%
100K
01005
MF
1%1/20W
44.2
201
10%
01005
6.3VX5R
0.01UF
DEVELOPMENT_JTAG_TAP
100K
10%0.01UF
01005
6.3VX5R
0.01UF
01005
10%6.3VX5R
10%
402CERM
1UF6.3V
0.01UF
01005
10%6.3VX5R
10%0.01UF
01005
6.3VX5R
0.01UF10%
01005
6.3VX5R
100K
100K
100K
GDZ-0201GDZT2R5.1B
35
35
28 31 35
4 10 39
10 39
4 28 39
4 28 39
10 39
28 39
28 39
1/32W
01005MF
1%82.5K
11 39
11 39
BGAH4P-512MB
01005
10%0.01UF6.3VX5R
10%
01005
0.01UF6.3VX5R
0201-1
80-OHM-0.2A-0.4-OHM
CERM
10%1UF
402
6.3V
0.1UF10%6.3VX5R201
24.000MHZ-16PF-60PPMSM-2
CRITICAL
5%16VCERM
22PF
01005
01005
1/32W5%
22
MF
H4P-512MBBGA
SC58940X01-A030
01005MF
0%
0.00
1/32W
01005MF
0%
0.00
1/32W
01005MF
0%
0.00
1/32W
01005MF
0%
0.00
1/32W
01005
0%
0.00
1/32WMF
MF
0%
0.00
1/32W
01005
56PF
NP0-C0G
5%
01005
6.3V
5%
NP0-C0G01005
56PF6.3V
6.3V
0.22UF20%
X5R0201
NOSTUFF
SHORT-01005
SHORT-01005NOSTUFF
10%1000PF
X7R16V
201
SYNC_MASTER=JAMES
AP: MAINSYNC_DATE=N/A
AP_DDR1_CKEINAP_DDR1_CKEIN_1V2
AP_CFSB
NC_HSIC2_AP_DATA
AP_JTAG_SEL
JTAG_AP_TDI
JTAG_AP_TCK
JTAG_AP_TDI
JTAG_AP_TMS
JTAG_AP_TCK
USB_REXT
NC_USB_ID
USB_D_P
USB_D_N
XTAL_24M_O
USB_FS_D_P
USB_FS_D_N
24M_O
JTAG_AP_TMS
=PP1V8_H4
PPVBUS_USB
=PP1V8_H4
AP_TESTMODE
AP_TST_STPCLK
AP_FAST_SCAN_CLK
AP_HOLD_RESET
TP_AP_TST_CLKOUT
USB_BRICKID
XTAL_24M_I
USB_AP_VBUS
NC_USB_ANALOGTEST
RST_AP_1V8_L
=PP3V3_USB_H4
RST_AP_L
=PP1V1_USB_H4
RST_PMU_IN
=PP1V1_MIPI_PLL_H4
=PP1V1_USB_H4
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.1VMIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
PP1V1_PLL_USB_F
=PP3V3_USB_H4
=PP1V1_PLL_H4
JTAG_AP_TDO
JTAG_AP_TRST_L
NC_JTAG_AP_RTCK
NC_HSIC2_AP_STB
TP_HSIC1_AP_STB
TP_HSIC1_AP_DATA
=PP1V2_HSIC_H4
VOLTAGE=1.1V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
PP1V1_MIPID_PLL_F
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
VOLTAGE=1.1V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PP1V1_PLL4_F
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MMVOLTAGE=1.1V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PP1V1_PLL3_F
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MMVOLTAGE=1.1V
NET_SPACING_TYPE=PWR
PP1V1_PLL2_F
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
VOLTAGE=1.1VMIN_LINE_WIDTH=0.2MM
PP1V1_PLL1_F
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MMVOLTAGE=1.1V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PP1V1_PLL0_F
=PP1V1_USB_H4
C06271
2
C06301
2
R06171
2
C06131
2
R0655
12
R0632
1 2
R06881
2
R06511 2
R06421
2
C06081
2
R06621 2
C06421
2
C06411
2
C06401
2
C06441
2
C06461
2
C06481
2
R06471 2
R06461 2
R06451 2
DZ0600
1
2
R06891
2
U0652
W30
G11
R7
T32
M28
P31
A26
A27
C26
D26
F24
E24
D25
D24
C25
C24
N31
N30
M32
M31
N32
N29
M30
AR10
AT14
AN10
AN11
C19
D19
C20
D20
C21
D21
C18
D18
C17
D17
C22
D22
P32
P29
P34
P33
A23
A22
G26
G27
A28
A29
C28
D28
F28
A21
F27
H27
H28
H26
J26
P30
A18
A19
C06511
2
C06521
2
FL0610
1 2
C06551
2
C06541
2
Y0602
2 4
1 3
C06071
2
R06401 2
U0652AU14
AU15
AU16
AU17
AV1
AV2
AV3
AV4
AV5
AV6
AV7
AV8
AV9
AV10
AV11
AV12
AV13
AV14
AV15
AV16
AV17
AV29
AV33
AV34
AW1
AW2
AW4
AW23
AW33
AW34
AY1
AY2
AY3
AY4
AY20
AY22
AY24
AY30
AY31
AY32
AY33
AY34
B1
B2
B7
B9
B10
B12
B13
B15
B17
B18
B20
B22
B23
B28
B29
B30
B32
B33
B34
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C23
C27
C29
C32
C33
D1
D3
D5
D7
D9
D11
D13
D15
D16
D23
D27
D32
E1
E2
E3
E4
E6
E8
E10
E12
E14
E16
E17
E18
E19
E20
E21
E22
E23
E25
E26
E27
E28
E30
E31
E32
E34
F1
F2
F3
F5
F19
F20
F21
F22
F23
F25
F26
F29
F30
F31
F32
G1
G3
G4
G7
G8
G9
G10
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G25
G28
G29
G30
H1
H2
H3
H5
H7
H8
H10
H12
H14
H16
H18
H20
H22
H24
H25
H29
H30
J1
J2
J3
J4
J7
J9
J11
J13
J15
J17
J19
R06241 2
R06231 2
R06221 2
R06211 2
R06201 2
R06251 2
C06601
2
C06611
2
C06431
2
XW0605
1 2
XW06041 2
C06181
2
6 OF 106
A.0.0
051-8962
4 OF 42
10
4 10 39
4 28 39
39
39
4 28 39
4 5 7 10 13 32
34
4 5 7 10 13 32
10
10
10
10
39
4 32
4 32
32
4 32
4 32
32
32
4 32
OUT
BI
BI
OUT
BI
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
EHCI_PORT_PWR2
EHCI_PORT_PWR1
EHCI_PORT_PWR0
TMR32_PWM2
TMR32_PWM0
TMR32_PWM1
GPIO1
GPIO2
GPIO5
GPIO4
GPIO18
GPIO0
UART3_RTSN
UART3_CTSN
UART2_TXD
UART2_RXD
UART2_RTSN
GPIO3
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO11
GPIO14
GPIO13
GPIO15
GPIO17
GPIO16
GPIO19
GPIO22
GPIO23
GPIO25
GPIO24
GPIO27
GPIO26
GPIO28
GPIO30
GPIO29
GPIO32
GPIO31
GPIO33
GPIO35
GPIO34
GPIO37
GPIO36
GPIO38
GPIO_3V0
GPIO39
GPIO_3V1
UART6_CTSN
UART6_RTSN
UART6_RXD
UART6_TXD
UART5_RTXD
UART0_RXD
UART0_TXD
UART1_RTSN
UART1_CTSN
UART1_RXD
UART2_CTSN
UART1_TXD
UART3_RXD
UART3_TXD
UART4_RTSN
UART4_CTSN
UART4_RXD
UART4_TXD
VSS
GPIO20
GPIO21
SYM 2 OF 12
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
SPI3_SSIN
SPI3_SCLK
SPI3_MISO
SPI3_MOSI
DWI_DO
DWI_DI
SWI_DATA
DWI_CLK
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
I2S1_LRCK
I2S0_DOUT
SDIO0_CLK
SDIO0_DATA0
SDIO0_CMD
SDIO0_DATA1
SDIO0_DATA3
SDIO0_DATA2
I2S1_DIN
I2S1_DOUT
I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DOUT
I2S2_DIN
I2S3_BCLK
I2S3_MCK
I2S3_DOUT
I2S3_DIN
SPI0_MISO
SPDIF
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
SPI2_MOSI
SPI2_MISO
SPI2_SCLK
SPI2_SSIN
VSS
I2S1_BCLK
I2S1_MCK
I2S0_DIN
I2S0_LRCK
I2S0_BCLK
I2S0_MCK
I2S3_LRCK
SYM 3 OF 12
OUT
OUT
BI
BI
BI
BI
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
GROUP 6
TO GPS UART
CODEC ASP
TO DOCK MUX
TO BB USART
TO BB UMTS
TO BT UART
1.8V/3.0V
GROUP 0
3.0V
GROUP 1
1.8V
TO WIFI
GROUP 7
1.8V/3.0V
GROUP 5
CODEC VSP & BT
CODEC XSP
TO GRAPE
TO BB
BB (NOT USED)
FOR PMUDUAL-WIRE INTF
(SCREEN ROTATION LOCK)
01005MF
4.7K5%1/32W
MF
4.7K5%1/32W
01005 01005MF
4.7K5%1/32W
01005MF
5%1/32W
4.7K1/32W5%
MF01005
1.8K5%1/32WMF01005
1.8K
5 10 19 35 39
5 10 19 35 39
5 25 39
5 25 39
5 25 26 39
5 25 26 39
17 40
17 40
17 40
17 40
31 40
31 40
31 40
31 40
BGAH4P-512MB
SC58940X01-A030
10
10
10
201
220K
5%1/20WMF
201
220K
5%1/20WMF
MF
5%
201
220K
1/20W
201
5%1/20W
100K
MF201
5%1/20W
100K
MF201
5%1/20W
100K
MFMF1/32W5%100K
01005201
100K5%1/20WMF
5 29 35
5 25 35
5 31
31
31
35
10
18
5 35
5
10
5 37
10
31
10
25
25
26
25
20
31
10
10
10
10
10
10
10
10
10
10
10
10
SC58940X01-A030
H4P-512MBBGA
30 40
30 40
30 40
30 40
30 40
30 40
19 39
19 39
19 39
19 39
19 30 39
19 30 39
19 30 39
19 30 39
19 39
19 39
19 39
19 39
11
35 39
35 39
35 39
30
19
31
33 35
10
10
10
10
5 25
31
5 25 35
25
25
25
31
MF1/32W
01005
1%33.2
19 39
10
10
10
31
31
SYNC_DATE=N/ASYNC_MASTER=JAMES
AP: I/Os
SDIO_WL_CLK
I2C2_SCL_3V0
I2C2_SDA_3V0
NC_I2S_AP_1_MCK
TP_IRQ_COMPASS_INT_L
IRQ_ACCEL_INT1_L
IRQ_ALS_INT_L
AUD_SPKRAMP_MUTE_L
PORT_DOCK_VIDEO_AMP_EN
NC_GPIO_218
UART_1_TXD
IRQ_ACCEL_INT2_L
NC_SPI_FLASH_CS_L
NC_AP_GPIO185
NC_AP_GPIO186
NC_SWI_AP
NC_SPI_AP_3_MISO
NC_SPI_AP_3_MOSI
NC_SPI_AP_3_CS_L
NC_SPI_AP_3_SCLK
NC_AP_GPIO216
NC_I2S_AP_3_MCK
NC_I2S_AP_2_MCK
NC_I2S_AP_1_DOUT
I2S_AP_0_MCK
NC_I2S_AP_1_BCLK
NC_I2S_AP_1_DIN
NC_I2S_AP_1_LRCK
PM_KEEPACT
IRQ_GYRO_INT2
FORCE_DFU
DFU_STATUS
NC_AP_GPIO187
=PP1V8_H4
I2C1_SCL_1V8
I2C0_SCL_1V8
I2C0_SDA_1V8
ONOFF_L
HOME_L
SRL_L
=PP1V8_S2R_MISC
=PP1V8_ALWAYS
=PP1V8_S2R_MISC
PM_RADIO_ON
NC_AP_GPIO2
NC_AP_GPIO3
NC_AP_GPIO4
NC_AP_GPIO8
NC_BOARD_ID_3
NC_AP_GPIO10
NC_AP_GPIO14
NC_AP_GPIO5
NC_AP_GPIO6
NC_AP_GPIO22
NC_AP_GPIO20
BOOT_CONFIG_2
TP_PROX_GPIO
IRQ_GPS_INT_L
GSM_TXBURST_IND
BOARD_ID_0_SPI_FLASH_CLK
BOARD_ID_1_SPI_FLASH_DIN
BOARD_ID_2_SPI_FLASH_DOUT
I2S_AP_0_MCK_R
IPC_GPIO
IRQ_PROX_INT_L
AUD_VOL_DOWN_L
AUD_VOL_UP_L
SRL_L
RST_BB_L
IRQ_GYRO_INT2
UART_4_TXD
UART_4_RXD
UART_4_RTS_L
UART_4_CTS_L
BATTERY_SWI
PM_GPS_STANDBY_L
IRQ_CODEC_L
PM_BT_WAKE
DWI_AP_DI
DWI_AP_DO
DWI_AP_CLK
I2S_AP_3_DIN
I2S_AP_3_DOUT
I2S_AP_3_LRCK
I2S_AP_3_BCLK
I2S_AP_2_DIN
I2S_AP_2_BCLK
I2S_AP_2_LRCK
I2S_AP_2_DOUT
I2S_AP_0_DIN
I2S_AP_0_DOUT
I2S_AP_0_LRCK
I2S_AP_0_BCLK
SDIO_WL_DATA<3>
SDIO_WL_DATA<2>
SDIO_WL_DATA<0>
SDIO_WL_CMD
UART_3_TXD
UART_3_RXD
UART_3_RTS_L
UART_3_CTS_L
UART_2_TXD
UART_2_RXD
UART_1_RTS_L
UART_1_CTS_L
UART_1_RXD
UART_0_TXD
UART_0_RXD
GPS_SYNC
IRQ_GYRO_INT1
BOOT_CONFIG_3
RST_GPS_L
FORCE_DFU
BOOT_CONFIG_1
DFU_STATUS
PM_KEEPACT
IRQ_GRAPE_HOST_INT_L
BOOT_CONFIG_0
IRQ_PMU_L
RST_DET_L
SPI_IPC_SRDY
PM_RADIO_ON
ONOFF_L
HOME_L
AP_GPIO42_BRD_REV2
AP_GPIO40_BRD_REV0
AP_GPIO41_BRD_REV1
SPI_IPC_SCLK
SPI_IPC_MRDY
SPI_IPC_MISO
SPI_GRAPE_CS_L
SPI_GRAPE_MISO
SPI_GRAPE_MOSI
SPI_GRAPE_SCLK
I2C2_SDA_3V0
I2C2_SCL_3V0
I2C1_SDA_1V8
I2C1_SCL_1V8
I2C0_SCL_1V8
I2C0_SDA_1V8
I2C1_SDA_1V8
=PP3V0_OPTICAL
SPI_IPC_MOSI
SDIO_WL_DATA<1>
R07001
2
R07011
2
R07021
2
R07031
2
R07051
2
R07041
2
U0652
AL7
AL6
AM6
AA3
AA4
AD7
AC3
AD6
AD5
AD4
AD3
AE7
AD1
AE1
AE4
AA5
AE3
AE2
AF4
AF3
AF7
AF2
AG7
AG6
AG5
AG4
AA6
AG3
AG1
AH1
AH2
AH7
AH3
AH4
AJ5
AJ4
AJ3
AA7
AB3
AB4
AB5
AC7
AC4
U30
V30
AC30
AA27
AB30
R31
R30
AN4
AM5
AM3
AM1
AP4
AM2
AM4
AN5
AP1
AR2
AR4
AP2
AU1
AT3
AT4
AT1
AR3
AU2
AN3
AU3
AP3
A1
A2
A3
A6
A7
A8
A9
A10
A11
A12
R07711 2
R07701 2
R07651 2
R07391
2
R07381
2
R07371
2
R07361
2
R07351
2
U0652
AB34
AA31
Y27
AD26
AD29
AD31
AE30
AF30
AF29
AB33
AC34
AA32
Y31
Y32
AD32
W34
AC32
Y34
AC33
V32
U32
V31
U34
V33
W32
T30
W29
U31
T31
AB27
AC26
AB31
AD30
AB26
AB32
W31
AE29
AG34
AE31
AE32
AH32
AF28
AG32
AF31
AF34
AG33
AE27
AE28
AH31
AH29
AH30
AG30
AA30
A13
A14
A15
A16
A17
A20
A30
A33
A34
AA9
R0720
1 2
7 OF 106
A.0.0
051-8962
5 OF 42
5 25 26 39
5 25 26 39
5 35
5 25
5 37
5
4 7 10 13 32
5 25 39
5 10 19 35 39
5 10 19 35 39
5 25 35
5 29 35
5 25 35
5 28 32
32
5 28 32
5 31
5 25 39
26 27 32
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
FMI0_IO6
FMI0_IO5
FMI2_CEN2
FMI2_CEN3
FMI3_IO3
FMI3_IO1
FMI3_IO0
FMI3_CEN7
FMI3_CEN6
FMI3_CEN5
FMI3_CEN2
FMI3_CEN1
FMI3_CEN0
FMI2_DQS
FMI2_REN
FMI2_IO0
FMI2_IO1
FMI0_IO0
FMI0_IO1
FMI0_CEN5
FMI0_CEN6
FMI0_CEN7
FMI0_CEN4
FMI0_CEN2
FMI0_CEN3
VSS
FMI1_DQS
FMI1_WEN
FMI1_REN
FMI1_CLE
FMI1_ALE
FMI1_IO7
FMI1_IO6
FMI1_IO5
FMI1_IO3
FMI1_IO4
FMI1_IO2
FMI1_IO1
FMI1_IO0
FMI1_CEN7
FMI1_CEN6
FMI1_CEN4
FMI1_CEN3
FMI1_CEN5
FMI1_CEN1
FMI1_CEN2
FMI1_CEN0
FMI0_REN
FMI0_ALE
FMI0_IO7
FMI0_IO4
FMI0_IO3
FMI0_IO2
FMI0_CEN0
FMI0_CEN1
FMI3_DQS
FMI3_WEN
FMI3_REN
FMI3_CLE
FMI3_ALE
FMI3_IO7
FMI3_IO6
FMI3_IO5
FMI3_IO2
FMI3_IO4
FMI3_CEN4
FMI3_CEN3
FMI2_CLE
FMI2_WEN
FMI2_ALE
FMI2_IO7
FMI2_IO4
FMI2_IO5
FMI2_IO6
FMI2_IO2
FMI2_IO3
FMI2_CEN7
FMI2_CEN6
FMI2_CEN5
FMI2_CEN4
FMI2_CEN1
FMI2_CEN0
FMI0_CLE
FMI0_WEN
FMI0_DQS
SYM 4 OF 12
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
VSS VSS
SYM 12 OF 12
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
GROUP 2GROUP 2
GROUP 2GROUP 2
GROUP 4
GROUP 5
GROUP 4GROUP 2
3.3V
GROUP 2
GROUP 3
3.3V
GROUP 3GROUP 5
MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
H4P-512MB BGA
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
12 39
SC58940X01-A030
BGAH4P-512MB
5%
MF
100K
01005
1/32W
14
36
MF1/32W5%100K
01005
1/32W
01005
100K5%
MF01005
100K5%1/32WMF
01005
100K5%1/32WMF
01005
100K5%1/32WMF
01005
100K5%1/32WMF
01005
100K5%1/32WMF
01005
100K5%1/32WMF
17
17
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
01005
MF1/32W5%100K
01005MF1/32W5%100K
01005MF1/32W5%100K
0100501005
1/32WMF
5%100K
SYNC_MASTER=JAMES SYNC_DATE=N/A
AP: NAND
F1ALEF1CLE
F0ALEF0CLE
=PPIO_NAND_H4
F1RE_LF1WE_LF0RE_LF0WE_L
F1CE3_LF0CE0_L
F1RE_LF1WE_L
F0RE_LF0WE_L
F1CLEF1ALE
F0CLEF0ALE
F0AD<6>F0AD<5>
NC_F2CE2_LNC_F2CE3_L
NC_F3AD<3>
NC_F3AD<1>NC_F3AD<0>
TP_CD_SD_CTRL_L
PM_MLC_PWR_EN
TP_RST_SD_CTRL_L
NC_F3CE2_LNC_F3CE1_LNC_F3CE0_L
NC_AP_GPIO_110
NC_F2RE_L
NC_F2AD<0>NC_F2AD<1>
F0AD<0>F0AD<1>
F0CE5_LF0CE6_LF0CE7_L
F0CE4_L
F0CE2_LF0CE3_L
NC_AP_GPIO93
F1AD<7>F1AD<6>F1AD<5>
F1AD<3>F1AD<4>
F1AD<2>F1AD<1>F1AD<0>
F1CE7_LF1CE6_L
F1CE4_LF1CE3_L
F1CE5_L
F1CE1_LF1CE2_L
F1CE0_L
F0AD<7>
F0AD<4>F0AD<3>F0AD<2>
F0CE0_LF0CE1_L
NC_AP_GPIO_135
NC_F3WE_LNC_F3RE_L
NC_F3CLENC_F3ALE
NC_F3AD<7>NC_F3AD<6>NC_F3AD<5>
NC_F3AD<2>
NC_F3AD<4>
NC_AP_GPIO_147
NC_F3CE3_L
NC_F2CLENC_F2WE_L
NC_F2ALE
NC_F2AD<7>
NC_F2AD<4>NC_F2AD<5>NC_F2AD<6>
NC_F2AD<2>NC_F2AD<3>
GRAPE_FW_DNLD_EN_L
RST_GRAPE_L
TP_GPIO_SD_CTRL
RST_MLC_L
NC_F2CE1_LNC_F2CE0_L
NC_AP_GPIO76
F0CE7_L
F1CE6_L
F0CE5_LF0CE6_L
F1CE4_LF1CE5_L
F1CE7_LF0CE4_L
=PPIO_NAND_H4
=PPIO_NAND_H4
F0CE2_LF0CE3_L
F0CE1_L
F1CE2_LF1CE1_LF1CE0_L
R08251
2
R08361
2
R08281
2
R08271
2
R08341
2
R08331
2
R08321
2
R08311
2
U0652
AT20
AV20
AW21
AU19
AU20
AV31
AT31
AV32
AU30
AU21
AT21
AV18
AU18
AT22
AW19
AV21
AU22
AY21
AR20
AV22
AT19
AP23
AN22
AY19
AP20
AT18
AN30
AU34
AU33
AP30
AV19
AY25
AV25
AU23
AW25
AU25
AU24
AV24
AT23
AV23
AN21
AN23
AW27
AY26
AU26
AW26
AV26
AP34
AL32
AK31
AM32
AU27
AV30
AY29
AR30
AU29
AV28
AY28
AW30
AW28
AU28
AY27
AV27
AT32
AT30
AP31
AU31
AU32
AN34
AM33
AM34
AN33
AT34
AR33
AP33
AL31
AR34
AN32
AM31
AN31
AR32
AP32
AR31
AT33
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA29
AB1
AB6
AB8
U0652J21
J23
J25
J27
J28
J29
J30
K1
K3
K5
K7
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K30
K31
K32
L1
L2
L3
L4
L7
L9
L11
L13
L15
L17
L19
L21
L23
L25
L28
L29
L30
L31
L32
L33
M1
M3
M5
M7
M8
M10
M12
M14
M16
M18
M20
M22
M24
M26
M29
M33
N1
N2
N3
N4
N7
N9
N11
N13
N15
N17
N19
N21
N23
N25
N27
N28
P1
P2
P3
P5
P7
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
R1
R3
R4
R9
R11
R13
R15
R17
R19
R21
R23
R25
R27
R29
R34
T1
T2
T3
T5
T7
T8
T10
T12
T14
T16
T18
T20
T22
T24
T26
T29
T33
U1
U3
U4
U7
U9
U11
U13
U15
U17
U19
U21
U23
U25
U27
U28
V1
V2
V3
V5
V7
V8
V10
V12
V14
V16
V18
V20
V22
V24
V26
V28
V34
W1
W2
W3
W4
W7
W9
W11
W13
W15
W17
W19
W21
W23
W25
W27
Y3
Y5
Y7
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
Y29
Y30
R08781
2
R08671
2
R08661
2
R08651
2
R08641
2
R08631
2
R08621
2
R08611
2
R08601
2
R08001
2
R08011
2
R08021
2
R08031
2
R08131
2
R08121
2
R08111
2
R08101
2
8 OF 106
A.0.0
051-8962
6 OF 42
6 12 39
6 12 39
6 12 39
6 12 39
6 9 10
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 9 10
6 9 10
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
IN
BI
OUT
OUT
OUT
OUT
IN
IN
MIPI_VSSMIPI0D_DNCLK
MIPI0D_DPCLK
MIPI0D_DNDATA3
MIPI0D_DPDATA3
MIPI0D_DNDATA2
MIPI0D_DPDATA2
MIPI0D_DNDATA1
MIPI0D_DPDATA1
MIPI0D_DNDATA0
MIPI0D_DPDATA0
MIPI0C_DNCLK
MIPI0C_DNDATA3
MIPI0C_DPCLK
MIPI0C_DPDATA3
MIPI0C_DNDATA2
MIPI0C_DPDATA0
MIPI_VSYNC
MIPI1C_DNCLK
MIPI1C_DPCLK
MIPI1C_DNDATA1
MIPI1C_DPDATA1
MIPI1C_DNDATA0
SENSOR1_RST
MIPI1C_DPDATA0
SENSOR0_RST
SENSOR1_CLK
SENSOR0_CLK
ISP1_SDA
ISP1_SCL
ISP1_PRE_FLASH
ISP0_SDA
ISP1_FLASH
ISP0_SCL
ISP0_PRE_FLASH
ISP0_FLASH
MIPI0D_VREG_0P4V
MIPI1D_VREG_0P4V
MIPI0D_VDD18
MIPI1D_VDD18
MIPI_VDD11
MIPI0C_DNDATA0
MIPI0C_DPDATA1
MIPI0C_DNDATA1
MIPI0C_DPDATA2
SYM 5 OF 12
OUT
OUT
OUT
OUT
BI
OUT
BI
DAC_COMP
DP_PAD_TX0N
DP_PAD_TX0P
DP_PAD_TX1N
DP_PAD_TX1P
DP_PAD_AUXN
DP_PAD_AUXP
DP_HPD
DAC_OUT1
DAC_OUT2
DAC_OUT3
DP_PAD_DC_TP
DP_PAD_R_BIAS
DP_PAD_DVSS
DP_PAD_AVSSX
DP_PAD_AVSSP0
DP_PAD_AVSS1
DP_PAD_AVSS0
DP_PAD_AVSS_AUX
DAC_AVSS30A
DAC_AVSS30D
DAC_AVSS30A
DP_PAD_DVDD
DP_PAD_AVDDX
DP_PAD_AVDDP0
DP_PAD_AVDD0
DP_PAD_AVDD1
DP_PAD_AVDD_AUX
DAC_AVDD30D
DAC_AVDD30A
DAC_VREF
DAC_IREF
SYM 6 OF 12
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
<= 5MA
YIN
CVBSIN
CIN
5MA1.2MA6MA
63MA 63MA2MA
21MA
NOTE: 0.6V ANALOG REF
FRONT CAMERA
2MA ???
GROUP 5
28MA
REAR CAMERA
FRONT CAMERA
NOTE: PLACE R0955-57 NEAR U0652
REAR CAMERA
MIN_NECK_MIDTH SHOULD BE 0.2MM
10%
X5R
2.2NF10V
201
201X5R
10%6.3V
0.1UF
201X5R
10%6.3V
0.1UF
6.3VX5R
0.1UF10%
201
201
6.3VX5R
0.1UF10%
20%
402X5R6.3V
0.22UF
14 40
14 40
14 40
14 40
14 40
14 40
14 40
14 40
14 40
14 40
13 40
13
13 40
10 13 40
10 13 40
10 13 40
10 13 40
27 40
27 40
H4P-512MBBGA
SC58940X01-A030
27 39
25
22
26 39
26
7 25 39
7 26 39
7 26 39
10%
X5R
2.2NF10V
201
201
10%6.3VX5R
0.1UF
H4P-512MBBGA
SC58940X01-A030
1/32WMF
1%4.99K
01005
X5R01005
6.3V10%NOSTUFF
0.01UF
X5R
10%
201
6.3V
0.1UF
201MF
1/20W1%
6.34K
01005
6.3VX5R
10%0.01UF
0201
240-OHM-0.2A-0.8-OHM
402
10%1UF
CERM6.3V
01005
6.3V
0.01UF
X5R
10%
201MF1/20W
2001%
201MF
2001%1/20W
201MF1/20W
2001%
6.3V10%
CERM
1UF
402
402
6.3V20%0.22UF
X5R X5R
0.22UF20%6.3V
402NP0-C0G6.3V5%
01005
56PF MF1/20W
201
0
5%
NP0-C0G6.3V5%56PF
01005
7 25 39
26 40
26 40
22
5%1.00K
MF01005
1/32W5%1.00K
MF01005
1/32WMF01005
4.7K1/32W5%
MF01005
4.7K1/32W5%
27 40
27 40
26 40
26 40
11 40
11 40
11 40
AP: TV,DP,MIPISYNC_DATE=N/ASYNC_MASTER=JAMES
=PP1V8_H4
ISP_AP_1_SCL
VOLTAGE=0.4VMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
PP_AP_MIPI0D_0P4V
ISP_AP_1_SDA
NC_AP_GPIO153
NC_AP_GPIO152
PM_REAR_CAM_SHUTDOWN
CLK_CAM_RF_R
CLK_CAM_FF_R
MIN_LINE_WIDTH=0.4MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
VOLTAGE=1.8V
PP_AP_DP_AVDD_AUX
MIN_NECK_WIDTH=0.1MM=PP3V0_IO_H4
MIPID_AP_CLK_N
=PP3V0_VIDEO_H4
DAC_AP_OUT3
DAC_AP_OUT2
DP_AP_AUX_P
DP_AP_AUX_N
DAC_AP_OUT1
DP_AP_HPD
MIPI0C_AP_CLK_N
MIPID_AP_DATA_P<0>
MIPID_AP_DATA_P<1>
MIPID_AP_DATA_N<2>
MIPID_AP_DATA_N<1>
MIPI0C_AP_CLK_P
NC_MIPI0C_AP_DATA_P<3>
NC_MIPI0C_AP_DATA_N<1>
DP_AP_TX_P<1>
DP_AP_TX_N<1>
DP_AP_TX_P<0>
DP_AP_TX_N<0>
NC_MIPI0C_AP_DATA_P<1>
NC_MIPI0C_AP_DATA_N<2>
NC_MIPI0C_AP_DATA_P<2>
PP_DP_PAD_AVDD1
PP_DP_PAD_AVDD0
MIPI1C_AP_CLK_N
MIPI1C_AP_CLK_P
ISP_AP_0_SCL
ISP_AP_0_SDA
MIPID_AP_CLK_P
MIPID_AP_DATA_P<3>
MIPID_AP_DATA_N<3>
MIPID_AP_DATA_P<2>
MIPID_AP_DATA_N<0>
MIPI0C_AP_DATA_N<0>
MIPI0C_AP_DATA_P<0>
NC_MIPI0C_AP_DATA_N<3>
NC_AP_GPIO184
NC_MIPI1C_AP_DATA_N<1>
NC_MIPI1C_AP_DATA_P<1>
MIPI1C_AP_DATA_P<0>
ISP_AP_1_SDA
ISP_AP_1_SCL
NC_AP_GPIO154
ISP_AP_0_SDA
NC_AP_GPIO155
ISP_AP_0_SCL
=PP1V1_MIPI_H4
=PP1V8_MIPI_H4
PP_AP_MIPI1D_0P4V
VOLTAGE=0.4VMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
TP_DP_AP_ANALOG_TEST
DAC_AP_VREF
DAC_AP_IREF
=PP3V0_VIDEO_H4
DAC_AP_COMP
AP_DP_R_BIAS
=PP1V1_DPORT_H4
=PP1V8_DPORT_H4
DAC_AP_COMP_FTR
VOLTAGE=1.8V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
MIPI1C_AP_DATA_N<0>
PM_FRONT_CAM_SHUTDOWN
CLK_CAM_FF
CLK_CAM_RF
C09021
2
C09031
2
C09071
2
C09081
2
C09091
2
C09271
2
U0652
AG31
AG29
AE26
AC29
AJ32
AG28
AC31
AF27
AY12
AY10
AY11
AY13
AY14
AW12
AW10
AW11
AW13
AW14
AY7
AY5
AY6
AY8
AY9
AW7
AW5
AW6
AW8
AW9
AN13
AR11
AY16
AY15
AY17
AW16
AW15
AW17
AN15
AR15
AP10
AP11
AP13
AP14
AP15
AP16
AP17
AP18
AR12
AN12
AP12
AR14
AR16
AR17
AR18
AA26
AA33
Y26
AA34
Y33
R09001 2
C09201
2
C0956 1
2
U0652
L27
K29
M27
K27
K28
K34
J34N34
M34
L34J33
R32
F34
G34
E29
D30
H31
D31
G32
D29
C30
G31
C31
H32
H33
J31
J32
H34C34
D34
A31
A32R09201
2
C0950 1
2
C09551
2
R09501
2
C09521
2
FL0910
1 2
C09511
2
C09541
2
R09551
2
R09561
2
R09571
2
C09301
2
C09261
2
C09251
2
C09241
2
R09101 2
C09231
2
R09401 2
R09331
2
R09321
2
R09311
2
R09301
2
9 OF 106
A.0.0
051-8962
7 OF 42
4 5 10 13 32
7 26 39
7 26 39
10
9 32
7 32
10
10
7 25 39
7 25 39
32
32
7 32
32
32
VSS
VSSVDDIO18
VDDIOD
SYM 9 OF 12
VSS
VSS
VSS
VSS
VSS_39
VSS_38
VSS_37
VSS_35
VSS_34
VSS_32
VDDQ
VDD1
VDD2
DDR1_ZQ
DDR0_ZQ
DDR1_VREF_DQ
VDDCA
DDR1_VREF_CA
DDR0_VREF_CA
DDR0_VREF_DQ
DDR0_VDDQ_CKE
DDR1_VDDQ_CKE
VSS_36
VSS_33
SYM 7 OF 12
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(DDR IMPEDANCE CONTROL)
(VDDQ = VDDIOD: DON’T DOUBLE COUNT)
500MA
40MA
320MA
80MA
<1MA
<1MA
44MA
(VDDQ = VDDIOD: DON’T DOUBLE COUNT)
500MA
10UF
603
6.3VX5R
20%
0.01UF
01005
10%
NOSTUFF
6.3VX5R
1/32W1%
MF
1.00K
01005
1.00K1%
MF1/32W
01005
0.01UF
01005
10%
NOSTUFF
6.3VX5R
6.3VX5R
0201
0.22UF20%
1/32W
1.00K1%
MF01005
MF
1.00K1/32W1%
01005
1UF10%
402CERM6.3V6.3V
X5R0201
0.22UF20%
01005NP0-C0G
5%56PF
NOSTUFF
6.3V
SC58940X01-A030
BGAH4P-512MB
6.3VX5R
0201
0.22UF20%
1UF
CERM
10%
402
6.3V6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
SC58940X01-A030
H4P-512MBBGA
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
0610
4.3UF
X5R-CERM4V20%0.01UF
01005
10%
NOSTUFF
6.3VX5R
6.3VX5R
0201
0.22UF20%
01005
5%56PF
NP0-C0G
NOSTUFF
6.3V
240
1% 1/20W MF 201
240MF1/20W1% 201
01005
56PF5%
NP0-C0G
NOSTUFF
6.3V
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
402
10%1UF
CERM6.3V
6.3VX5R
0201
0.22UF20%
402CERM
10%1UF6.3VX5R-CERM
0610
4.3UF4V20%
6.3VX5R
0201
0.22UF20%
603
10UF6.3VX5R
20%
01005
10%0.01UF
6.3VX5R
10V
0.01UF10%
X5R201
01005
0.01UF10%
6.3VX5R
01005
5%56PF
NP0-C0G
NOSTUFF
6.3V6.3VX5R
0201
0.22UF20%
01005
10%0.01UF
6.3VX5R
10%
402CERM
1UF6.3V
6.3VX5R
0201
0.22UF20%
1UF
CERM
10%
402
6.3V
603
10UF6.3VX5R
20%
6.3VX5R
0201
0.22UF20%6.3V
X5R0201
0.22UF20%
0610
4.3UF4V
X5R-CERM
20%
603
10UF6.3VX5R
20%
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
01005
56PF5%
NP0-C0G
NOSTUFF
6.3V
1%2.21K
MF1/32W
01005
1/32W1%2.21K
MF01005
0.01UF
01005
10%
NOSTUFF
6.3VX5R
1/32W1%2.21K
MF01005
MF1/32W1%2.21K
01005
SYNC_MASTER=JAMES
AP: PWRSYNC_DATE=N/A
PPVREF_DDR0_CA
NET_SPACING_TYPE=VREF
PPVREF_DDR0_CA
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
NET_SPACING_TYPE=VREF
PPVREF_DDR0_DQ
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0.6V
MAX_NECK_LENGTH=3 MM
PPVREF_DDR0_DQ
NET_SPACING_TYPE=VREF
PPVREF_DDR1_CA
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0.6V
MAX_NECK_LENGTH=3 MM
PPVREF_DDR1_CA
NET_SPACING_TYPE=VREF
PPVREF_DDR1_DQ
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0.6V
MAX_NECK_LENGTH=3 MM
PPVREF_DDR1_DQ
=PP1V2_S2R_H4
=PP1V8_S2R_H4
=PP1V2_S2R_H4
DDR0_ZQ
DDR1_ZQ
=PP1V2_S2R_H4
=PP1V2_VDDQ_H4
=PP1V2_S2R_H4
=PP1V2_VDDQ_H4
=PP1V2_VDDQ_H4
=PP1V2_VDDIOD_H4
=PP1V8_VDDIO18_H4
C1035 1
2
C1034 1
2
C10401
2
C1039 1
2
C1038 1
2
C1037 1
2
C1032 1
2
C1036 1
2
C1043 1
2
C1042 1
2
C1041 1
2
U0652
AA28
AB7
AN7
AN8
H23
P28
R28
T28
W28
Y28
AB28
AC6
AC28
AD28
AE6
AF6
AH6
AN6
D4
D6
E13
E15
F4
F6
F7
F8
F9
F10
F11
F12
D8
F13
F14
F15
F16
F17
F18
G5
G6
H4
H6
D10
J5
J6
K4
K6
L5
L6
M4
M6
N5
N6
D12
P4
P6
R5
R6
T4
T6
U5
U6
V4
V6
D14
W5
W6
Y4
Y6
E5
E7
E9
E11
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM29
AM30
AN1
AN14
AN16
AN17
AN18
AN19
AN20
AN24
AN25
AN26
AN27
AN28
AN29
AP5
AP6
AP7
AP8
AP9
AP19
AP21
AP22
AR1
AR5
AR6
AR7
AR8
AR9
AR13
AR19
AR24
AR25
AR26
AR27
AR28
AR29
AT5
AT6
AT7
AT8
AT9
AT10
AT11
AT12
AT13
AT15
AT16
AT17
AT24
AT25
AT26
AT27
AT28
AT29
AU4
AU5
AU6
AU7
AU8
AU9
AU10
AU11
AU12
AU13
C1046 1
2
C1045 1
2
C1044 1
2
U0652
H11
AY23
A25
AY18
R8
AE34
AA1
AK34
A4
A5
AB2
AL2
AL33
AW18
AW32
B26
E33
U33
A24
AA2
F33
T34
Y1
AF33
AK33
AL1
AW22
AW31
B4
B5
B25
AD33
AH33
AW20
AW24
AW29
W33
AC2
AG2
B14
B16
B19
B21
B24
B27
B31
D2
D33
G2
AK2
G33
K2
K33
M2
N33
R2
R33
U2
Y2
AN2
AT2
AW3
B3
B6
B8
B11
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AB29
AC1
AC5
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AC25
AC27
AD2
AD8
AD10
AD12
AD14
AD16
AD18
AD20
AD22
AD24
AD27
AD34
AE5
AE9
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE33
AF1
AF5
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF32
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
C1001 1
2
C1000 1
2
C10021
2
C10071
2
C1013 1
2
R1001
1 2
R1000
1 2
C1006 1
2
C1005 1
2
C1011 1
2
C1004 1
2
C1010 1
2
C1009 1
2
C1008 1
2
C1018 1
2
C1012 1
2
C1017 1
2
C1022 1
2
C10211
2
C1026 1
2
C1016 1
2
C1015 1
2
C1014 1
2
C10201
2
C1019 1
2
C1024 1
2
C1023 1
2
C1031 1
2
C1030 1
2
C1029 1
2
C1027 1
2
R10051
2
R10061
2
C10521
2
R10511
2
R10521
2
C10561
2
R10561
2
R10551
2
C10541
2
R10531
2
R10541
2
10 OF 106
A.0.0
051-8962
8 OF 42
8 39
8 39
8 39
8 39
8 39
8 39
8 39
8 39
8 32
32
8 32
8 32
8 32
8 32
8 32
8 32
32
9 32
VDDVDD
SYM 10 OF 12
VDDIOD5
VDDIOD4
VDDIOD1
VSS
VSS
VSS
VSS
VDDIO30
VDDIOD0
VDDIOD2
VDDIOD3
VDDIOD6
VDDIOD7
VSSVDD_CPU
SYM 8 OF 12
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
3.3V
24MA
24MA
24MA
10MA
9MA
100MA
1900MA
2100MA
3.3V
1.8V
I2C2
SPI1
FMI[3]
FMI[0-2]
GPIO[30-39]1.8V
UART4
24MA
FMI[2-3]_CEN[4-7]SPI3,ISP FLASH
FMI[0-1]_CEN[4-7]3.3V
NOT USED
1MA
1MA3.0V
20%
X5R-CERM4V
4.3UF
0610
6.3V
01005
5%56PF
NP0-C0G
NOSTUFF
20%0.22UF
0201X5R
6.3V
20%4V
0610X5R-CERM
4.3UF
6.3V
01005
5%56PF
NP0-C0G
NOSTUFF
20%0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
20%4.3UF
X5R-CERM0610
4V
20%0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
SC58940X01-A030
H4P-512MBBGA
20%0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V
20%
X5R6.3V
603
10UF
20%4.3UF
0610X5R-CERM
4V
20%
X5R-CERM
4.3UF
0610
4V
6.3V
01005
56PF5%
NP0-C0G
20%0.22UF
0201X5R
6.3V
20%4V
4.3UF
X5R-CERM0610
20%
X5R-CERM0610
4V
4.3UF
6.3V
01005
5%56PF
NP0-C0G
20%0.22UF
0201X5R
6.3V
6.3V
01005
56PF5%
NP0-C0G
NOSTUFF
6.3V
01005
5%56PF
NP0-C0G
20%0.22UF
0201X5R
6.3V
20%
X5R6.3V
603
10UF
6.3V
01005NP0-C0G
5%56PF
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
20%
X5R6.3V
10UF
603
20%0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V
6.3V
402
10%
CERM
1UF6.3V
402CERM
10%1UF
SC58940X01-A030
H4P-512MBBGA
6.3V
01005
5%56PF
NP0-C0G
NOSTUFF
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V
6.3VNP0-C0G
5%56PF
01005
NOSTUFF
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V
20%0.22UF
0201X5R
6.3V20%
0.22UF
0201X5R
6.3V6.3V
402
10%
CERM
1UF6.3V
402CERM
10%1UF
6.3V
1UF10%
CERM402
6.3V
01005
5%56PF
NP0-C0G
NOSTUFF
SYNC_DATE=N/A
AP: PWRSYNC_MASTER=JAMES
=PP1V8_VDDIO18_H4
=PP3V0_IO_H4
=PPVDD_SOC_H4
=PPVDD_CPU_H4
=PPIO_NAND_H4
=PP3V0_IO_H4
C1103 1
2
C1102 1
2
C1101 1
2
C11071
2
C11111
2
C1106 1
2
C1105 1
2
C1110 1
2
C1100 1
2
C1104 1
2
C1109 1
2
C11081
2
C11161
2
C11201
2
C11151
2
C11141
2
C11191
2
U0652AA20
AA22
AB23
AM17
AM19
AM21
AM23
AM25
H9
H13
H15
H17
H19
AB25
H21
J8
J10
J12
J14
J16
J18
J20
J22
J24
AC8
K9
K11
K13
K15
K17
K19
K21
K23
K25
L8
AC10
L10
L12
L14
L16
L18
L20
L22
L24
L26
M9
AC12
M11
M13
M15
M17
M19
M21
M23
M25
N20
N22
AC14
N24
N26
P19
P21
P23
P25
P27
R20
R22
R24
AC16
R26
T19
T21
T23
T25
T27
U20
U22
U24
U26
AC18
V19
V21
V23
V25
V27
W20
W22
W24
W26
Y19
AC20
Y21
Y23
Y25
AC22
AA24
AC24
AD9
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD25
AB9
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE22
AE24
AF9
AB11
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF25
AG8
AG10
AB13
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AH9
AH11
AB15
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AJ8
AJ10
AJ12
AB17
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AK9
AK11
AK13
AB19
AK15
AK17
AK19
AK21
AK23
AK25
AL8
AL10
AL12
AL14
AB21
AL16
AL18
AL20
AL22
AL24
AL26
AM9
AM11
AM13
AM15
C11131
2
C11121
2
C11181
2
C11171
2
C1121 1
2
C1128 1
2
C11321
2
C1136 1
2
C1127 1
2
C1126 1
2
C11311
2
C1135 1
2
C1130 1
2
C11341
2
C1125 1
2
C1129 1
2
C11331
2
C11411
2
C1149 1
2
C1143 1
2
C1142 1
2
C1148 1
2
C1147 1
2
U0652AA8
AA10
N16
N18
P9
P11
P13
P15
P17
R10
R12
R14
AA12
R16
R18
T9
T11
T13
T15
T17
U8
U10
U12
AA14
U14
U16
U18
V9
V11
V13
V15
V17
W8
W10
AA16
W12
W14
W16
W18
Y9
Y11
Y13
Y15
Y17
AA18
N8
N10
N12
N14
G23
G24
U29
V29
AJ7
AK7
AN9
AP24
AP25
AP26
AP27
AP28
AR21
AR22
AR23
AP29
AL27
AM27
AJ27
AK27
AH27
AG27
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH34
AJ1
AJ2
AJ6
AJ9
AJ11
AJ13
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ28
AJ29
AJ30
AJ31
AJ33
AJ34
AK1
AK3
AK4
AK5
AK6
AK8
AK10
AK12
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK29
AK30
AK32
AL3
AL4
AL5
AL9
AL11
AL13
AL15
AL17
AL19
AL21
AL23
AL25
AL28
AL29
AL30
AL34
AM7
AM8
AM10
AM12
AM14
AH5
AH8
C1152 1
2
C1151 1
2
C11401
2
C11391
2
C11381
2
C1146 1
2
C1145 1
2
C1144 1
2
C11371
2
C1150 1
2
C1161 1
2
C1160 1
2
C1182 1
2
C1181 1
2
C1180 1
2
11 OF 106
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051-8962
9 OF 42
8 32
7 9 32
32
32
6 10
7 9 32
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
K95 AP
0011
0010
PROTO 1
PROTO 2
EVT010
11103. READ
2. DISABLE PU AND ENABLE PD
1010 FMI1 4CS W/TEST
1011 RESERVED
1110 FMI0/1 4/4 CS W/TEST
1111 RESERVED
1101 FMI0/1 4/4 CS
0011 SPI3 W/TEST
0001 SPI3
PLACEMENT NOTE: NEAR U0652
TO GPS UART
TO BT UART
TO BB UMTS
TO BB USART
TO DOCK MUX
1001 FMI1 4 CS
0110 FMI0 4CS W/TEST
0010 SPI0 W/TEST
BOOT_CONFIG[3:0]
1000 FMI1 2 CS0111 RESERVED
0101 FMI0 4CS0100 FMI0 2CS
0000 SPI0
BOARD REVISION
BOOT CONFIG ID
DEVELOPMENT_JTAG
JTAG_DAP
DEVELOPMENT_JTAG
2-WIRE DAP SCAN DUMP
DEVELOPMENT_JTAG_TAP
JTAG_DAP
JTAG
PRODUCTION
BOARD_ID[3]
BOARD_ID[2]
BOARD_ID[1]
BOARD_ID[0]
BOOT_CONFIG[2] (GPIO28)
BOOT_CONFIG[3] (GPIO29)
BRD_REV[2-0]
000
FOR REFERENCE
1. SET GPIO AS INPUT
S/W READ FLOW
FMI0/1 4/4 CS
FMI0/1 4/4 CS WITH TEST
BOOT_CONFIG[3-0]
1101
1100 FMI0/1 2/2 CS
BOOT_CONFIG[0] (GPIO18)
K93 DEV
K93 AP
BOARD_ID[3-0]
0100
0111
0110
0101
K94 AP
K94 DEV
K95 DEV
3. READ
2. DISABLE PU AND ENABLE PD
BOOT_CONFIG[1] (GPIO25)
CURRENT SETTING ->
001
1. SET GPIO AS INPUT
S/W READ FLOW
BOARD_ID_3
BOARD ID
011 EVT2
DVT100
3. READ
2. ENABLE PU AND DISABLE PD
1. SET GPIO AS INPUT
S/W READ FLOW
K94-K95
01005MF
10K5%1/32W
4 39
4 39
4 10 39
11 28 40
11 28 40
11 28 40
4
4 10 39
201
10K5%1/20WMF
201
10K5%1/20WMF
FMI_NOTEST
MF1/32W5%10K
01005
K9X_DEV
1/32W
10K5%
MF01005
K93-K94
1/32WMF
5%10K
01005
SHORT-01005NOSTUFF
SHORT-01005NOSTUFF
SHORT-01005NOSTUFF
11
11
31
31
31
31
31
31
30
30
30
30
31
31
31
31
7 13 40
7 13 40
7 13 40
7 13 40
201
25VCERM
100PF5%
NOSTUFFSIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTYNOSTUFF
5%1501/20WMF201
SIGNAL_MODEL=EMPTY
201
5%1501/20WMF
NOSTUFFSIGNAL_MODEL=EMPTY
201
NOSTUFF
MF1/20W
1505%
SIGNAL_MODEL=EMPTYNOSTUFF
201
5%
MF
1501/20W
SIGNAL_MODEL=EMPTY
25VCERM
100PF5%
NOSTUFF
201
5 19 35 39
5 19 35 39
01005
5%
100
1/32WMF
201
10K5%1/20WMF
FMI_TEST
100
JTAG_DAP
DEVELOPMENT_JTAG_TAP
1/32W
0.00
0%
MF01005
1/32W
0.00
0%
MF
DEVELOPMENT_JTAG_TAP
01005100
JTAG_DAP
1/32W
0.00
0%
MF
DEVELOPMENT_JTAG_TAP
01005
MF1/20W
10K5%
201MF
10K5%1/20W
201
5%10K
201
1/20WMF
NOSTUFF
SYNC_MASTER=JAMES SYNC_DATE=N/A
AP: MISC & ALIASES
BOARD_ID_2_SPI_FLASH_DOUT
BOARD_ID_0_SPI_FLASH_CLK
BOARD_ID_1_SPI_FLASH_DIN
=PP1V8_H4
DP_TERM_C1251
DP_AP_TX_N<1>
DP_AP_TX_P<1>
DP_TERM_C1250
DP_AP_TX_N<0>
DP_AP_TX_P<0>
PP_DP_PAD_AVDD0
PP_DP_PAD_AVDD1
PP_AP_DP_AVDD_AUX
MAKE_BASE=TRUE
AP_TST_STPCLK
AP_FAST_SCAN_CLK
AP_HOLD_RESET
=PP1V8_H4
VIDEO_EMI_C_Y
VIDEO_EMI_Y_PR
JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TRST_L
AP_JTAG_SEL
JTAG_AP_TRST_L
BOOT_CONFIG_0
BOOT_CONFIG_1
BOOT_CONFIG_3
BOOT_CONFIG_2
AP_GPIO42_BRD_REV2
AP_GPIO40_BRD_REV0
UART_1_RXD
UART_1_CTS_L
UART_1_RTS_L
UART_1_TXD
UART_2_RXD
UART_2_TXD
UART_3_CTS_L
UART_3_RTS_L
UART_3_RXD
UART_3_TXD
UART_4_CTS_L
UART_4_RTS_L
UART_4_RXD
UART_4_TXD
UART_AP_1_CTS_LMAKE_BASE=TRUE
UART_AP_1_RTS_LMAKE_BASE=TRUE
UART_AP_1_RXDMAKE_BASE=TRUE
UART_AP_1_TXDMAKE_BASE=TRUE
UART_AP_2_RXDMAKE_BASE=TRUE
UART_AP_2_TXDMAKE_BASE=TRUE
UART_AP_3_CTS_LMAKE_BASE=TRUE
UART_AP_3_RTS_LMAKE_BASE=TRUE
UART_AP_3_RXDMAKE_BASE=TRUE
UART_AP_3_TXDMAKE_BASE=TRUE
UART_AP_4_CTS_LMAKE_BASE=TRUE
UART_AP_4_RTS_LMAKE_BASE=TRUE
UART_AP_4_RXDMAKE_BASE=TRUE
UART_AP_4_TXDMAKE_BASE=TRUE
=PPIO_NAND_H4 =PP3V3_NAND_H4
UART_0_RXD
UART_0_TXDMAKE_BASE=TRUE
UART_AP_0_RXD
MAKE_BASE=TRUE
UART_AP_0_TXD
I2C0_SDA_1V8MAKE_BASE=TRUE
I2C0_SCL_1V8MAKE_BASE=TRUE
CHS_SDA
CHS_SCL
AP_TESTMODE
VIDEO_EMI_CVBS_PB
AP_GPIO41_BRD_REV1
R12051
2
R12021
2 R12101 2
R12121 2
R12131 2
R12111 2
R12141 2
R12071
2
R12081
2
R12091
2
R12011
2
R12001
2
R12031
2
R12061
2
R12041
2
XW0602 1 2
XW0601 1 2
XW0603 1 2
C12511
2
R12521
2
R12531
2
R12511
2
R12501
2
C12501
2
R12601 2
12 OF 106
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051-8962
10 OF 42
5
5
5
4 5 7 10 13 32
7
7
7
4
4
4
4 5 7 10 13 32
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6 9 32
5
5
23
23
4
5
RX_VHIGH/USB_2D+
TX_VHIGH/USB_2D-
CH.3_OUT
CH.2_OUT
CH.1_OUT
VID_EN
USB_1D-
USB_1D+
SEL
DGNDAGND
CH.1_IN
CH.2_IN
CH.3_IN
USB_D-
USB_D+
RX_VLOW
TX_VLOW
VA_1
VDH
VA_0
VDL
OUT
OUT
OUT
OUT
INOUT
IN
BI
BI
BI
BI
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
YIN
CIN
NOTE: PLACE R0960-62 NEAR U0900
H4P UART0 <-> DOCK SERIAL
LDO3 PROVIDES 50MA TO BOTH H4P AND U1300
IF THAT’S NOT ENOUGH, STUFF R1371 AND NOSTUFF R1370
CVBSIN
NOTE:
BB USB <-> DOCK SERIALDOCK_BB_EN = 1:
DOCK_BB_EN = 0:
NOTE:
BB USB <-> H4P FS USB
~15MA
THS7380IZSYRUCSP
10 28 40
10 28 40
75
1/20WMF
1%
201
JTAG_DAP
201MF
1%
75
JTAG_DAP
1/20W
201
1%
MF
75
JTAG_DAP
1/20W
10 28 40
0.00
MF01005
0%1/32W
NOSTUFF
0%
0.00
1/32WMF
01005
0.1UF10%
X5R201
6.3V
MF
100K5%
1/32W
01005
28 39
28 39 10
10
31 39
31 39
4 39
4 39
7 40
7 40
7 40
01005
6.3V5%
NP0-C0G
56PF6.3V
0.1UF10%
X5R201
100K5%
MF01005
1/32W
5
35
1/32W
01005
5%1.00M
MF
AP: VIDEO BUFFER,BB USB MUXESSYNC_DATE=N/ASYNC_MASTER=JAMES
PP3V0_U0900_FILTR
VOLTAGE=3.0V
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.2MM
BUF_C_Y
BUF_CVBS_PB
UART_AP_0_RXD
UART_AP_0_TXD
=PP3V0_VIDEO_BUFFER
DOCK_BB_EN
USB_FS_D_P
USB_BB_D_N USB_FS_D_N
USB_BB_D_P VIDEO_EMI_C_Y
VIDEO_EMI_Y_PR
VIDEO_EMI_CVBS_PB
=PP3V0_VIDEO_BUF
DAC_AP_OUT2
DAC_AP_OUT3
DAC_AP_OUT1
PORT_DOCK_VIDEO_AMP_EN
BUF_Y_PR
=PP3V2_S2R_USBMUX
USB_FS_P_ACC_RX
USB_FS_N_ACC_TX
U1300
B2
B3
A3 A2
A4 A1
B4 B1
D3
E3
E1
E4
C2
D1
D4
F1
F2
F4
F3
C1
C4
E2
D2
C3
R13601 2
R13611 2
R13621 2
R13711 2
R13701 2
C13701
2
R13721
2
C1301 1
2
C1300 1
2
R13201
2
R13151
2
13 OF 106
A.0.0
051-8962
11 OF 42
40
40
32
32
40
32
BI
IO0_1
CE6*
IO0_0
IO1_0
IO1_1
CE7*
CLE0
CLE1
ALE0
IO4_1
RE0*
RE1*
R/B0*
R/B1*
IO6_0
IO2_0
WE1*
CE2*
CE3*
CE4*
CE5*
CE0*
WE0*
R
CE1*
IO4_0
ALE1
INC
VSSQ
VCC
VCCQ
IO7_0
IO7_1
IO5_1
IO5_0
VSS
IO6_1
IO3_1
IO3_0
IO2_1
INC_VDDI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO0_1
CE6*
IO0_0
IO1_0
IO1_1
CE7*
CLE0
CLE1
ALE0
IO4_1
RE0*
RE1*
R/B0*
R/B1*
IO6_0
IO2_0
WE1*
CE2*
CE3*
CE4*
CE5*
CE0*
WE0*
R
CE1*
IO4_0
ALE1
INC
VSSQ
VCC
VCCQ
IO7_0
IO7_1
IO5_1
IO5_0
VSS
IO6_1
IO3_1
IO3_0
IO2_1
INC_VDDI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
64GB FLASH CONFIGURATIONS16GB FLASH CONFIGURATIONS
32GB FLASH CONFIGURATIONS
6 12 39
NAND-XXNM-64GX8
VLGA5-N90
LGA
OMIT
6 39
6 39
6 39
6 39
6 39
6 39
6 39
6 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
LGA
OMIT
NAND-XXNM-64GX8
VLGA5-N90
6 12 39
6 12 39
6 39
6 39
6 39
6 39
6 39
6 39
6 39
6 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
10%1UF
402X5R6.3V
6.3VX5R402
1UF10%
2.2UF20%6.3VCERM402-LF
0.1UF10%
X5R201
6.3V6.3V10%
201X5R
0.1UF
20%2.2UF6.3VCERM402-LF201
X5R
10%6.3V
0.1UF10%6.3VX5R201
0.1UF
100K
1/20WMF
1%
2011/20W
100K
201
1%
MF
25VCERM0201
82PF5%
0201
25V
82PF
CERM
5%
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
6 12 39
335S0722 SANDISK 32NM 32GB RAWU1400,U141064GB_PROD335S0702
HYNIX 26NM 32GB PPN335S0782 335S0702 U1400,U141064GB_PROD
335S0791 64GB_PROD SAMSUNG 27NM 32GB RAWU1400,U1410335S0702
64GB_PROD335S0665 335S0702 U1400,U1410 SAMSUNG 35NM 32GB RAW
U1400,U1410 64GB_PROD2335S0702 TOSHIBA 32NM 32GB RAW
32GB_PROD HYNIX 26NM 16GB PPNU1400,U1410335S0701335S0781
32GB_PROD335S0790 SAMSUNG 27NM 16GB RAW335S0701 U1400,U1410
335S0701335S0682 SAMSUNG 35NM 16GB RAWU1400,U141032GB_PROD
HYNIX 26NM 16GB PPN335S0781 335S0701 U140016GB_PROD
TOSHIBA 32NM 16GB RAW U1400,U1410 32GB_PROD335S0701 2
335S0790 SAMSUNG 27NM 16GB RAW335S0701 U140016GB_PROD
335S0682 335S0701 SAMSUNG 35NM 16GB RAWU140016GB_PROD
TOSHIBA 32NM 16GB RAW U14001335S0701 16GB_PROD
NANDSYNC_DATE=N/ASYNC_MASTER=JONATHAN
F0AD<3>
F0AD<5>
F0AD<0>
F1AD<0>
F1AD<5>
F1AD<2>
F1AD<4>
=PP3V3_NAND
F0RE_L
F1WE_L
NAND0_RB
F0AD<6>F1AD<6>
F1AD<7>
F0AD<7>
NAND0_RB
F0AD<2>
F0AD<6>
F1AD<4>
F1AD<1>
F0AD<1>
F1CLE
F1RE_L
F0ALE
NAND1_RB
F0RE_L
F1RE_L
F0CLE
F1CLE
F1CE7_L
F1CE3_L
F0CE2_L
F0WE_L
F0AD<3>
F0AD<4>
F0AD<5>
F1AD<5>
NAND0_VDDL
F0CE6_L
F1CE6_L
F0CE7_L
NAND1_VDDL
F1WE_L
F1AD<3>
F0CE0_L
F1AD<3>
F1AD<7>
F0AD<0>
F1AD<0>
F1AD<2>
NAND1_RB
F0AD<7>
F1AD<6>
=PP3V3_NAND
F0AD<2>
F1AD<1>
F0AD<1>
F1CE0_L
F0CE1_L
F1CE1_L
F0WE_L
F0ALE
F1ALE
F0CLE
F1CE5_L
F0CE5_L
F1CE4_L
F0CE4_L
F0AD<4>
F1ALE
F0CE3_L
F1CE2_L
C14021
2
C14011
2
C14001
2C14121
2
C14111
2
C14101
2
R14001 2 R1401
1 2
C14131
2
C14031
2
U1400
C1
D2
A5
C5
A1
OA0
G5
F2
OB0
OE0
A3
C3
A7
OA8
OB8
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
OC0
OC8
OD0
OD8
OF0
OF8
E5
E7
C7
D6
B6
M6
N1
N7
B2
F6
L3
M2
OE8
E3
E1
U1410
C1
D2
A5
C5
A1
OA0
G5
F2
OB0
OE0
A3
C3
A7
OA8
OB8
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
OC0
OC8
OD0
OD8
OF0
OF8
E5
E7
C7
D6
B6
M6
N1
N7
B2
F6
L3
M2
OE8
E3
E1
C14141
2
C14041
2
14 OF 106
A.0.0
051-8962
12 OF 42
12 32
12 12
12 12
12 32
GND
VCC
NCNC
YA
OUT
OUT
OUT
OUT
BI
BI
OUTIN
IN
IN
IN
IN
BI
BI
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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A
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DISPLAYPORT AC COUPLING
DISPLAYPORT HOT PLUG DETECT
1/32WMF
100K1%
01005
MF1/32W
100K1%
01005
1/32W
220K
MF
5%
01005CRITICAL
SOT88674LVC1G07
6.3VX5R201
0.1UF10%
NOSTUFF
5%
MF
10K1/32W
01005
MF1/32W
0.000%
01005
28 40
28 40
28 40
28 40
13 28 40
13 28 40
7 28 35
7 10 40
7 10 40
7 10 40
7 10 40
7 40
7 40
10% X5R0.1UF
6.3V 201
10% X5R0.1UF
6.3V 201
10% X5R0.1UF
6.3V 201
10% X5R0.1UF
6.3V 201
10% X5R0.1UF
6.3V 201
10% X5R0.1UF
6.3V 201
VIDEO: DISPLAY PORTSYNC_DATE=N/ASYNC_MASTER=JAMES
RADAR:8481319U1701311S0341311S0536
DP_AP_HPD
=PP3V0_IO_MISC
FW_ZENER_PWR DP_BUF_HPD
=PP1V8_H4
DP_AP_AUX_N
DP_AP_TX_P<0>
DP_AP_TX_N<1>
DP_AP_TX_P<1>
DP_AP_TX_N<0>
DP_EMI_TX_P<0>
DP_EMI_TX_P<1>
DP_EMI_TX_N<1>
DP_EMI_TX_N<0>
DP_AP_AUX_P DP_EMI_AUX_P
DP_EMI_AUX_N
=PP3V0_IO_MISC
DP_EMI_AUX_N
DP_EMI_AUX_P
C1702 1 2
C1703 1 2
C1704 1 2
C1705 1 2
C1706 1 2
C1707 1 2
R17201
2
R17231
2
R17311
2
U1701
2
3
1 5
6
4
C17501
2
R17511
2
R1750
1 2
17 OF 106
A.0.0
051-8962
13 OF 42
13 32
4 5 7 10 32
13 32
13 28 40
13 28 40
OUT
OUT
OUT
OUT
OUT
BI
IN
OUT
OUT
OUT
BI
MONITOR5
VDD33A_OSC
VSYNC
PPC
MONITOR6
MONITOR4
TCLKN
TEST
MONITOR1
S_DNDATA2
S_DPDATA2
S_DNDATA1
S_DPDATA1
S_DPDATA0
S_DNDATA0
VDD33A_18LDO
VDD33A_12LDO_1
VDD33A_12LDO_0
VDD33A_12LDO_2
VDD33P_LVDS
VDD33A_LVDS
VDD33D_LVDS
TCLKP
TCN
TCP
TBN
TBP
TAN
TAP
PWM
VSS33A_18LDO
VSS33A_12LDO_0
VSS33A_12LDO_1
VSS33A_LVDS
MONITOR3
MONITOR2
MONITOR0
M_DPDATA0
S_DPCLK
S_DNCLK
M_DNDATA0
TDP
TDN
ROUT_LVDS
SWI
RESET*
VSS33D_LVDS
VSS12D_PLL
VSS33P_LVDS
MLC_SCL
MLC_SDA
EDID_SCL
EDID_SDA
M_DPCLK
M_VREG_0P4V
M_DNCLK
CAP_12LDO_5
CAP_12LDO_3
CAP_12LDO_1
CAP_12LDO_0
CAP_18LDO
BIST
S_DNDATA3
S_DPDATA3
WC*
E2
E0
SDASCL
E1
VSS
VCC
EEPROM
THM_P
PP
PP
PP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
WHEN WC_L IS LOW, CAN WRITE TO EEPROM
WHEN WC_L IS HIGH, CANNOT WRITE TO EEPROM
MLC EEPROM:RAW APN 335S0661
16 40
16 40
16 40
16 40
16
8.45K1/20W
201MF
1%
15
15
16
16
15
15
201
1/20W5%
4.7K
MF201
1/20W5%
4.7K
MF
201MF
1%1/20W
100K
X5R201
10%10V
2.2NF FBGA1S6T2MLC
OMIT
MLP
M24C64
80-OHM-0.2A-0.4-OHM
0201-1
80-OHM-0.2A-0.4-OHM
0201-1
0201-1
80-OHM-0.2A-0.4-OHM
X5R-CERM6.3V20%
402
4.7UF6.3V20%
4.7UF
402X5R-CERM
20%
402
6.3V
4.7UF
X5R-CERM
0.1UF20%10VCERM402 402
CERM
0.1UF10V20% 20%
10V
0.1UF
402CERM
402
20%6.3V
4.7UF
X5R-CERM
201MF
1/20W1%
100K1%
MF1/20W
100K
201
10K
MF1/20W
1%
201
X5R-CERM
4.7UF6.3V20%
402
201
100K1/20W
1%
MF
NOSTUFF
201
100K1/20W
MF
1%
NOSTUFF
SMP4MM
4.7UF
X5R-CERM402
20%6.3V
NOSTUFF
P4MMSM
NOSTUFF
P4MMSM
402
0.1UF20%10VCERM
5%82PF
0201CERM25V
6
7 14 40
7 40
7 14 40
7 40
6.3VX5R-CERM
4.7UF
402
20%
7 40
7 40
7 40
7 40
7 40
7 14 40
16 40
16 40
16 40
16 40
CRITICALMLC EEPROM 100MHZ LVDS,2MHZ SWI1 100MHZ_PANELU2001341S2799
138S0652 138S0618 RADAR:8377307C2000,C2001,C2002,C2003,C2010,C2011,C2012,C3609,C3611,C3616
SYNC_DATE=N/ASYNC_MASTER=MIKE
VIDEO: MLC
MLC_MUX_SDA_3V3
MLC_MUX_SCL_3V3
TP_PM_LCD_BKLT_PWM
NC_MLC_MONITOR3
MLC_MONITOR0_PD
=PP3V3_MLC
NC_MLC_MONITOR2
MIPID_AP_CLK_P
NC_MIPI_MLC_MASTER_CLK_P
NC_MLC_MONITOR6
NC_MLC_MONITOR5
NC_MLC_MONITOR4
NC_LVDS_DATA_P<3>
MIPID_AP_DATA_P<0>
NC_MIPI_MLC_MASTER_CLK_N
MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.2 MMVOLTAGE=0.4V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MLC_VREG_0V4
PP3V3_MLC_18LDO_12LDO
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4 MM
NC_MIPI_MLC_MASTER_DATA_P
NC_MIPI_MLC_MASTER_DATA_N
MLC_CAP_1V2_LDO_5VOLTAGE=1.2V
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMMAX_NECK_LENGTH=3 MM
NC_MLC_MONITOR1
MIPID_AP_DATA_P<2>
RST_MLC_L
LVDS_DATA_N<0>
LVDS_DATA_P<0>
LVDS_CLK_N
MIPID_AP_DATA_N<3>
MIPID_AP_DATA_P<3>
MIPID_AP_DATA_N<2>
MIPID_AP_DATA_P<1>
MLC_SDA_3V3
MLC_SCL_3V3
LVDS_DDC_DATA
LVDS_DDC_CLK
PM_MLC_PPC_OUT
LVDS_DATA_P<2>
LVDS_DATA_N<1>
LVDS_DATA_P<1>
=PP3V3_MLC
MLC_2WC_L
MLC_BIST
MLC_TEST
=PP3V3_MLC
SWI_MLC
MIPID_AP_DATA_N<1>
MLC_CAP_1V8LDO
MIN_LINE_WIDTH=0.4 MMVOLTAGE=1.2V
MIN_NECK_WIDTH=0.2 MMMAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
MLC_CAP_1V2LDO_1_3
NET_SPACING_TYPE=PWR
VOLTAGE=1.2V
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM
MIPID_AP_DATA_N<3>
MIPID_AP_DATA_N<0>
MIPID_AP_DATA_P<0>
MIPID_AP_CLK_N
MIPID_AP_CLK_PLVDS_CLK_P
PP3V3_MLC_LVDS
MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MMMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMVOLTAGE=3.3V
PP3V3_MLC_DIG_12LDO
MLC_CAP_1V2LDO_0
MIN_LINE_WIDTH=0.4 MMVOLTAGE=1.2V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.2 MM
TP_MLC_VSYNC
ROUT_LVDS
NC_LVDS_DATA_N<3>
LVDS_DATA_N<2>
C2000 1
2
C2003 1
2
C2001 1
2
C2002 1
2
R20011
2
C20041
2
U2000
B7
E3
H7
A7
A4
C3
A8
B6
C2
B2
C1
B1
B3
A6
A5
H5
G3
G4
G5
F4
E4
D3
G6
D4B5
C5
F2
D2
E2
G2
H2
F1
D1
E1
G1
H1
H6
G7
G8
F7
F8
C7
C8
E7
E8
D7
D8
B8
F3
H8
B4
A2
C6
H4
E5
D5
A3
H3
C4
A1
D6
F6
E6
F5
U2001
1
2
3
6 5
9
8
4
7
FL2000
1 2
FL2001
1 2
FL2002
1 2
C2010 1
2
C2011 1
2
C2012 1
2
C20131
2
C20141
2
C20151
2
R20021
2
R20031
2
R20061
2
R20081
2
R20101
2
PP20001
PP2009
1
PP2011
1
C20171
2
C20161
2
R20501
2
R20511
2
R20521
2
20 OF 106
A.0.0
051-8962
14 OF 42
14 16 32
7 14 40
7 14 40
14 16 32
14 16 32
7 14 40
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SYNC_MASTER=MIKE
VIDEO: MLC ALIASESSYNC_DATE=N/A
MLC_MUX_SCL_3V3
MLC_MUX_SDA_3V3MLC_SDA_3V3
MLC_SCL_3V3
21 OF 106
A.0.0
051-8962
15 OF 42
14
14 14
14
S
D
G
DS
G
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
OUT
TABLE_ALT_ITEM
TABLE_ALT_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
3 A
RDS(ON)
CABLINE-CA CONNECTOR: 518S0787
NOTE: CONNECTOR ON PANEL IS FLIPPED
(LVDS DDC POWER)
THE CHOKE
LVDS CONNECTOR
NC
SIA413DJSIA413DJ
IMAX
CHANNEL
VGS MAX
100MOHM @-1.5V
+/- 8V
P-TYPE
MOSFET
NOSTUFF RESISTORS ARE THERE TO
INVESTIGATE POSSIBILITY OF REMOVING
5%
MF
10K1/20W
201
10K5%1/20W
201MF
FERR-120-OHM-1.5A
0402
1000PF
201
16VX7R
10%
603X5R6.3V20%10UF0.1UF
X5R201
10%6.3V
MF
1%1/20W
100K
201
2N7002TXGSOT-523-3
CRITICAL
SIA413DJSC70-6L
10%
X5R6.3V
0201
0.015UF
1/20W
39K1%
MF201
NOSTUFF
1%10K1/20W
201MF
NOSTUFF
201
1%
MF1/20W
10K
MF1/20W1%
201
21.5K
10%50V
402
820PF
CERM
5%
402CERM50V
100PF
25VCERM0201
82PF5%5%
82PF
0201CERM25V
5%82PF
0201CERM25V
25VCERM0201
82PF5%
82PF
0201
25V5%
CERM
0402
FERR-240-OHM-25%-300MA
14
14
14
14 40
14 40
14 40
14 40
14 40
14 40
14 40
14 40
35
35
35
35
35
35
90-OHM-50MATCM0605
TCM060590-OHM-50MA
TCM060590-OHM-50MA
TCM060590-OHM-50MA
MF1/20W5%
0
201
CABLINE-CAF-RT-SM
CRITICAL
35
10%
201
1000PF
X7R16V
Q2200376S0796 RADAR:8403895376S0961
VIDEO: LVDS CONNECTORSYNC_DATE=N/ASYNC_MASTER=ALEX
376S0903 376S0796 Q2200 RADAR:8403865
RADAR:8376383155S0583 155S0460L2202,L2212,L2222,L2232,L5500,L5501,L5600,L5601,L5702,L5716
LVDS_CLK_N
LED_IO_3
LED_IO_4
LCDVDD_PWREN_L
PM_MLC_PPC_OUT
=PP3V3_LCD
=PP3V3_MLC
PP3V3_S0_LCD_FERR
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MM
LVDS_DATA_N<0>
LVDS_DATA_N<1>
LVDS_DATA_P<2>
LVDS_CLK_P
R2250_1LCDVDD_PWREN_L_R
LVDS_DATA_P<0>
LVDS_DATA_CONN_P<0>
LED_IO_5
LVDS_DATA_P<1>
LVDS_DATA_N<2> LED_IO_1
LED_IO_2
LVDS_CLK_CONN_N
VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM
PP3V3_LCDVDD_SW_FMIN_NECK_WIDTH=0.20 MM
BOARD_TEMP4
LVDS_DATA_CONN_N<0>
LVDS_DDC_DATA
LVDS_DDC_CLK
LVDS_DATA_CONN_N<1>
=PPLED_REG
BOARD_TEMP4_N
LVDS_DATA_CONN_P<1>
=PP3V3_MLC
NC_LCD_PGAMMA
PPLED_BACK_REG
VOLTAGE=20.4VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
LED_IO_6
LVDS_CLK_CONN_P
LVDS_DATA_CONN_P<2>
LVDS_DATA_CONN_N<2>
C2206
1 2
R22001
2
R22011
2
L2201
1 2
C2200
1 2
C22021
2
C22031
2
R22051
2
Q22013
1
2
Q2200
1
3
47
C2204
1 2
R22031
2
R22101
2
R22111
2
R22041 2
C22201
2
C22331
2
C22411
2
C22401
2
C22301
2
C22321
2
C2231
1 2
L2200
1 2
L2202
1
2 3
4
L2232
1
2 3
4
L2222
1
2 3
4
L2212
1
2 3
4
R22501 2
J2201
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
5
6
7
8
9
22 OF 106
A.0.0
051-8962
16 OF 42
32
14 16 32
40
40
40
40
32
35
40
14 16 32
40
40
40
CTRL
PGND
THRML
L
VIN
DO
FB
SW
PAD GND
VCCA
1B1
1B2
2A2
1A1
2A1
1A2
2DIR
2OE*
1DIR
1OE*
2B2
2B1
GND
VCCB
VSTM26
VSTM25
VSTM24
VSTM23
MUX19
MUX17
BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
MUX8
MUX9
MUX10
MUX11
MUX12
MUX13
MUX16
MUX15
MUX18
MUX20
MUX21
MUX22
MUX23
NC
VSTM1
VSTM0
VSTM6
VSTM5
VSTM4
VSTM3
VSTM2
VSTM8
VSTM11
VSTM10
VSTM7
VSTM16
VSTM15
VSTM14
VSTM13
VSTM12
VSTM21
VSTM20
VSTM19
VSTM18
VSTM17
VSTM22
VSTM27
VSTM31
VSTM30
VSTM29
VSTM28
VSTM32
VSTM36
VSTM35
VSTM34
VSTM33
VSTM37
VSTM42
VSTM41
VSTM40
VSTM39
VSTM38
VSTM47
VSTM45
VSTM44
VSTM43
A_AD_R2
A_AD_R1
A_AD_R0
MUX14
VSTM46
GND
VSTM9
VDDHVCC_DIG
VCC
OE
A
NC
Y
GND
NCOE*
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUTIN
IN
IN
IN
OUT
OUT IN
OUT
OUT
OUT
OUT
OUT
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
MIN_NECK_MIDTH SHOULD BE 0.4MM
MATES WITH LEFTMOST GRAPE FLEX TAIL
BOOST CONVERTOR
NC
NC
MATES WITH RIGHTMOST GRAPE FLEX TAIL
NC
P/N 518S0817
NC
NC
NC
NC
NC
(A -> B)
TO Z1/Z2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TO Z2
APN:311S0485
NC
LOAD CURRENT ~ 153UA
CONNECTORS TO GRAPE FLEX
603-1
25VX5R
10%1UF
4.7UH-700MA-280MOHM
VLF
TPS61045
CRITICAL
QFN-1
SM
0.1UF
6.3V
201X5R
10%
X5R201
6.3V10%0.1UF
201
5%1/20WMF
10K10K
201MF
5%1/20W
MF1/20W
201
5%3.3K
5%10K
201
1/20WMF
6.3VX5R
10%
201
0.1UF
10%
201X5R6.3V
0.1UF
5%1/20WMF
10K
201
PQFP1
SN74AVCH4T245RSV
CRITICAL
402X5R25V10%
0.1UF
402X5R25V10%
0.1UF
402X5R25V10%
0.1UF
6.3VX5R
0.1UF10%
201
BGAGROUNDHOG
CRITICALOMIT
LLP
CRITICAL
SN74LVC1G126DRYR-M
LLP
CRITICAL
SN74LVC1G125DRYR-M
5 17 40
5 17 40
5 17 40
6
5 17 40
5 17 40
5 17 40
6
18
17 18
18
17 18
5 17 40 18
17 18
17 18
17 18
18
5 17 40 18
18
18
18
18
18
10%16V
470PF
201X5R-X7R
F-RT-SM
502250-8237
F-RT-SM
502250-8237
402
1%1M
1/16WMF-LF
1%1/20W
201
71.5K
MF2.2UF
X5R6.3V10%
603
NP0-C0G
5%
201
25V
33PF
B0520WSXG
SOD-323
0.1UF10%
X5R402
16V
1%
201MF
0.1
1/20W
U3009311S0524 311S0533
U3010311S0525 311S0532
311S0523 311S0485 U3007
SYNC_MASTER=RAMSIN SYNC_DATE=N/A
GRAPE: GROUNDHOG,CONN,BOOST
1 IC,ASIC,GROUNDHOG B0,120B BGA U3003 CRITICAL343S0525
MIN_LINE_WIDTH=0.2MM
VR_BOOST_SW
VR_BOOST_FBK
SPI_GRAPE_SCLK
MUX_IN<9>
MT_PANEL_OUT<29>
=PP3V0_GRAPE
MUX_IN<1>
MUX_IN<11>
MUX_IN<12>
MUX_IN<15>
MUX_IN<19>
=PP3V0_GRAPE
MUX_IN<18>
MUX_IN<17>
MUX_IN<16>
MUX_IN<7>
MUX_IN<6>
MT_PANEL_OUT<18>
MT_PANEL_OUT<19>
MT_PANEL_OUT<26>
SPI_GRAPE_MOSI
Z1_CS_OE
SPI_GRAPE_MISO
MIN_NECK_WIDTH=0.25MM
PP18V_R_GRAPEVOLTAGE=18V
MIN_LINE_WIDTH=0.6MMNET_SPACING_TYPE=PWR
PP18V_GRAPEMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=18VNET_SPACING_TYPE=PWR
GRAPE_FW_DNLD_EN_L
AGND_U3000MIN_LINE_WIDTH=0.2MM
PP18V_GRAPE=PP3V0_GRAPE_MARIO1
Z1_SCLK
Z2_H_CS_L
Z1_MOSI
Z1_MISO
Z2_H_CS_L
Z1_CS_OE
PM_BOOST_EN
MT_PANEL_OUT<32>
MT_PANEL_OUT<25>
MT_PANEL_OUT<24>
MT_PANEL_OUT<23>
MT_PANEL_OUT<6>
MT_PANEL_OUT<8>
MT_PANEL_OUT<11>
MT_PANEL_OUT<10>
MT_PANEL_OUT<7>
MT_PANEL_OUT<16>
MT_PANEL_OUT<15>
MT_PANEL_OUT<12>
MT_PANEL_OUT<21>
MT_PANEL_OUT<20>
MT_PANEL_OUT<17>
MT_PANEL_OUT<28>
MT_PANEL_OUT<36>
MT_PANEL_OUT<35>
MT_PANEL_OUT<34>
MT_PANEL_OUT<37>
MT_PANEL_OUT<39>
MT_PANEL_OUT<38>
MT_PANEL_OUT<9>
MT_PANEL_OUT<0>MUX_IN<0>
MUX_IN<2>
MUX_IN<3>
MUX_IN<14>
MUX_IN<13>
Z1_BON_L<3>
Z1_BON_L<0>
Z1_B_ADR<1>
Z1_CS_OE
Z1_CS_L
MT_PANEL_OUT<14>
SPI_GRAPE_CS_L
DIR_U3007
Z1_B_ADR<2>
MT_PANEL_OUT<1>
GRAPE_MOSI
GRAPE_SCLKMAKE_BASE=TRUESPI_GRAPE_SCLKMAKE_BASE=TRUESPI_GRAPE_CS_L GRAPE_CS_L
=PP3V0_GRAPE
RST_GRAPE_Z1_L
MAKE_BASE=TRUE
RST_GRAPE_L
RST_GRAPE_Z2_L
MAKE_BASE=TRUESPI_GRAPE_MOSI
MAKE_BASE=TRUE
SPI_GRAPE_MISO GRAPE_MISO
MT_PANEL_OUT<22>
MIN_LINE_WIDTH=0.2MM
VR_BOOST_L
Z1_BON_L<4>
Z1_BON_L<5>
Z1_BON_L<2>
=PP3V0_GRAPE
MT_PANEL_IN<10>
MT_PANEL_IN<8>
MT_PANEL_IN<1>
MT_PANEL_IN<3>
MT_PANEL_IN<5>
MT_PANEL_IN<7>
MT_PANEL_IN<9>
MT_PANEL_IN<11>MT_PANEL_IN<12>
MT_PANEL_IN<13>MT_PANEL_IN<14>
MT_PANEL_IN<15>MT_PANEL_IN<16>
MT_PANEL_IN<17>MT_PANEL_IN<18>
MT_PANEL_IN<19>MT_PANEL_IN<20>
MT_PANEL_IN<21>MT_PANEL_IN<22>
MT_PANEL_IN<23>MT_PANEL_IN<24>
MT_PANEL_IN<25>MT_PANEL_IN<26>
MT_PANEL_IN<27>MT_PANEL_IN<28>
MT_PANEL_IN<29>
MT_PANEL_OUT<39>MT_PANEL_OUT<38>
MT_PANEL_OUT<37>MT_PANEL_OUT<36>
MT_PANEL_OUT<35>MT_PANEL_OUT<34>
MT_PANEL_OUT<0>MT_PANEL_OUT<1>
MT_PANEL_OUT<2>
MT_PANEL_OUT<4>MT_PANEL_OUT<5>
MT_PANEL_OUT<6>MT_PANEL_OUT<7>
MT_PANEL_OUT<8>MT_PANEL_OUT<9>
MT_PANEL_OUT<10>MT_PANEL_OUT<11>
MT_PANEL_OUT<12>MT_PANEL_OUT<13>
MT_PANEL_OUT<14>MT_PANEL_OUT<15>
MT_PANEL_OUT<16>MT_PANEL_OUT<17>
MT_PANEL_OUT<18>MT_PANEL_OUT<19>
MT_PANEL_OUT<22>MT_PANEL_OUT<23>
MT_PANEL_OUT<25>
MT_PANEL_OUT<27>MT_PANEL_OUT<28>
MT_PANEL_OUT<29>MT_PANEL_OUT<30>
MT_PANEL_OUT<31>MT_PANEL_OUT<32>
MT_PANEL_OUT<33>
MT_PANEL_OUT<26>
MT_PANEL_OUT<24>
=PP3V0_GRAPE
Z1_B_ADR<0>
MT_PANEL_OUT<3>
MT_PANEL_OUT<20>
MT_PANEL_IN<4>
MT_PANEL_IN<6>
MT_PANEL_OUT<21>
MT_PANEL_IN<2>
MT_PANEL_IN<0>
MT_PANEL_OUT<33>
MT_PANEL_OUT<31>
MT_PANEL_OUT<30>
MT_PANEL_OUT<27>
Z1_BON_L<1>
MUX_IN<5>
MUX_IN<8>
MUX_IN<10>
MUX_IN<4>
MT_PANEL_OUT<5>
MT_PANEL_OUT<4>
MT_PANEL_OUT<3>
MT_PANEL_OUT<2>
MT_PANEL_OUT<13>
C30001
2
R3009 1
2
R30121
2
C3008 1
2
D30001 2
C30091 2
L3000
1 2
U3000
53
4
6
1
7
8
9
2
XW3000
1
2
C30011
2
R30661 2
C30311
2
C30301
2
R30311
2
R30301
2
R30321
2
R30251
2
C30411
2C30501
2
R30331
2
U3007
6
7
15
14
4
1
8
9
13
12
5
16
10
11
3 2
C3005 1
2
C3007 1
2
C3053 1
2
C30061
2
U3003
A10
B9
A9
C7
A7
B7
B8
A8
C8
C9
D7
G7
G8
E3
E5
E6
E7
F6
F7
G5
G6
B1
C1
I5
J8
J9
K8
J10
I10
H10
F11
C11
E10
E1
A11
B4
A5
A2
F2
H1
J1
J2
J3
K4
H5
C6
D3
F5
F8
F9
G3
G4
G9
H3
H4
H7
H8
D4
H9
J6
K7
D5
D6
D8
D9
E4
E8
F4
A6
B6
E9
F3
A1
B2
H2
I2
K1
K2
I3
K3
J4
I4
K6
H6
C2
K5
J5
I7
K9
I8
K10
I6
J7
K11
I9
D1
J11
I11
H11
G11
G10
F10
C10
D10
E11
D11
D2
B11
B10
C4
A4
B5
C5
A3
B3
E2
F1
G1
G2
I1
U3010
2
3
1
6
4
U3009
2
3
1
6
4
C30021
2
J3010
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
38
39
4
40
41
56
78
9
J3011
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
38
39
4
40
41
56
78
9
30 OF 106
A.0.0
051-8962
17 OF 42
5
5
18
17
17 18 32
18
18
18
18
18
17 18 32
18
18
18
18
18
17
17
17
17
17 32
18
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17 18
18
18
18
18
18
18
18
17
18
17
17 18 32
17
18
18
18
17 18 32
18
18
18
18
18
18
18
18 18
18 18
18 18
18 18
18 18
18 18
18 18
18 18
18 18
18
17 17
17 17
17 17
17 17
17
17 17
17 17
17 17
17 17
17 17
17 17
17 17
17 17
17 17
17
17 17
17 17
17 17
17
17
17
17 18 32
18
17
17
18
18
17
18
18
17
17
17
17
18
18
18
18
18
17
17
17
17
17
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
IN
RESET*
DONE
GO
MOSI
IN9
VDDDIG
PCLK
STMIN
STMOUT
BON_L1
BON_L0
TM
IN0
IN1
IN30
IN31
IN29
IN22
IN23
IN24
IN25
IN26
IN27
IN28
IN21
IN20
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN10
IN8
IN6
IN5
IN4
IN7
IN3
IN2
IN53
IN52
IN51
IN50
IN49
IN48
IN47
IN46
IN45
IN44
IN43
IN42
IN41
IN40
IN39
IN32
IN33
IN34
IN35
IN36
IN37
IN38
IN60
IN61
IN62
IN63
IN59
IN58
IN57
IN56
IN55
IN54
GNDANA
B_ADR2
BON_L2
BON_L3
BON_L4
BON_L5
B_ADR0
B_ADR1
MISO
CS*
SCLK
IN19
VDDANA
VDDIO
V18
GNDIOGNDDIG
VDDANA VDDCORE
TM0
TM1
RESET*
LFOO
A_CS*
A_SDI
IN7_0
H_SCLK
VDDLDO
JTAG_TDI
JTAG_TCK
IN9_1
IN9_0
IN8_1
IN8_0
IN7_1
IN6_1
IN6_0
IN5_1
IN4_1
IN4_0
IN3_1
IN3_0
IN2_1
IN2_0
IN11_1
IN11_0
IN10_1
IN10_0
IN1_1
IN1_0
IN0_1
IN0_0
H_SDO
H_SDI
H_CS*
GPIO7
GPIO6
FLOO
BOOT_CFG1
BOOT_CFG0
BON_L5
BON_L4
BON_L3
BON_L2
BON_L1
BON_L0
B_ADR1
ARMTAPMD*A_SDO
A_SCLK
GPIO1
GPIO0
GPIO2
GPIO3
VDDIO
GPIO5
CLKIN
CLKOUT
EXTFLLIN
JTAG_TDO
JTAG_TMS
GPIO4
IN5_0
B_ADR2
B_ADR0
GND
TABLE_ALT_ITEM
TABLE_ALT_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
NC
PULL UP = RESERVED FOR FUTURE
NOTE: PLATEFORM DETECTION PIN "H5"
ARE EACH GENERATED WITHIN
FLOATING = K93/K94
NC
NC
MIN_NECK_MIDTH SHOULD BE 0.4MM
PULL DOWN = K48
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
INTERNAL PU
ZEPHYR 1+ ASIC
NC
NC
NC
NC
NC
NC
1
1
0
1
0
1
AUTONOMOUS
DEPENDENT 2
SLAVE
DEPENDENT 100
CFG1 CFG0 MODE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ARM9 MCU (Z2 BASED)
K48 USES DEPENDENT 2 MODE
INTERNAL PU
Z2 AND BYPASSED OUTSIDE
VDDANA AND VDDCORE
0201
05%1/20WMF
MF
5%1/20W
100K
201
201
05%
1/20WMF
X5R-CERM603
22UF20%6.3V
4.7UF20%6.3V
402X5R
17
5
17
17
17
17
17
17
17 18
17
17 18
17 18
17 18
17 18
17 18
17
35 39
5%
MF201
100K
NOSTUFF
1/20W
01005MF
1/32W
100
5%
01005
5%
100
1/32WMF
2.2UF
X5R
20%
402
4V
201X5R
10%6.3V
0.1UF
201X5R
10%6.3V
0.1UF2.2UF20%4VX5R402
MF1/20W
4.7
5%
201
X5R201
10%6.3V
0.1UF
201
10%
X5R6.3V
0.1UF
0.1UF6.3V10%
201X5R
BGA-HF
CRITICAL
BCM5973
100K1/20W5%
201MF
0.1UF
201
6.3VX5R
10%
6.3V
0.1UF
201X5R
10%
603
20%6.3VX5R
10UF
2.2UF20%4VX5R402
Z1_GO
CRITICAL
BCM5974CKFBGHFBGA
201MF1/20W
100K5%
1.00
1/20WMF201
1%
GRAPE: Z1, Z2SYNC_DATE=N/ASYNC_MASTER=RAMSIN
RADAR:8392120C3107138S0648138S0652
138S0618 138S0648 BOM CONSOLIDATIONC3107
MT_3V3_INT
MIN_LINE_WIDTH=0.2MMVOLTAGE=3.0V
NET_SPACING_TYPE=PWR
=PP3V0_GRAPE
BOOT_CFG1_R
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
Z2_3V3_1V8_IN
NET_SPACING_TYPE=PWRVOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.8VNET_SPACING_TYPE=PWR
Z1_1V8_OUT
TP_U3101_TM0BOOT_CFG0_R
TP_U3101_TCK
TP_U3101_TDI
NC_BON_L2
NC_BON_L3
NC_BON_L4
HOST_REFCLK
TP_U3101_TDO
NC_BON_L1
RST_GRAPE_Z2_L
Z1_MOSI
Z1_MISO
Z1_SCLK
Z2_H_CS_L
=PP3V0_GRAPE
Z1_PCLK
TP_Z2_A_SCLK
TP_Z2_A_SDO
TP_Z2_A_SDI
CLK_32K_PMUMAKE_BASE=TRUE
GRAPE_SCLK
GRAPE_MISO
GRAPE_MOSI
GRAPE_CS_L
Z1_DONE
Z1_CS_OE_R
Z1_CS_OE
Z1_1V8_OUT
=PP3V0_GRAPE
Z1_STMIN
=PP3V0_GRAPE_Z1
Z1_CS_L
Z1_SCLK
Z1_MISO
Z1_GO
Z1_MOSI
Z1_DONE
Z1_B_ADR<1>
Z1_B_ADR<0>
Z1_B_ADR<2>
Z1_BON_L<1>
Z1_BON_L<2>
Z1_BON_L<3>
Z1_BON_L<4>
Z1_BON_L<5>
MUX_IN<2>
MUX_IN<3>
MUX_IN<6>
MUX_IN<5>
MUX_IN<4>
MUX_IN<7>
MUX_IN<8>
MUX_IN<9>
MUX_IN<10>
MUX_IN<11>
MUX_IN<12>
MUX_IN<14>
MUX_IN<15>
MUX_IN<16>
MUX_IN<17>
MUX_IN<19>
MUX_IN<18>
MT_PANEL_IN<2>
MT_PANEL_IN<3>
MT_PANEL_IN<5>
MT_PANEL_IN<6>
MT_PANEL_IN<8>
MT_PANEL_IN<7>
MT_PANEL_IN<9>
MT_PANEL_IN<10>
MT_PANEL_IN<11>
MT_PANEL_IN<13>
MT_PANEL_IN<12>
MT_PANEL_IN<14>
MT_PANEL_IN<15>
MT_PANEL_IN<16>
MT_PANEL_IN<22>
MT_PANEL_IN<26>
MT_PANEL_IN<24>
MT_PANEL_IN<27>
MT_PANEL_IN<28>
MUX_IN<1>
MUX_IN<0>
MT_PANEL_IN<29>
Z1_PCLK
MT_PANEL_IN<4>
MT_PANEL_IN<0>
=PP3V0_GRAPE_Z2
Z2_BON_L4
MT_PANEL_IN<25>
IRQ_GRAPE_HOST_INT_L
MT_PANEL_IN<17>
MT_PANEL_IN<18>
MT_PANEL_IN<21>
MT_PANEL_IN<20>
MT_PANEL_IN<19>
Z2_A_CS_L
TP_U3101_TMS
PM_BOOST_EN
MT_PANEL_IN<23>
RST_GRAPE_Z1_L
U3100_TM
U3101_TM1
Z1_BON_L<0>
MT_PANEL_IN<1>
Z2_VDDCOREVOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
=PP3V0_GRAPE_Z2
Z2_VDDANAVOLTAGE=1.8VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MUX_IN<13>
C31011
2
C31021
2
C31031
2
C31041
2
R31011 2
C31061
2
C31051
2
C31081
2
U3100
B2
B3
B4
A1
A2
A3
A4
A5
B1
A8
B6
C2
C9
D6
E6
F6
B7
C8
C3
B5
D1
D2
F3
F4
G1
G2
G3
G4
G5
H1
H2
H3
D3
H4
H5
J1
K1
J2
K2
J3
K3
J4
K4
D4
J5
K5
K6
J6
J7
K7
J8
K8
J9
K9
E1
J10
K10
H6
H7
H8
H9
H10
G6
G7
G8
E2
G9
G10
F7
F8
F9
F10
E7
E8
E9
E10
E3
D7
D8
D9
D10
E4
F1
F2
A7
A6
A10
C5
A9
B10
B9
B8
C6
C1
C10
D5
E5
F5
C7
C4
R31071
2
C31091
2
C31101
2
C31111
2
C31121
2
U3101
F1
G1
F2
G4E6
F9
F8
G9
J8
H9
J9
H7
J7
H5
F6
D3
E5
E4
G7
G5
C3
H8
C4
D6
D7
D8
C9
D9
G2
D1
J2
J3
H4
J6
G3
F3
F4
H6
H1
J1
H3
J4
A9
B9
B2
C1
B1
A1
A7
A8
B8
C8
B7
C7
A6
B6
C6
C5
B5
A5
A4
B4
A3
B3
C2
A2
G6
E8
E9
F7
F5
D5
E7
D4
D2
E1
G8
H2
J5
E2
E3
R31601
2
R31901 2
R3171
1 2
R31731
2
R31551
2
R3120
1 2
C31911
2
C31071
2
R31611
2
R31801 2
R31811 2
31 OF 106
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051-8962
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18
17 18 32
18
17 18 32
18
18
18
17 18 32
32
18
18
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
18
17
17
18 32
17
17
17
17
17
17
17
17
17
17
18 32
17
IN
OUT
IN
OUT
IN
IN
BI
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
OUT
IN
IN
OUT
IN
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
OUT
IN
IN
OUT
IN
OUT
IN
SCL
SDA
INT*
SPEAKEROUTB+
SPEAKEROUTB-
SPEAKEROUTA+
SPEAKEROUTA-
EAROUT+
EAROUT-
LINEOUT2B
LINEOUT2B_REF
LINEOUT2A
LINEOUT2A_REF
LINEOUT1_REF
LINEOUT1A
LINEOUT1B
HPOUT_REF
HPOUTB
HPOUTA
HP_DETECT
VL
VA
VCP
VP
VD
RESET*
MCLK
WAKE*
ASP_LRCLK
ASP_SCLK
ASP_SDIN
ASP_SDOUT
VSP_LRCLK
VSP_SLCLK
VSP_SDIN
VSP_SDOUT
XSP_LRCLK
XSP_SCLK
XSP_SDIN/DAC2B_MUTE
DMIC_SCLK
LINEINA_REF
MIC1
MIC2_REF
MIC2_DETECT_REF
MIC2_BIAS_FILT
MIC3A_BIAS
MIC3A_REF
MIC3B
FLYP
-VCP_FILT
+VCP_FILT
FLYC
FLYN
SPEAKER_VQ
FILT+
GND
GNDP
GNDA
GNDCP
GNDD
MIC2
MIC2_DETECT
MIC2_BIAS
MIC1_BIAS_FILT
MIC1_REF
LINEINB_REF
XSP_SDOUT
MIC3B_BIAS_FILT
MIC3B_REF
MIC3B_BIAS
MIC3A_BIAS_FILT
MIC3A
MIC1_BIAS
DMIC_SD
LINEINA
LINEINB
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
2.2UFRECOMMENDED
NOT USING SPEAKER AMPLIFIER, THIS CAN BE A NO STUFF
L63 AUDIO CODEC
I2C ADDRESS: 1001010X??
APN:338S0940
20%
X5R4V
01005
0.1UF
01005
10%
X5R6.3V
1000PF
27PF
01005
16VNP0-C0G
5%
402
10UF20%
X5R4V
SM
SM
SM
603
6.3VX5R
20%10UF
201
10%6.3VX5R
0.1UF
5 39
21
5 30 39
5
35
5 10 35 39
5 10 35 39
21
21
21
21 23
21
20 40
20 40
20 40
5 39
5 39
CRITICAL
402-1
6.3V
1UF10%
TANT
4VTANT
20%
402-3
4.7UF
10UF20%
6.3VX5R603
20%10UF
X5R6.3V
603
20 40
6.3V
4.7UF
402
20%
X5R-CERM
1.00K
01005
1%1/32WMF
402
6.3V20%
4.7UF
X5R-CERM
23 40
23 40
23
1.00K
1/32W1% MF
01005
23
35
5 39 22MF5%
1/32W 01005
5 39
5 30 39
5 30 39
5 30 39
1/32W5%
01005
22MF
01005
22MF5%
1/32W
5 39
5 39
5 39
5 39
20%
X5R4V
0.1UF
01005
24
23
CRITICAL
4.7UF
402
6.3V20%
X5R-CERM
NOSTUFF
5%01005MF22
1/32W
NOSTUFF
5% MF01005
22
1/32W
25
25
010055% MF
221/32W
MF010051/32W
225%
25
25
CS42L63BWLCSP
20%10V
X5R-CERM
2.2UF
402
402
2.2UF
X5R-CERM10V20%
4VX5R
20%
01005
0.1UF
AUDIO: L63 CODECSYNC_MASTER=LENG SYNC_DATE=N/A
=PPVCC_MAIN_AUDIO
=PP1V8_AUDIO
HP_DETI2C0_SCL_1V8
RIGHT_CH_OUT_P
CODEC_LINE_OUT_REF
NC_EAROUT_AN
NC_SPEAKEROUT_AP
NC_SPEAKEROUT_AN
NC_SPEAKEROUT_BP
NC_SPEAKEROUT_BN
VHP_FLYN
FILT_P
SPKR_VQ
VHP_FLYC
VHP_FLYP
LEFT_CH_OUT_P
VHPPFILT
NC_EAROUT_AP
RIGHT_CH_OUT_REF
LEFT_CH_OUT_REF
CODEC_LINE_OUT_L
CODEC_LINE_OUT_R
HP_REF
HP_L
HP_R
GND_AUDIO_CODEC
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=1.0MM
GND_AUDIO_HP_AMP
I2C0_SDA_1V8
NC_LINE_IN2_REF_CODEC
NC_LINE_IN2_CODEC
I2S_AP_3_DOUT
NC_MIC1_BIAS_CODEC
I2S_AP_0_MCK_R
I2S_AP_0_LRCK
I2S_AP_0_DOUT
I2S_AP_2_DOUT
I2S_AP_2_BCLK
MIC2_BIAS_FILT
MAX_NECK_LENGTH=75 MMMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
GND_AUDIO_CODEC
VHPNFILT
NC_LINE_IN1_CODEC
DMIC_SD_CODEC
L63_XSP_SDOUT
NC_MIC1N_CODEC
NC_MIC1_FILT_CODEC
EXT_MIC_BIAS
MIC2_DET
EXT_MIC_P
MIC2_DET_REF
EXT_MIC_REF
NC_MIC1P_CODEC
NC_LINE_IN1_REF_CODEC
DMIC_SCLK_CODEC
I2S_AP_3_BCLKI2S_AP_3_LRCK
L63_VSP_SDOUT
I2S_AP_2_LRCK
L63_ASP_SDOUT
I2S_AP_0_BCLK
AUD_MIK_HS1_INT_L
RST_L63_L
=PP1V7_VA_VCP
IRQ_CODEC_L
DMIC_SCLK_SENSOR
DMIC_SD_CANADA
DMIC_SCLK_CANADA
HSMIC_C_N
I2S_AP_2_DIN
I2S_AP_0_DIN
HSMIC_C_P
DMIC_SD_SENSOR
I2S_AP_3_DINC3617
1 2 C36181 2
C3602 1
2
C3601 1
2
C3600 1
2
C36051
2
C36061
2
XW3600
1 2
XW3601
1 2
XW3602
1 2
C3603 1
2
C36041
2
C36151
2
C36081
2
C3614 1
2
C36131
2
C3611 1
2
R36051 2
C3609 1
2
R36041 2
R3601 1 2
R3602 1 2
R3603 1 2
C36071
2
C36161
2
R36081 2
R36211 2
R36201 2
R36221 2
U3600
C8
B7
B8
A9
B5
A5
F3
G3
G1
F11
G11
E11
D8
D9
F2
E10
B10
G5
E9
F9
G10
G9
E4
C5
C4
D6
D5
E8
F8
G8
D7
E7
F7
G7
F10
B9
A3
D4
E2
B3
B1
C2
C1
D3
C3
B2
A1
D2
D1
A2
A4
F1
E1
B4
D10
E5
C6
C7
E6
G6
F6
G4
F4
G2
D11
B11
C11
F5
C9
C10
A11
A10
E3
B6
A6
A8
A7
36 OF 106
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20 32
32
19 21
21 23
19 21
39
39
39
32
OUT
IN
IN
OUT
OUT
OUT
OUT
VDD
EDGEGND
GAINSD*
OUT+
OUT-IN-
IN+
VDD
EDGE
GND
GAINSD*
OUT+
OUT-IN-
IN+
IN
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NC
LEFT CHANNEL IS INVERTED TO FIX CODEC BUG ON LINEOUT2
GAIN:6DB
GAIN:6DB
SHORTNCNCSPEAKER AMPLIFIER
APN:353S2958
TURN ON TIME: 7.5MS
TURN ON DELAY: 20MS
L63 LINEOUT2A IS CONNECTED TO U3700
80HZ +/- XXX%
GND
SHORT
47K
VDDGAIN
APN 518S0521
SPEAKER CONNECTOR
12DB9DB6DB3DB0DB
NCNC47KNC
L63 LINEOUT2B IS CONNECTED TO U3710
19 40
19 40
19 40
SM
SM
20
20
20
20
M-RT-SM78171-0004
X5R603
10V
10UF20%
10UF
10V
603
20%
X5R
CRITICALNOSTUFF
5%100PF
NP0-C0G16V
01005
CRITICALNOSTUFF
100PF5%
NP0-C0G16V
01005
CRITICALNOSTUFF
100PF5%
NP0-C0G16V
01005
CRITICALNOSTUFF
100PF5%
NP0-C0G16V
01005
WLCSPSSM2375
SSM2375WLCSP
01005
0.00
MF1/32W
0%
1/32W
01005
1%
MF
100
201
10%6.3VX5R
0.047UF
CRITICAL
0.000%
01005MF
1/32W
CRITICAL
6.3VX5R
0.047UF
201
10%
1/32W
01005
100
1%
MF
0.000%
01005MF
1/32W
01005
1/32W0%
MF
0.00
5 20
SM
SM
10%0.1UF
6.3V
201X5R
19 40
01005
1/32WMF
5%100K
0.1UF10%6.3VX5R201
CRITICAL
6.3V
0.047UF
10%
X5R201
CRITICAL
0.047UF
10%
201X5R6.3V
SYNC_DATE=N/ASYNC_MASTER=LENG
AUDIO: SPEAKER AMP
=PPVCC_MAIN_AUDIO
AUD_SPKRAMP_MUTE_L
RIGHT_CH_P
SPKRAMP_R_OUT_PSPKRAMP_L_OUT_N
SSM2375_L_GAIN
SPKRAMP_R_OUT_NMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM
SPKRAMP_L_OUT_P MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM
RIGHT_CH_OUT_P
RIGHT_CH_OUT_REF SSM2375_R_IN_N
SSM2375_R_IN_P
GND_SPKR_AMP2MIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM
SSM2375_R_GAIN
LEFT_CH_PLEFT_CH_OUT_P SSM2375_L_IN_P
SSM2375_L_IN_N
AUD_SPKRAMP_MUTE_L
=PPVCC_MAIN_AUDIO
SPKRAMP_R_OUT_N
LEFT_CH_OUT_REF
AUD_SPKR_AMP1_PBUSMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM
AUD_SPKR_AMP2_PBUS MIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MMGND_SPKR_AMP1
SPKRAMP_R_OUT_P MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM
SPKRAMP_L_OUT_P
SPKRAMP_L_OUT_NMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM
XW3700
1 2
XW3701
1 2
C3703 1
2
R37001
2
C3713 1
2
C3712
12
C3711
12
XW3710
1 2
XW3711
1 2
J3700
5
6
1
2
3
4
C37041
2
C37141
2
C3751 1
2
C37501
2
C3753 1
2
C37521
2
U3700
B2
A3
C1
A1
B1
B3
C3
A2
C2
U3710
B2
A3
C1
A1
B1
B3
C3
A2
C2
R37031
2
R370112
C3701
12
R37021
2
C3702
1 2
R371112
R37121
2
R37131
2
37 OF 106
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19 20 32
5 20
40
20
20
40
40
40 40
40
19 20 32
20
20
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CODEC DOCK
HEADPHONE OUTPUT ZOBEL NETWORK
DOCK LINE OUTPUT
01005MF
1%1001/32W
01005
1%
MF
1001/32W
10%6.3VX5R
33000PF
201201
6.3VX5R
10%33000PF
27PF
01005
5%
NP0-C0G16V
01005
16VNP0-C0G
27PF5%
15PF
NP0-C0G-CERM01005
16V5%
15PF16V5%
01005NP0-C0G-CERM
24
19 23
19
19
24
19 23
28
19
28
19
19
28
MF
1.00
1/20W1%
201
0.01UF10V
201
10%
X7R
NOSTUFF
28
SM
SM
SM
SM
NP0-C0G-CERM01005
16V
15PF5%
01005
5%16VNP0-C0G
27PF
SM
SM
SYNC_DATE=N/ASYNC_MASTER=LENG
AUDIO: HEADPHONE OUT
HP_ZL
GND_AUDIO_HP_AMP
MIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.1MM
AUDIO_EMI_LO_L
AUD_LO_REF_FILTMIN_LINE_WIDTH=0.1MMMIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM AUDIO_EMI_LO_RMIN_LINE_WIDTH=0.1MM
HP_R
AUD_HP1_MLBCON_LHP_L
AUD_HP1_MLBCON_R
CODEC_LINE_OUT_REF
MIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.1MM
CODEC_LINE_OUT_L
MIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.1MM
GND_AUDIO_CODEC
CODEC_LINE_OUT_R
MIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
MAX_NECK_LENGTH=75 MM
GND_AUDIO_PT_DK
MIN_LINE_WIDTH=0.1MMMIN_NECK_WIDTH=0.07MM AV_EMI_DIFF_SENSE
HP_ZR
HP_REF
R38511
2
R38501
2
C38511
2
C3850 1
2
C38531
2
C38521
2
C3802 1
2
C38011
2
R38001 2
C38001
2
XW3801
1 2
XW3802
1 2
XW3800
1 2
XW3803
1 2
C3803 1
2
C38541
2
XW3851
1 2
XW3850
1 2
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19 23
19
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THE INFORMATION CONTAINED HEREIN IS THE
36
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DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
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PAGE TITLE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
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B
C
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D
B
8 7 5 4 2 1
AUDIO: BLANKSYNC_MASTER=LENG SYNC_DATE=N/A
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OUT
OUT
IN
IN
IN
OUT
OUT
OUT
ADDR
SDA
SCL
REF
MIC
CLAMPO
CLAMPI
RAMPO
RAMPI
GND2
MIC2
GND
MIC1
VDD
GND1
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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THE INFORMATION CONTAINED HEREIN IS THE
36
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DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
EXT MIC LPF FC = 677KHZ
FROM HEADSET TO CODEC
EXTERNAL (HEADSET) MIC INPUT CIRCUITRY
0.1UF
201
6.3VX5R
10%
19 40
19 40
24
24
5%16V
33PF
NP0-C0G01005
X7R16V10%1000PF
201
201MF
470
1%1/20W
470
201MF
1%1/20W
201
5%
1K
1/20WMF
19
10%6.3VX5R
0.1UF
201
1/20W1%
MF
2.2K
201
2.2K
1/20W1%
MF201
0402-1
10UF
CERM-X5R6.3V20%
19 23 19 23
19 23 19 23
19 21
SM
WCSPTS3A8235YFP
10%
X5R6.3V
0.1UF
201
NP0-C0G-CERM01005
15PF5%16V
AUDIO: DETECT/MIC BIASSYNC_MASTER=LENG SYNC_DATE=N/A
=PP3V0_S2R_HALL_CHSW
HSMIC_R_P
HSMIC_R_N
EXT_MIC_P
EXT_MIC_REF
CHS_CLAMPO
CHS_CLAMPI
EXT_MIC_BIAS
AUD_HS_MIC1_LO
HP_REF
AUD_HS_RET1
AUD_HS_RET2
GND_AUDIO_HP_AMP
AUD_HS_MIC1_HI
CHS_SCL
CHS_SDA
HSMIC_C_N
HSMIC_C_N
HSMIC_C_P
HSMIC_C_P
C4211
1 2
C4212 1
2 C4213
1 2
C4216 1
2
C42171
2
R42121 2
R42131 2
R42011 2
C42001
2
R42021 2
R42031 2
C42011
2
XW4200
1 2
U4200
A2
C4
B4
C2
B2
B3
C3
D2B1
C1
D4
D3
D1
A3
A4
A1
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32
24
24
19 21
10
10
OUT
OUT
OUT
OUT
IN
IN
IN
IN OUT
OUTIN
OUT
IN
IN
IN OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
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B
C
345678
D
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8 7 5 4 2 1
HEADPHONE JACK CONNECTION IS ON FRONT PANEL FLEX, CSA 55/PDF 29PLACE ALL COMPONENTS NEAR J5501
HEADSET JACK INSERTION DETECT
23
0402
30-OHM-1.7A
0402
30-OHM-1.7A
23
25
25
25
25
25
0402
30-OHM-1.7A
0402
30-OHM-1.7A
25 23
23 25
240-OHM-0.2A-0.8-OHM
020124
21
21
201X7R
4700PF10V10%
NOSTUFF
01005
3.3K
1/32W5%
MF
24 19
SYNC_DATE=N/ASYNC_MASTER=LENG
AUDIO: HP/MIC FILTERS
HP_DET
CONN_AUD_HP1_DET_H AUD_HP1_DET_H
CONN_AUD_HP1_MLBCON_R
MAKE_BASE=TRUEMIN_LINE_WIDTH=1.0MMMIN_NECK_WIDTH=0.1MM AUD_HS_RET2CONN_AUD_HS_RET2
CONN_AUD_HS_RET1 AUD_HS_RET1MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=1.0MM
AUD_HS_MIC1_LOMIN_LINE_WIDTH=1.0MMMIN_NECK_WIDTH=0.1MMCONN_AUD_HS_MIC1_LO
MIN_LINE_WIDTH=1.0MMMIN_NECK_WIDTH=0.1MM
AUD_HS_MIC1_HIMIN_LINE_WIDTH=1.0MMMIN_NECK_WIDTH=0.1MM
CONN_AUD_HP1_MLBCON_L
AUD_HP1_MLBCON_R
AUD_HP1_MLBCON_L
AUD_HP1_DET_H
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=1.0MM
CONN_AUD_HS_MIC1_HI
L4303
1 2
C43101
2
R43121 2
L4306
1 2
L4304
1 2
L4301
1 2
L4302
1 2
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IN
BI
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
BI
BI
ININ
IN
IN
IN
IN
BI
BI
OUT
IN
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CANADA FLEXES CONN. SENSOR BOARD CONN ALIASESAPN: 518S0817
31
31
24
24
31
24
24
24
26
26
26 39
26 39
26 26 39
26 39
26 39
26 40
26 40
26 40
26 40
F-RT-SM
CRITICAL
502250-8237
24
19
19
24
SYNC_MASTER=MARK B. SYNC_DATE=N/A
CONNECTOR: CANADA FLEX CONN,SENSOR PANEL ALIASES
MIPI1C_CAM_DATA_P<0>
DMIC_SD_CANADAI2C2_SCL_3V0_ALSDMIC_SCLK_CANADACONN_AUD_HP1_MLBCON_L
SIM_RST
CONN_AUD_HS_RET1CONN_AUD_HS_RET2
PP3V0_ALSPM_FRONT_CAM_SHUTDOWN_FILTISP_CAM_1_SDAI2C2_SDA_3V0_ALS
SIM_CLK_FILTSIM_DETCONN_AUD_HS_MIC1_HI
MIPI1C_CAM_DATA_N<0>
MIPI1C_CAM_CLK_P
PP1V8_CAM_FFCLK_CAM_FF_CONN
ISP_CAM_1_SCL
MIPI1C_CAM_CLK_N
PP2V85_CAM_FF
PPVSIM
CONN_AUD_HS_MIC1_LO
IRQ_ALS_INT_CONN_L
CONN_AUD_HP1_MLBCON_R
SIM_IOMAKE_BASE=TRUE
PP2V85_CAM_REAR
MIPI0C_CAM_DATA_P<0>MAKE_BASE=TRUE
MAKE_BASE=TRUE
MIPI0C_CAM_CLK_P
PM_REAR_CAM_SHUTDOWNMAKE_BASE=TRUE
PP1V8_SENSOR_FILTMAKE_BASE=TRUE
CONN_I2C2_SDA_3V0
CONN_IRQ_GYRO_INT1
CONN_AUD_VOL_DOWN_FTR_LMAKE_BASE=TRUE
AUD_VOL_UP_L
CONN_PM_REAR_CAM_SHUTDOWN
CONN_MIPI0C_CAM_CLK_PMAKE_BASE=TRUE
MIPI0C_CAM_CLK_N CONN_MIPI0C_CAM_CLK_N
CONN_MIPI0C_CAM_DATA_P<0>
MAKE_BASE=TRUE
CLK_CAM_RF_FILT CONN_CLK_CAM_RF_FILT
MIPI0C_CAM_DATA_N<0>MAKE_BASE=TRUE
CONN_MIPI0C_CAM_DATA_N<0>
CONN_PP1V8_SENSOR_FILT
MAKE_BASE=TRUE
AUD_VOL_DOWN_L
CONN_I2C1_SCL_1V8
CONN_SRL_FTR_L
CONN_IRQ_GYRO_INT2
CONN_I2C1_SDA_1V8
CONN_IRQ_HALL
CONN_IRQ_PROX_INT_L
CONN_PP3V0_S2R_HALL
CONN_ONOFF_FTR_LONOFF_LMAKE_BASE=TRUE
CONN_AUD_HP1_DET_H
CONN_PP2V85_CAM_REAR
CONN_IRQ_ACCEL_INT2_L
CONN_ISP_AP_0_SDA
CONN_IRQ_ACCEL_INT1_L
CONN_I2C2_SCL_3V0
CONN_AUD_VOL_UP_FTR_L
CONN_PP3V0_OPTICAL_SENSMAKE_BASE=TRUE
PP3V0_OPTICAL_SENS
SRL_LMAKE_BASE=TRUE
MAKE_BASE=TRUE
PP3V0_S2R_HALL_FILTMAKE_BASE=TRUE
IRQ_PROX_INT_LMAKE_BASE=TRUE
IRQ_HALL
I2C1_SDA_1V8MAKE_BASE=TRUE
I2C1_SCL_1V8MAKE_BASE=TRUE
MAKE_BASE=TRUE
IRQ_ACCEL_INT1_LMAKE_BASE=TRUE
I2C2_SDA_3V0MAKE_BASE=TRUE
I2C2_SCL_3V0
ISP_AP_0_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUE
ISP_AP_0_SCLMAKE_BASE=TRUE
DMIC_SCLK_SENSORMAKE_BASE=TRUE
DMIC_SD_SENSOR CONN_DMIC_SD_SENSOR
CONN_DMIC_SCLK_SENSORCONN_ISP_AP_0_SCL
MAKE_BASE=TRUE
IRQ_GYRO_INT2MAKE_BASE=TRUE
IRQ_GYRO_INT1
IRQ_ACCEL_INT2_LMAKE_BASE=TRUE
J5501
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
38
39
4
40
41
56
78
9
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26
26
26
26 31
27
27 40
27 40
7
27
27
27
27
5
27
27
27 40 27
27
27 39 27
27 40 27
27
5
27
27
27
27
27
27
27
27 5 35
27
27
27
27
27
27
27 27
5 35
27
5
35
5 39
5 39
5
5 26 39
5 26 39
7 39
7 39
19
19 27
27
27
5
5
5
IN
IN
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
IN
BI
BI
OUTIN
IN
BI
BI
SYM_VER-1
SYM_VER-1
IN OUT
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
BI
BI
OUT
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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THE INFORMATION CONTAINED HEREIN IS THE
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DR
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SHEET
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PAGE
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B
C
345678
D
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8 7 5 4 2 1
CANADA FLEX CONN ON PG 54
FILTER PLACEHOLDER
FILTER PLACEHOLDER
FILTER PLACEHOLDER
CANADA FLEX SIGNAL FILTERS
0201
240-OHM-0.2A-0.8-OHM
7
7 39
0603800MHZ-100MA-27PF
800MHZ-100MA-27PF0603
7 39
7 39
5 25 39
5 7 40
7 40
7 40
7 40
0201
240-OHM-0.2A-0.8-OHM
10%
402X5R
1UF10V25V
5%
0201CERM
82PF
5%
0201
82PF
CERM25V
402
1UF
X5R
10%10V
TCM060590-OHM-50MA
90-OHM-50MATCM0605
NOSTUFF0
201MF
1/20W5%
201
0MF
1/20W5%
NOSTUFF
1/20W 201MF5%
0 NOSTUFF
201MF
1/20W5%
0
NOSTUFF
201X7R16V
1000PF10%
16VX7R
1000PF10%
201
X5R201
6.3V10%0.1UF
31 25
25
25 39
25 39
25 39
25
25 39
25 40
25 40
25 40
25 40
100K1/20WMF201
5%
NOSTUFF
25VCERM
5%
201
100PF
16VX7R
1000PF10%
201 402
1UF
X5R
10%10V
5%
0201
82PF
CERM25V
0201
240-OHM-0.2A-0.8-OHM
25 39
5 25 39
NOSTUFF
1000PF10%16VX7R201
CONNECTOR: CANADA FLEX FILTERS
SYNC_DATE=N/ASYNC_MASTER=MARK B.
I2C2_SDA_3V0_ALS
I2C2_SCL_3V0
ISP_CAM_1_SCL
I2C2_SDA_3V0CLK_CAM_FF_CONN
MIPI1C_AP_CLK_P
SIM_CLK
PPVSIM
=PP1V8_CAM=PP2V85_CAM
=PP3V0_OPTICAL
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=2.85V
PP2V85_CAM_FF
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.0V
PP3V0_ALS
MIN_LINE_WIDTH=0.6MM
MIPI1C_AP_DATA_N<0>
MIPI1C_CAM_DATA_N<0>
MIPI1C_CAM_DATA_P<0>
MIPI1C_AP_CLK_N
MIPI1C_CAM_CLK_N
MIPI1C_CAM_CLK_P
SIM_CLK_FILT
=PP1V8_CAM
MIPI1C_AP_DATA_P<0>
PP1V8_CAM_FFMIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.8V
NET_SPACING_TYPE=PWR
IRQ_ALS_INT_CONN_LIRQ_ALS_INT_L
I2C2_SCL_3V0_ALSISP_AP_1_SDA
PM_FRONT_CAM_SHUTDOWNISP_AP_1_SCL
ISP_CAM_1_SDAPM_FRONT_CAM_SHUTDOWN_FILT
CLK_CAM_FF
L5520
1 2
U5500
9
10
1
2
3
4
5
6
7
8
U5501
9
10
1
2
3
4
5
6
7
8
L5510
1 2
C55201
2
C55211
2 C55111
2
C55101
2
L5500
1
2 3
4
L5501
1
2 3
4
R55101 2
R55111 2
R55121 2
R55131 2
C55221
2 C55121
2
C55301
2
R55011
2
C55001
2
C55421
2
C55401
2
C55411
2
L5540
1 2
C55011
2
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25 31
26 32 27 32
5 27 32
25
25
26 32
25
SYM_VER-1
IN
IN
BI
BI
IN
SYM_VER-1
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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Apple Inc.
PAGE
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C
345678
D
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8 7 5 4 2 1
SENSOR PANEL CONNECTOR
CONNECTED BYPG 54 ALIASES
CABLINE-CA CONNECTOR: 518S0787NOSTUFF
5%
0
1/20W 201MF
TCM060590-OHM-50MA
5%NOSTUFF
0MF2011/20W
10%1000PF
X7R201
16V
NOSTUFF
201X7R16V
1000PF10%
0.1UF
201X5R
10%6.3V10V
402
10%1UF
X5R
82PF
CERM0201
5%25V
10%16VX7R201
1000PF
X5R10V10%1UF
402
10%16V
201X7R
1000PF
402
10V
1UF10%
X5R
25V5%
CERM
82PF
0201
7 40
7 40
7 40
7 40
0201
240-OHM-0.2A-0.8-OHM
201MF
1/20W5%
0
0201
82PF
CERM
5%25V
240-OHM-0.2A-0.8-OHM
0201
0201
240-OHM-0.2A-0.8-OHM
NOSTUFF
1/20W
0MF5%201
7 39
X7R
1000PF
201
16V10%
1UF10V10%
X5R402
CERM25V5%82PF
0201
240-OHM-0.2A-0.8-OHM
0201
CRITICAL
F-RT-SMCABLINE-CA
90-OHM-50MATCM0605
1/20W5% MF
201
0
NOSTUFF
CONNECTOR: SENSOR PANEL CONNECTOR
SYNC_MASTER=MARK B. SYNC_DATE=N/A
CLK_CAM_RF_FILT
MIPI0C_CAM_DATA_N<0>
MIPI0C_CAM_DATA_P<0>
CONN_PP2V85_CAM_REAR
CONN_PP1V8_SENSOR_FILT
CONN_ISP_AP_0_SCL
CONN_CLK_CAM_RF_FILT
CONN_ISP_AP_0_SDA
CONN_PM_REAR_CAM_SHUTDOWN
CONN_MIPI0C_CAM_CLK_N
CONN_MIPI0C_CAM_DATA_P<0>
CONN_MIPI0C_CAM_DATA_N<0>
CONN_IRQ_GYRO_INT2
CONN_IRQ_GYRO_INT1
CONN_PP3V0_S2R_HALL
CONN_I2C1_SCL_1V8
CONN_IRQ_HALL
CONN_MIPI0C_CAM_CLK_P
CONN_I2C2_SCL_3V0
CONN_I2C2_SDA_3V0
CONN_AUD_VOL_DOWN_FTR_L
CONN_ONOFF_FTR_L
CONN_SRL_FTR_L
CONN_AUD_VOL_UP_FTR_L
CONN_IRQ_PROX_INT_L
MIPI0C_CAM_CLK_P
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.0V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
PP3V0_S2R_HALL_FILT
MIPI0C_AP_DATA_N<0>
MIPI0C_AP_DATA_P<0>
MIPI0C_CAM_CLK_N
MIPI0C_AP_CLK_P
MIPI0C_AP_CLK_N
PP3V0_OPTICAL_SENS
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.0VMIN_LINE_WIDTH=0.6 MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
=PP2V85_CAM
=PP3V0_OPTICAL
=PP3V0_S2R_HALL
PP2V85_CAM_REAR
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.3VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWR
=PP1V8_SENSOR
CONN_IRQ_ACCEL_INT2_L
CONN_IRQ_ACCEL_INT1_L
CONN_I2C1_SDA_1V8
PP1V8_SENSOR_FILT
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.8V
NET_SPACING_TYPE=PWR
CONN_DMIC_SCLK_SENSOR
CONN_DMIC_SD_SENSOR
CONN_PP3V0_OPTICAL_SENS
CLK_CAM_RF
C56001
2
R56001 2
R56101 2
L5600
1
2 3
4
R56111 2
R56121 2
L5601
1
2 3
4
R56131 2
C56231
2
C56161
2
C56151
2
C56141
2
C56211
2
C56181
2
C56201
2
C56131
2
C56171
2
L5611
1 2
C56121
2
L5613
1 2
L5612
1 2
C5631
2
C56021
2
C56011
2
L5610
1 2
J5600
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
5
6
7
8
9
56 OF 106
A.0.0
051-8962
27 OF 42
25 39
25 40
25 40
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25 40
25
25 40
25
26 32
5 26 32
32
25
32
25
25
25
25
25
25
25
GND
VBUS
IO
NC
IO
NC
GND
VBUS
IO
NC
IO
NC
GND
VBUS
IO
NC
IO
NC
REF
GND
IN OUTBI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
GND
VBUS
IO
NC
IO
NC
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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DRAWING NUMBER SIZE
DR
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SHEET
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A
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DISPLAYPORT
FIREWIRE DETECT/ DISPLAYPORT HPD
(JTAG_TMS)
(JTAG_TCK)
NOTE:
JTAG_AP_TMS = 3.3V: U5730’S IN = 2.13V
0.095 OHM DCR
ACCESSORY
JTAGUSBANALOG VIDEO
NOTE:
JTAG_AP_TMS = 1.8V: U5730’S IN = 1.16V
LINEOUT
PLACE BY PMU
MAX CONTINUOUS VOLTAGE IS 19V - SPEC IS 16V
NP0-C0G
27PF25V5%
201
NP0-C0G
5%25V
201
27PF
5%
201NP0-C0G25V
27PF
201
25VNP0-C0G
27PF5%
201
NOSTUFF
NP0-C0G
27PF25V5%
NOSTUFF
27PF
201NP0-C0G
5%25V
SLP1210N6RCLAMP0502N
RCLAMP0502NSLP1210N6
RCLAMP0502NSLP1210N6
201
5%
NP0-C0G25V
12PF25VNP0-C0G
5%
201
27PF
0201
22-OHM-25%-900MA
X5R201
10%10V
0.01UF
25V
0.01UF
X7R402
10%
0402
FERR-120-OHM-1.5A
FERR-120-OHM-1.5A
0402
30-OHM-1.7A
0402
402
0.01UF50VX7R
10%
47K
1/20W5%
MF201
GDZ-0201GDZT2R5.1B
0201UCLAMP0511Z
UCLAMP0511Z0201
02016.8V-100PF
201
5%1001/20WMF
DEVELOPMENT_JTAG
00
DEVELOPMENT_JTAG
MAX9061UCSP
DEVELOPMENT_JTAG
0.1UF6.3V
201
10%
X5R
DEVELOPMENT_JTAG
MF201
220K1/20W5%
10K
1/20W5%
MF201
1%MF2011/20W
100K
4 39
4 39
13 40
13 40
13 40
13 40
13 40
13 40
10 11 40
10 11 40
10 11 40
21
21
21
21
11 39
11 39
201
1/20W
10K
5%
MF
4 39
4 39
4 31 35
35
35
13 35
0201
0.01UF10%16V
X5R-CERM
523K1%1/32WMF01005
DEVELOPMENT_JTAG
1.00M
DEVELOPMENT_JTAG
01005MF1/32W1%
12-OHM-100MA-8.5GHZTCM0806-4SM
TCM0806-4SM12-OHM-100MA-8.5GHZ
90-OHM-50MATCM0605
14.2V-6PF0201
6.8V-100PF0201
SM
OMIT
27V-100PF0402
BGAUSBULC6-2F3
201
1/20W5%
MF
0
0
MF
5%1/20W
201
FERR-120-OHM-1.5A
0402
0603
FERR-70-OHM-4A
CRITICAL
NUP412VP5XXGSOT953
8V-100PF0201
80-OHM-0.2A-0.4-OHM
0201
80-OHM-0.2A-0.4-OHM
0201
0201
80-OHM-0.2A-0.4-OHM90-OHM-50MATCM0605
5%
201
1/20WMF
100K
SLP1210N6RCLAMP0502N
IO FLEX: DOCK COMPONENTSSYNC_MASTER=JAMES SYNC_DATE=N/A
L5700,L5701155S0625 155S0559 RADAR:8423156
D5700,D5701,D5702,D5703 RADAR:8289785377S0066377S0107
DZ5710,DZ5711 RADAR:8379541377S0111 377S0099
DZ5751 ?377S0090 377S0081
DP_EMI_AUX_N DP_PT_DK_CON_AUX_N
DP_EMI_TX_N<1>
ACC_PT_DK_CON_PP3V3
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3VMIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
ACC_PT_DK_CON_ID
AV_PT_DK_CON_RET
DP_PT_DK_CON_TX_P<0>
USB_PT_DK_CON_D_P
AUDIO_EMI_LO_R
AUDIO_EMI_LO_L
GND_AUDIO_PT_DK
FW_PT_DK_CON_PWRACC_PT_DK_CON_TX
USB_FS_P_ACC_RX
PPVBUS_USB_PT_DK_CON
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=4.1MMVOLTAGE=5V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
AUDIO_PT_DK_RET
VIDEO_PT_DK_CON_C_Y
VIDEO_PT_DK_CON_CVBS_PB
VIDEO_EMI_C_Y
ACC_PT_DK_CON_DET_L
USB_D_N
USB_D_P
USB_PT_DK_CON_D_N
NC_D5703_6
PORT_DOCK_ACCID
PMU_ADC_REF
DP_EMI_TX_N<0>
DP_EMI_TX_P<0>
NC_D5700_6
AV_EMI_DIFF_SENSE
MIN_LINE_WIDTH=0.1MMMIN_NECK_WIDTH=0.07MM
AUDIO_PT_DK_CON_LO_R
AUDIO_PT_DK_CON_LO_L
MIN_LINE_WIDTH=0.1MMMIN_NECK_WIDTH=0.07MM
VIDEO_PT_DK_CON_Y_PR
PORT_DOCK_ACC_DET_L
=PP3V3_PORT_ACC
PPVBUS_USB_EMI
MIN_LINE_WIDTH=4.1MMMIN_NECK_WIDTH=0.2MM
=PPVCC_MAIN_DOCK
VIDEO_EMI_CVBS_PB
VIDEO_EMI_Y_PR VIDEO_PT_DK_CON_Y_PR
VIDEO_PT_DK_CON_C_Y
VIDEO_PT_DK_CON_CVBS_PB
RST_AP_L
=PP1V8_S2R_MISC
PT_DK_CON_P14
PT_DK_CON_P17
JTAG_AP_TCK
JTAG_AP_TMS
U5730_IN
USB_FS_N_ACC_TX
ACC_PT_DK_CON_RX
MIN_NECK_WIDTH=0.2MM
AUDIO_PT_DK_RETMIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.1MM
AV_PT_DK_CON_DIFF_SENSE
FW_ZENER_PWR
DP_EMI_AUX_P
NC_D5701_6
DP_EMI_TX_P<1>
DP_PT_DK_CON_TX_N<1>
DP_PT_DK_CON_TX_P<1>
DP_PT_DK_CON_AUX_P
NC_D5702_6
DP_PT_DK_CON_TX_N<0>
L5714
1 2
L5757
1 2
U5700
1
2
3 4
5
DZ5790
1
2
FL5711
1 2
FL5707
1 2
FL5708
1 2
L5716
1
2 3
4
R57901
2
D5703
1
5
4
6
C57501
2
C57511
2
C57521
2
C57531
2
C57541
2
C57551
2
D5702
1
5
4
6
D5701
1
5
4
6
D5700
1
5
4
6
C57221
2
C57211
2
L5762
1 2
C57821
2
C57831
2
L5761
1 2
L5760
1 2
L5763
1 2
C57801
2
R57101 2
DZ5720
1
2
DZ5710
1
2
DZ5711
1
2
DZ5712
1
2
R57401
2
R5730 1 2
R5731 1 2
U5730
B2
A2 A1
B1
C57301
2
R57501
2
R57511 2
R57521 2
R57531 2
C57601
2
R57951
2
R57961
2
L5700
1
2 3
4
L5701
1
2 3
4
L5702
1
2 3
4
DZ5752A
C
DZ5753
1
2
XW5700
1 2
DZ5760
1
2
DZ5751
A1
A2
B1
B2
R57201 2
R57211 2
57 OF 106
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2
3
2
3
2
3
2
3
29 40
29
29
29
29 40
29 39
29 29 39
29
28
28 29 40
28 29 40
29
29 39
35
29
29
28 29 40
32
32
32
28 29 40
28 29 40
28 29 40
5 32
29
29
29 39
28
29 29 40
29 40
29 40
29 40
OUT
IN
IN
IN
OUT
OUT
IN
IN
IN
OUT
BI
BI
IN
IN
IN
IN
BI
BI
IN
IN
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
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C
A
D
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(JTAG_TMS)
(JTAG_TCK)
(DP_HPD)
PN 516S0817 (PLUG - MALE)
5 29 35
6.8V-100PF0201
M-ST-SMAXK844135WG
CRITICAL
28 40
28 40
28 40
28
28
28
28
28 39
28 39
28 39
28 39
28 40
28 40
28 40
28 40
28 40
28 40
28
28
28
28
28
5 29 35
SYNC_MASTER=JAMES SYNC_DATE=N/A
IO FELX: B2B Connector
HOME_L
PPVBUS_USB_PT_DK_CON
VIDEO_PT_DK_CON_CVBS_PB
VIDEO_PT_DK_CON_C_Y
VIDEO_PT_DK_CON_Y_PR
ACC_PT_DK_CON_ID
FW_PT_DK_CON_PWR
PT_DK_CON_P14
PT_DK_CON_P17
ACC_PT_DK_CON_TX
ACC_PT_DK_CON_RX
USB_PT_DK_CON_D_P
USB_PT_DK_CON_D_N
DP_PT_DK_CON_TX_P<0>
DP_PT_DK_CON_TX_N<0>
DP_PT_DK_CON_TX_P<1>
DP_PT_DK_CON_TX_N<1>
ACC_PT_DK_CON_DET_L
AV_PT_DK_CON_DIFF_SENSE
AUDIO_PT_DK_CON_LO_L
AUDIO_PT_DK_CON_LO_R
DP_PT_DK_CON_AUX_P
ACC_PT_DK_CON_PP3V3
DP_PT_DK_CON_AUX_N
HOME_L
AV_PT_DK_CON_RET
DZ5750
1
2
J5900
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
56
78
9
59 OF 106
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051-8962
29 OF 42
28
28
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
IN
IN
OUT
IN
IN
BI
BI
BI
BI
BI
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
X23 WIFI/BT CONNECTOR
516S0884
AXT530224F-ST-SM
35
35
35
35
5
10
10
10
10
5 19 39
5 19 39
5 19 39
5 19 39
5 40
5 40
5 40
5 40
5 40
5 40
35 39
201
5%68PF
CERM25V
25VCERM
5%
201
68PF
0603
22-OHM-25%-0.5A-0.20DCR
0402
22-OHM-25%-0.4A-0.35DCR
SYNC_DATE=N/ASYNC_MASTER=MIKE
CONNECTOR: X23 WIFI/BT
PPVCC_MAIN_WL_CONNVOLTAGE=4.7VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
=PP1V8_S2R_WLPP1V8_S2R_WL_CONNVOLTAGE=1.8VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
=PPVCC_MAIN_WL
PM_WLAN_HOST_WAKE
SDIO_WL_CLK
SDIO_WL_DATA<3>SDIO_WL_DATA<2>SDIO_WL_DATA<1>SDIO_WL_DATA<0>
SDIO_WL_CMD
I2S_AP_2_LRCK
I2S_AP_2_DOUT
UART_AP_3_TXDUART_AP_3_RXD
PM_BT_WAKEPM_BT_HOST_WAKERST_BT_L
UART_AP_3_CTS_LUART_AP_3_RTS_L
I2S_AP_2_DIN
I2S_AP_2_BCLK
CLK_32K_WLAN
RST_WLAN_L
J6000
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
4
5 6
7 8
9
C6000 1
2
C6001 1
2
L6000
1 2
L6001
1 2
60 OF 106
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32
32
OUT
IN
IN
OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
BI
BI
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
OUT
OUT
BI
IN
OUT
OUT
IN
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MIN_NECK_MIDTH SHOULD BE 0.2MM
998-3141
X24 CELLULAR/GPS CONNECTOR
HB-SMOMIT
CELL-MODULE-X24
4 28 35
5
35
5
5
5 40
5
5 40
5 40
5 40
5
35
11 39
11 39
10
10
10
10
10
10
5
5
10
10
10
10
5
25
25
26
25
35 39
5
5
35
0.01UF
01005
10%6.3VX5R
NOSTUFF
MF1/32W
01005
255K1%
01005
1/32WMF
255K1%
35
SYNC_DATE=N/ASYNC_MASTER=MIKE
CONNECTOR: X24 CELLULAR/GPS
SPI_IPC_MOSI
IPC_GPIO
BB_VBUS_DETUSB_BB_D_P
ADC_IN7
SNSV_BATT_POS_ACF
RST_BB_PMU_L
SPI_IPC_MRDYSPI_IPC_SRDYSPI_IPC_SCLK
SPI_IPC_MISO
PM_BB_HOST_WAKE
RST_AP_L
=BATT_POS_F_3G
PM_RADIO_ON
GSM_TXBURST_IND
RST_DET_L
CLK_32K_GPS
UART_AP_1_CTS_LUART_AP_1_RTS_LUART_AP_2_RXDUART_AP_2_TXD
PM_GPS_STANDBY_L
UART_AP_4_CTS_L
GPS_SYNCUART_AP_4_RTS_L
UART_AP_4_TXD
SIM_CLK
UART_AP_4_RXD
RST_GPS_L=PP1V8_S2R_GPS
RST_BB_L
UART_AP_1_TXD
USB_BB_D_N
UART_AP_1_RXD
IRQ_GPS_INT_L
SIM_IO
MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=1.2VNET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PPVSIM
SIM_RSTSIM_DET
J6100
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5
50
6
7
8
9
C6100 1
2
R61001
2
R61011
2
61 OF 106
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32
32
25 26
BI
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MIN_NECK_MIDTH SHOULD BE 0.2MM
MIN_NECK_MIDTH SHOULD BE 0.2MM
MIN_NECK_MIDTH SHOULD BE 0.2MM
MIN_NECK_MIDTH SHOULD BE 0.2MM
MIN_NECK_MIDTH SHOULD BE 0.2MM
MIN_NECK_MIDTH SHOULD BE 0.2MM
MIN_NECK_MIDTH SHOULD BE 0.2MM
CHARGER MAINBUCK RAILSPROGRAMMABLE ON/OFF
LDO RAILS
POWER CONN / ALIAS
BATTERY
USB POWER INPUT
34
POWER: ALIASESSYNC_MASTER=YOSH SYNC_DATE=N/A
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PP3V0_S2R_HALLMAKE_BASE=TRUEVOLTAGE=3.0V
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 MM
=PP3V0_S2R_HALL_CHSW
=PP3V0_VIDEO_H4MAKE_BASE=TRUE
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm
PP3V0_VIDEOVOLTAGE=3.0VMIN_LINE_WIDTH=0.6 mm
MAX_NECK_LENGTH=0.8 MM
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.1MM
VOLTAGE=1.8VMAKE_BASE=TRUEPP1V8
MAX_NECK_LENGTH=0.8 MM
PP3V3_OUT
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3VMAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6MM
=PPVCC_MAIN_AUDIO
=PPVCC_MAIN_DOCK
=PP1V8_ALWAYS
MAX_NECK_LENGTH=0.8 MM
MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.6 MM
PP1V1
NET_SPACING_TYPE=PWR
MAKE_BASE=TRUEVOLTAGE=1.1V
=PP1V8_DPORT_H4=PP1V8_MIPI_H4=PP1V8_VDDIO18_H4=PP1V8_H4=PP1V8_AUDIO=PP1V8_SENSOR=PP1V8_CAM
=PP1V8_S2R_MISC
=PP1V8_S2R_H4
=PP1V2_VDDIOD_H4=PP1V2_HSIC_H4
=PP1V2_VDDQ_H4
=PP3V3_MLC
=PP3V3_LCD
=PPVDD_CPU_H4
=PP1V2_S2R_H4
MAX_NECK_LENGTH=0.8 MM
MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=1.2V
NET_SPACING_TYPE=PWR
MAKE_BASE=TRUEPP1V2_S2R
=PP3V0_VIDEO_BUFFER
PPVBUS_USB_EMI
=PP3V0_S2R_HALL
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 MM
MAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP3V2_SDVOLTAGE=3.2V
=PP1V8_S2R_GPSMIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=PWR
VOLTAGE=1.8V
MAX_NECK_LENGTH=3 MM
PP1V8_S2R
MAKE_BASE=TRUEVOLTAGE=1.8V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PP1V8_ALWAYS
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
MAX_NECK_LENGTH=3 MM
PPVCC_MAINVOLTAGE=4.7VMAKE_BASE=TRUE
NET_SPACING_TYPE=PWR =PPVCC_MAIN_LED
MAX_NECK_LENGTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2VMAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 MM
PP1V2
=PPLED_REG
=PP1V1_MIPI_H4=PP1V1_DPORT_H4
=PP1V1_PLL_H4
=PP3V0_GRAPE_Z1=PP3V0_GRAPE_Z2=PP3V0_GRAPE_MARIO1
=PP3V0_GRAPE
=PP2V85_CAM
=PP3V2_S2R_USBMUX
=PP3V0_VIDEO_BUF
=PP3V3_PORT_ACC
=PP3V0_OPTICAL
MIN_LINE_WIDTH=0.6MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2MM
VOLTAGE=2.85V
PP2V85_CAMMAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUEVOLTAGE=3.0V
PP3V0_GRAPE
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4 MM
NET_SPACING_TYPE=PWR
PP3V2_S2R_USBMUXVOLTAGE=3.2V
MIN_LINE_WIDTH=0.4 MM
PP3V0_VIDEO_BUFVOLTAGE=3.0V
MIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR
PP3V0_OPTICALVOLTAGE=3.0VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm =BATT_POS_F_3G
MAX_NECK_LENGTH=0.8 MM
MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=1.2VMAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
PP1V2_CPU
MAX_NECK_LENGTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
MAKE_BASE=TRUEVOLTAGE=1.2VMIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR
PP1V2_SOC =PPVDD_SOC_H4
MIN_LINE_WIDTH=0.6 MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
PP3V3_MLC_OUT
MIN_LINE_WIDTH=0.6 MMMAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUEVOLTAGE=20.4V
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 MM
PPLED_OUT
MAKE_BASE=TRUEPPVBUS_USB_DCIN
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
PP3V3_ACC
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.3VMAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
=PPVCC_MAIN_WL
=PP1V1_USB_H4=PP1V1_MIPI_PLL_H4
=BATT_POS_CONN
MAX_NECK_LENGTH=1.7 MM
MIN_NECK_WIDTH=0.15 MM
PPBATT_VCCVOLTAGE=4.2VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR
=PP3V3_USB_H4
=PP3V3_NAND_H4
=PP3V3_NAND
=PP3V3_MLC_HI
=PP1V8_S2R_WL
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=3.0VMAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PP3V0_IO=PP3V0_IO_MISC=PP3V0_IO_H4
=PP1V7_VA_VCPPP1V7_VA_VCP
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM
MAKE_BASE=TRUEVOLTAGE=1.7V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
GNDVOLTAGE=0VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=GNDMAX_NECK_LENGTH=5 MM
MIN_NECK_WIDTH=0.10MM
73 OF 106
A.0.0
051-8962
32 OF 42
34
23
7
34
34
34
19 20
28
5
34
7
7
8 9
4 5 7 10 13
19
27
26
5 28
8
8
4
8
14 16
16
9
8 34
11
28
27
31
34
34
34 35
35
34
16
7
7
4
18
18
17
17 18
26 27
11
11
28
5 26 27
34
34
34
34
34
31
34
34 9
36
35
34
34
30
4
4
33
34 37
4
10
12
36
30
34
13
7 9
19 34
BI
BI THERM
HDQ
POS
GND
A
A
A
A
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: GET RID OF THERES AFTER BRINGUP
NOTE:VERIFY PINOUT OF
APN:516-0240
BATTERY CONNECTORVERIFY MOUNTING CONN TO GND
MIN_NECK_MIDTH SHOULD BE 0.2MM
201
25V
33PF5%
NP0-C0G
10%16VX7R201
1000PF
SM
NP0-C0G
33PF
201
5%25V
0201-1
240-OHM-0.2A-0.8-OHM
201
0
MF1/20W5%
5 35
25VCERM0201
82PF5%
35
BATT-K93
CRITICAL
F-ST-SM
NOSTUFFTP-P55
TP-P55NOSTUFF
TP-P55NOSTUFF
TP-P55NOSTUFF
POWER: BATTERY CONNECTORSYNC_MASTER=YOSH SYNC_DATE=N/A
MIN_LINE_WIDTH=0.25 MMNET_SPACING_TYPE=ANLG
BATT_SNS
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=ANLG
BATTERY_NTC
BATTERY_SWI
=BATT_POS_CONN
BATT_SWI_CONN
NET_SPACING_TYPE=ANLG
BATT_NTC_CONN
C7522 1
2
C7524 1
2
XW7520
1 2
C7523 1
2
FL7500
1 2
R75411 2 C7525 1
2
J7500
1
2
3
4
5
6
7
8
TP75001
TP75011
TP75021
TP75031
75 OF 106
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051-8962
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34
32
S
D
G
CHG_B_LX
BUCK2_LXR
VBUS_B_OV_N
VDD_BUCK2
VDD_BUCK0
VDD_BUCK3
VDD_BUCK4
VCC_MAIN
VCC_MAIN_S
VDD_BUCK5_BYP
VDD_BUCK5
XTAL2
XTAL1
VDD_LDO11
VDD_LDO12
VDD_LDO9
VDD_LDO10
VDD_LDO4_7
VDD_LDO2
VDD_LDO3_5_8
VDD_LDO1_6
VBUS_B
VCENTER_B
VBUS_A_OV_N
VCENTER_A
VBUS_A
ACT_DIO
VBAT
CHG_A_LX
VBUCK4
DSP_SW
CPU1V2_SW
VBUCK3
CPU1V8_SW
WDIG_SW
VBUCK0_SW0_G
VBUCK0_SW0_S
VPUMP
VLDO1
VLDO3
VLDO2
VLDO5
VLDO4
VLDO6
VLDO7
VLDO8
VLDO9
VLDO10
VLDO11
VLDO12
ON_BUF
BUCK2_FB
BUCK3_LX
BUCK4_LXL
BUCK4_LXM
BUCK4_FB
BUCK5_LX
BUCK5_BYP
BUCK5_FB
BUCK0_FB
BUCK0_LXL
BUCK3_FB
IBAT
IBAT_S
BUCK2_LXL
BUCK2_LXM
BUCK0_LXM
(SYM 2 OF 3)
BUCK
USB/BAT
SWITCH POWER
LDO INPUT
XTAL
VCC-MAIN LDO
S
G
D
TP
TP
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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8 7 5 4 2 1
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
LAYOUT NOTE: PLACERIGHT AT THE PIN
LAYOUT NOTE: PLACERIGHT AT THE PIN
(RON=0.2 OHM MAX)
(RON=0.1 OHM MAX)
(150MA; 0.6-1.3V)
(200MA; 1.7-3.0V)
PP1V8: 6UF (NO DE-RATING)
ADDITIONAL DISTRIBUTED:
47UF (NO DE-RATING)ADDITIONAL DISTRIBUTED
ADDITIONAL DISTRIBUTED20UF (NO DE-RATING)
ADDITIONAL DISTRIBUTED14UF (NO DE-RATING)
30UF (NO DE-RATING)ADDITIONAL DISTRIBUTED
ADDITIONAL DISTRIBUTED25UF (NO DE-RATING)
RDSON=0.0136@VGS=-2.5V
DCR=64MOHM MAX
DCR=54MOHM MAX
(RON=0.5 OHM MAX)
(50MA; 1.5-3.3V)
(200MA; 2.5-3.55V)
(50MA; 2.5-3.3V)
(100MA; 1.8-3.3V)
(300MA; 2.5-3.6V)
(150MA; 2.5-3.55V)
(100MA; 1.65-1.805V; BUCK3)
LDO BYPASS
NOTE: 10V ZENER
ID=12.0A
27 MOHM @-4.5V
6.9 A
P-TYPE
+/- 25V
MOSFET
CHANNEL
RDS(ON)
VGS MAX
IMAX
FDMC6676BZ
(BYPASS RON=0.14 OHM MAX)
NOTE: FOR NO BATTERY SITUATION
(PLACE ONE 1UF CAP AT EACH VDD INPUT)
NOTE: CONCERNED ABOUT ESR > 20MOHM
PP1V2: 30UF (NO DE-RATING)
(RON=1 OHM MAX)
(300MA; 1.2-3.0V)
(10MA; 2.0-3.55V)
(150MA; 2.5-3.6V)
(DISTRIBUTED AND NO DE-RATING)
USB REVERSE VOLTAGE PROTECTION
TOTAL CAPS = ~400UFVCC_MAIN BYPASS
CRITICAL
603
10UF6.3VX5R
20% 5%18PF
NP0-C0G25V
201
82PF
0201
5%25VCERM
CRITICAL
CASE-B15G-SMPOLY-TANT
150UF-0.035OHM
6.3V20%
CRITICAL
X5R-CERM
22UF
603
6.3V20%
NOSTUFFSM
SMNOSTUFF
NOSTUFFSM
SMNOSTUFF
NOSTUFF
SHORT-0201
1/20W1%
MF
470K
NOSTUFF
201
CRITICAL
BZT52C10LPLLP
CRITICAL
FDMC6676BZMLP3.3X3.3
1%220K1/20W
MF201
D1946A0-110-00UFBGA
ALISON-A0-OTPXX
OMIT
2.2UH-3.5A-54M-OHM
CRITICAL
PIME061E-SM
CRITICAL
10%25V
2.2UF
X5R-CERM805
CRITICAL805
25V10%10UF
X5R
1UF10%
402CERM6.3V
NP0-C0G
18PF25V5%
201
25VNP0-C0G
18PF5%
201
2012
CRITICAL
32.768K-20PPM-12.5PF
NOSTUFFSM
PIME051E-SM
CRITICAL
2.2UH-20%-3.3A-0.064OHM
CRITICALPMEG4030ER
SOD-123W
603X5R-CERM
22UF
CRITICALNOSTUFF
6.3V20%
CRITICAL
22UF
X5R-CERM603
6.3V20%
1%0.5
MF402
1/16W
CRITICAL
402
4.7UF
X5R-CERM16.3V20%
CRITICAL
10%2.2UF
402
6.3VX5R
10%2.2UF
402
CRITICAL
6.3VX5R
CRITICAL
10UF
CERM-X5R0402
6.3V20%
CRITICAL
2.2UF10%
402
6.3VX5R
6.3VX5R
0201
0.22UF20%
CRITICAL
402
2.2UF10%
6.3VX5R
CRITICAL
402
4.7UF
X5R-CERM16.3V20%
CRITICAL
CERM
10%1UF
402
6.3V
CRITICAL
10%2.2UF
402
6.3VX5R
CRITICAL
10%2.2UF
402
6.3VX5R
CRITICAL
402
2.2UF10%
6.3VX5R
CERM
1UF10%
402
6.3V
CRITICAL
603X5R-CERM
22UF6.3V20%
CRITICAL
22UF
X5R-CERM603
6.3V20%
CRITICAL
22UF
X5R-CERM603
6.3V20%
CRITICAL603
22UF
X5R-CERM6.3V20%
CRITICAL603
22UF
X5R-CERM6.3V20%
CRITICAL603
10UF6.3VX5R
20%
CRITICAL
X5R-CERM
22UF
603
6.3V20%
CRITICAL
22UF
X5R-CERM603
6.3V20%
CRITICAL
X5R-CERM
22UF
603
6.3V20%
402CERM
1UF10%6.3V
1UF
CERM
10%
402
6.3V
0201
1UF6.3VX5R
20%1UF
CERM
10%
402
6.3V
10%
01005
0.01UF6.3VX5R
CRITICAL
MLP3.3X3.3FDMC6683
0201-MUR
1.0UF
CRITICAL
6.3VX5R
20%
402
CRITICAL
2.2UF10%
6.3VX5R
CRITICAL
X5R-CERM1
4.7UF
402
6.3V20%
CRITICAL
4.7UF
X5R-CERM1402
6.3V20%
CRITICAL
4.7UF
X5R-CERM1402
6.3V20%
CRITICAL
4.7UF
402X5R-CERM16.3V20%
CRITICAL
X5R-CERM1
4.7UF
402
6.3V20%
CRITICAL
X5R-CERM1
4.7UF
402
6.3V20%
CRITICAL
402X5R-CERM1
4.7UF6.3V20%
X5R-CERM1
4.7UF
402
CRITICAL
6.3V20%
NOSTUFFTP-P55
TP-P55NOSTUFF
PLACEMENT_NOTE=PLACE NEAR L8225.1
CRITICAL
POLY-TANT
150UF-0.035OHM
CASE-B15G-SM
6.3V20%
CRITICAL
2.2UH-20%-1.85A-80MOHM
PST25201B-SM
PST25201B-SM
CRITICAL
2.2UH-20%-1.85A-80MOHM
PST25201B-SM
CRITICAL
2.2UH-20%-1.85A-80MOHM
PST25201B-SM
CRITICAL
2.2UH-20%-1.85A-80MOHM
PST25201B-SM
2.2UH-20%-1.85A-80MOHM
CRITICAL
CRITICAL
PST25201B-SM
2.2UH-20%-1.85A-80MOHM
PST25201B-SM
CRITICAL
2.2UH-20%-1.85A-80MOHM
CRITICAL
2.2UH-20%-1.85A-80MOHM
PST25201B-SM
CRITICAL
603
10UF6.3VX5R
20%
IC,PMU,ALISON,D1946A2,OTPXX,UFBGA292343S0542 1 U8100 CRITICAL
SYNC_DATE=N/A
POWER: PMUSYNC_MASTER=YOSH
ALT FOUNDRYY8138197S0299197S0392
PP1V2_S2R
PPVCC_MAIN
PP1V1
PPVCC_MAINPP3V0_IO
DSP_SW
PP1V2
PP1V2_S2R
PP3V3_OUT
DIDT=TRUE
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
BUCK4_LXL
NET_SPACING_TYPE=SWITCHNODE
NET_SPACING_TYPE=ANLG
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM
BUCK3_FBDIDT=TRUENET_SPACING_TYPE=SWITCHNODEMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
BUCK3_LX
BUCK2_FB
MIN_LINE_WIDTH=0.25 MMNET_SPACING_TYPE=ANLG
MIN_NECK_WIDTH=0.20 MM
DIDT=TRUENET_SPACING_TYPE=SWITCHNODEMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
BUCK4_LXM
BUCK4_FBNET_SPACING_TYPE=ANLGMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
PP3V3_ACC
PP3V0_S2R_HALL
PP1V8_ALWAYS
PP1V2_S2R
PP1V8_S2R
BUCK2_LXR
DIDT=TRUENET_SPACING_TYPE=SWITCHNODE
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MM
PP1V2_SOC
NET_SPACING_TYPE=SWITCHNODE
MIN_LINE_WIDTH=0.6 MM
BUCK2_LXM
MIN_NECK_WIDTH=0.25 MM
DIDT=TRUE
BUCK2_LXL
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=SWITCHNODE
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
BUCK0_LXM
NET_SPACING_TYPE=SWITCHNODEDIDT=TRUE
PP1V2_CPUBUCK0_LXLMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=SWITCHNODEDIDT=TRUE
BUCK5_FBNET_SPACING_TYPE=ANLGMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
NET_SPACING_TYPE=ANLG
BUCK0_FB
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.6 MM
BUCK5_LX
MIN_NECK_WIDTH=0.25 MM
DIDT=TRUENET_SPACING_TYPE=SWITCHNODE
PP1V7_VA_VCP
BATT_SNS
PP2V85_CAM
NET_SPACING_TYPE=CRYSTAL
PMU_XTAL
PPVBUS_USB
PPBATT_VCC
PP3V0_OPTICAL
PP3V0_VIDEO_BUF
PP3V0_S2R_HALL
PP2V85_CAM
PP1V1
PP1V8_ALWAYS
NC_VBUS_A_OV_N
NC_VBUS_B_OV_N
VBUS_PROT_G
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.20MM
NET_SPACING_TYPE=ANLGMAX_NECK_LENGTH=3 MM
PPVBUS_USB_DCINNET_SPACING_TYPE=PWR
VOLTAGE=6V
PP3V0_IO
PP3V2_S2R_USBMUX
PP3V0_VIDEO_BUF
PP3V0_OPTICAL
PP3V2_SD
PP3V0_VIDEO
PP3V0_GRAPE
SW_CHGA
DIDT=TRUENET_SPACING_TYPE=SWITCHNODEMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=CRYSTALPMU_EXTAL
NC_CHGB
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MM
DIDT=TRUENET_SPACING_TYPE=SWITCHNODE
NET_SPACING_TYPE=ANLG
ACT_DIOMIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.1 MM
PPBATT_VCC
VOLTAGE=4.6V
MIN_NECK_WIDTH=0.20MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PMU_VPUMPMIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
VOLTAGE=4.6V
MIN_LINE_WIDTH=0.30MMBATT_POS_RC
PP3V3_ACC
PP1V8_S2R
PP3V2_S2R_USBMUX
PP3V2_SD
PMU_VCENTER
VOLTAGE=6VMAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.60MM
PP1V8
NC_PMU_VBUCK0_SW0_S
PP3V0_VIDEO
PP1V7_VA_VCP
PP3V0_GRAPE
NC_PMU_VBUCK0_SW0_G
PPVCC_MAIN
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.60MMPPVBUS_PROT
VOLTAGE=6V
MIN_NECK_WIDTH=0.25MMNET_SPACING_TYPE=PWR
PP1V8_S2R
PP1V8_GRAPE
C81551
2
C81541
2
C81641
2
C81631
2
C8165 1
2
C81021
2
XW81261 2
XW81031 2
XW81171 2
XW81131 2
XW8114
12
R81161
2
DZ8120
12
Q8123
5
4
123
R81301
2
U8100
P24
D9
A11
A9
D7
A7
B8
A6
A4
D16
A16
D14
A14
B11
H1
J1
J2
G4
F1
F2
G24
G25
H24
H25
A18
A20
B20
N17
P17
N18
P18
P25
M2
L25
B21
A21
A19
B17
A22
A23
B24
P22
P23
N22
N19
P19
N20
P20
G22
F24
F25
J24
J25
A10
B10
A3
B3
B7
B6
A17
A13
B13
E1
E2
G1
G2
H2
N6
L2
N7
K2
L4
N9
N4
N10
L1
P5
M1
P6
P3
P9
N5
P10
K1
P4
P8
P11
B18
B19
P1
P2
L8112
1 2
C8124 1
2 C81251
2
C81351
2
C81431
2
C8142 1
2
Y81381 2
XW81321 2
L8128
1 2
D8100
1
2
C8100 1
2
C8101 1
2
R81001
2
C8148 1
2
C8146 1
2
C8145 1
2
C8144 1
2
C8149 1
2
C8169 1
2
C8153 1
2
C8152 1
2
C8151 1
2
C8150 1
2
C8167 1
2
C8168 1
2
C81361
2
C81031
2
C81081
2
C81071
2
C81181
2
C81171
2
C81221
2
C81211
2
C81191
2
C81201
2
C81401
2
C81391
2
C81381
2
C81411
2
C8137 1
2
Q8104
5
4
1 2 3
C81311
2
C8147 1
2
C81561
2
C81571
2
C81581
2
C81591
2
C81601
2
C81611
2
C81621
2
C81301
2
TP81331
TP81011
C8166 1
2
L8100
1 2
L8101
1 2
L8105
1 2
L8107
1 2
L8110
1 2L8115
1 2
L8119
1 2
L8121
1 2
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32 34
32 34 35
32 34
32 34 35 32 34
32
32 34
32
32 34
32 34
32 34
32 34
32 34
32
32
32 34
33
32 34
4
32 34 37
32 34
32 34
32 34
32 34
32 34
32 34
32
32 34
32 34
32 34
32 34
32 34
32 34
32 34
32 34 37
32 34
32 34
32 34
32 34
32
32 34
32 34
32 34
32 34 35
32 34
VSS
VSS
VSS_BUCK2
VSSA_BUCK0
VSS_BUCK5
VSSA_BUCK3
VSSA_BUCK5
PVSS_CHG_A
PVSS_CHG_B
VSS_WLED
VSS_BUCK34
VSS_LCM
VSSA_BUCK2
VSSA_BUCK4
VSS_BUCK04
VSS_BUCK02
(SYM 3 OF 3)
WLED_LX
WLED6
WLED5
WLED4
WLED3
WLED1
WLED2
VOUT_LED
ACC_DET_B
ACC_DET_A
DWI_DO
DWI_CK
DWI_DI
SCL
SDA
SHDN
KEEPACT
TBAT
TDEV3
TDEV4
TDEV2
TDEV1
BRICK_ID
ACC_ID
IREF
VREF
FW_DET
BUTTON2
BUTTON1
BUTTON3
VDD_RTC
ADC_REF
GPIO2
GPIO3
GPIO1
GPIO5
GPIO4
GPIO6
GPIO7
GPIO8
GPIO10
GPIO9
GPIO11
GPIO13
GPIO12
GPIO14
GPIO16
GPIO15
AMUX_A0
AMUX_A1
AMUX_A3
AMUX_A2
AMUX_AY
AMUX_B0
AMUX_B1
AMUX_B3
AMUX_B2
AMUX_BY
VDD_LCM
VDD_LCM_SW
LCM_LX
VBOOST_LCM
LCM2_EN
VLCM2
VLCM1
VLCM3
VDD_REF
VDD_REF_A
ADC_IN7
GPIO17
GPIO18
TCAL
IRQ*
RESET*
RESET_IN
TEMPERATURE
DIGITAL INPUT
GPIO
REFERENCES
ANALOG
INPUT
RESET
WDOG
I2C & DWI
VIB
BACKLIGHT
LED
ANALOG MUX
LCM/GRAPE
(SYM 1 OF 3)
IN
IN
OUT
IN
BI
IN
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
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PAGE
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A
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345678
D
B
8 7 5 4 2 1
(INTERNAL PU TO PP1V8_S2R)
(INTERNAL PD; CAN’T BE USED FOR 32K CLK OUTPUT)
(2.5V ALWAYS ON PU IN BMU)
(INTERNAL PULL-DOWN)
(EXTERNAL PU)
(WHAT SIGNALS DO YOU WANT MEASURED?)
(NOTE: 2MHZ)
DCR=106MOHM MAX
(INTERNAL PULL-DOWN)
(INTERNAL PULL-DOWN)
(INTERNAL PULL-DOWN)
(INTERNAL PULL-DOWN)
(PULLUP INSIDE H4P)
(1.8_S2R;NO PD REQ’D PER BB TEAM)
(1.8_S2R;NO PD REQ’D PER BB TEAM)
(1.8_S2R PUSH-PULL)
(PU TO BATTERY IN BB)
(INTERNAL PD)
(INTERNAL PD)
(1.8_S2R;EXT PD BY BB MUXES)
(1.8 PUSH-PULL)
(1.8 PUSH-PULL)
PLACEMENT NOTE: PLACE NEAR PIN K4
PLACEMENT NOTE: PLACE NEAR PIN H22
(INTERNAL PULLDOWN; TE ENABLE)
RESISTOR FOR TEMP CALIBRATION
PLACE CLOSE TO PMU
PLACE CLOSE TO PMU
PLACE CLOSE TO PMU
PLACE CLOSE TO PMU
I2C ADDRESS: 0111100X (0X78)
(BETWEEN WLED AND CHARGER)
(H4P)
(DOCK CONN)
(PANEL)
DWI NAMING RELATIVE TO AP
NOTE: TDEV4 NTC ON PANEL
PLACE CLOSE TO PMU
OMIT
UFBGA
ALISON-A0-OTPXXD1946A0-110-00
OMIT
UFBGA
ALISON-A0-OTPXXD1946A0-110-00
X5R6.3V
0.01UF10%
01005
X5R6.3V
0.01UF10%
01005
CRITICAL
0.1%
1/16WMF
402
3.92K
6.3VCERM01005
5%100PF
X5R
10%1UF25V
402
201
1%
1.00
1/20WMF
201
1%
MF
1.00
1/20W
201
1%
MF1/20W
1.00 201MF
1/20W
1.00
1%
201
1.00
1/20WMF
1%
201
1.00
1/20WMF
1%
20%
CRITICAL
X5R-CERM
22UF
25V
0805
201
1/20W
200K1%
MF
6.3V
402CERM
1UF10%
201X5R6.3V
0.1UF10%
X5R6.3V
1000PF
01005
10%
201X5R6.3V
0.1UF10%
CRITICAL
SOD882
PMEG2005AEL
5 39
5 39
5 39
5 10 19 39
5 10 19 39
5
4 28 31
4
28
13 28
4
5 29
5 25
5 25
16
16
16
16
16
16
28
19
11
31
30
30
30 39
18 39
31
30
30
5 33
33
31 39
20%
X5R603
10V
10UF20%
2.2UF
X5R-CERM10V
402
6.3VCERM402
1UF10%
31
CRITICAL
PIME051E-SM
4.7UH-3.2A PMEG4010BEA
CRITICAL
SOD-323
20%
X5R603
10UF10V
CRITICAL
10KOHM-1%0201
CRITICAL
10KOHM-1%0201
CRITICAL
10KOHM-1%0201
6.3V
01005CERM
100PF5%
6.3VCERM
100PF5%
01005 6.3VCERM
100PF5%
01005 6.3VCERM
100PF5%
01005
37
201
1/20W1%
MF
220K
5
X5R402
10%1UF25V
PLACEMENT_NOTE=PLACE NEAR U8100.N23
20%0.22UF
0201X5R6.3V
CRITICAL
2.2UH-1.05A-0.195OHM
VLS201612E-SM
19
SMNOSTUFF
NOSTUFFSM
NOSTUFFSM
NOSTUFFSM
25
X5R
10%1UF25V
402X5R402
25V
1UF10%
31
SYNC_DATE=N/ASYNC_MASTER=YOSH
POWER: PMU
NC_VLCM2
NET_SPACING_TYPE=ANLGBOARD_TEMP2
SRL_L
PORT_DOCK_ACC_DET_L
USB_BRICKID
BOARD_TEMP4_N
BOARD_TEMP4 NET_SPACING_TYPE=ANLG
BOARD_TEMP1_N
BOARD_TEMP3_N
BOARD_TEMP2_N
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
LED_IO6_R
LED_IO_6MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
LED_IO5_R
LED_IO_5MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
LED_IO4_R
LED_IO_4MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
LED_IO2_R
LED_IO_2MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
LED_IO3_R
LED_IO_3MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
LED_IO1_R
LED_IO_1MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
RST_L63_L
DOCK_BB_EN
MIN_LINE_WIDTH=0.4MM
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUEVOLTAGE=5V
PP6V0_LCM_HI
LCM_LX
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM
DIDT=TRUENET_SPACING_TYPE=SWITCHNODE
IRQ_PMU_L
RST_AP_L
RST_PMU_IN
PPVCC_MAIN
PMU_ACC_DET_B
DWI_AP_CLK
DWI_AP_DO
DWI_AP_DI
I2C0_SCL_1V8
I2C0_SDA_1V8
BATTERY_NTC
NET_SPACING_TYPE=ANLG
PMU_SHDWN
PM_KEEPACT
NET_SPACING_TYPE=ANLGPMU_TCALAUD_MIK_HS1_INT_L
CLK_32K_GPS
PM_BT_HOST_WAKE
BATTERY_SWI
RST_BB_PMU_L
RST_WLAN_L
BB_VBUS_DET
VOLTAGE=6V
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
PP6V0_LCM_VBOOST
PPVCC_MAIN
PORT_DOCK_ACCID
ONOFF_L
HOME_L
FW_ZENER_PWR
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.1MMNET_SPACING_TYPE=ANLG
PMU_ADC_REF
NET_SPACING_TYPE=ANLGBOARD_TEMP1
NET_SPACING_TYPE=ANLGBOARD_TEMP3
WLED_LXNET_SPACING_TYPE=SWITCHNODEDIDT=TRUEMIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 MM
=PPVCC_MAIN_LED
NC_LCM2_EN
NC_VLCM1
NC_PMU_AMUX_A0
NC_PMU_GPIO18
NC_PMU_GPIO16
NC_PMU_GPIO17
NC_PMU_AMUX_B1
NC_PMU_AMUX_B2
NC_PMU_AMUX_B3
NC_PMU_AMUX_BY
NC_PMU_AMUX_B0
NC_PMU_AMUX_AY
NC_PMU_AMUX_A3
NC_PMU_AMUX_A2
NC_PMU_AMUX_A1
NC_PMU_GPIO13
IRQ_HALL
PPLED_OUT
PM_BB_HOST_WAKE
PM_WLAN_HOST_WAKE
NET_SPACING_TYPE=ANLGPMU_VDD_RTC
NET_SPACING_TYPE=ANLGPMU_VDD_REFNET_SPACING_TYPE=ANLGPMU_VREF
PMU_IREFNET_SPACING_TYPE=ANLG
CLK_32K_PMU
CLK_32K_WLAN
RST_BT_LADC_IN7
U8100
E22
J22
B2
B4
E5
K17
K18
L5
L6
L7
L8
L9
N3
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
F4
F5
F6
F7
F8
C2
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
D4
F19
G5
G6
G7
G8
G9
G10
G11
G12
G13
D5
G14
G15
G16
G17
G18
G19
H4
H5
H6
H7
D6
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
K5
K6
E4
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
A8
B9
A12
B12
A5
B5
A15
B15
D1
D2
N16
N14
P14
D10
D8
B16
B14
C1
U8100
A2
A1
K24
K25
N8
E24
E25
G21
D25
G20
H21
H20
J20
J21
K19
K22
L15
L16
L17
F21
D22
E21
F22
D11
D21
B22
B23
L18
L19
L20
K20
K21
L21
D12
D13
D18
D19
D20
D15
D17
E20
N2
B25
C24
C25
P16
D24
F20
A25
A24
B1
N24
N25
M25
M24
L22
L24
N12
N21
P21
H22
K4
P7
P12
N11
L10
N23
N1
L11
L12
N13
P13
L13
L14
N15
P15
C82071
2
C82061
2
R8219
1
2
C8220 1
2
C82341
2
R82271 2
R82311 2
R82351 2
R82321 2
R82391 2
R82401 2
C82331
2
R82031
2
C82091
2
C82041
2
C82141
2
C82121
2
D8230
1 2
C82371
2
C8236 1
2
C82381
2
L8225
1 2
D8228
1 2
C8226 1
2
R8218
1
2
R8222
1
2
R8216
1
2C8215 1
2
C8221 1
2
C8217 1
2
C8223 1
2
R82021
2
C8201 1
2
C82101
2
L8229
1 2
XW82031 2
XW82021 2
XW82011 2
XW82001 2
C82351
2
C82321
2
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16
32 34 35
32 34 35
28
32
32
D
G S
IN
S
G
D
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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PAGE
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A
B
C
345678
D
B
8 7 5 4 2 1
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
VGS MAX
4 A
52MOHM @-1.8V
P-TYPE
CSD68803W15
CSD68803MOSFET
+/- 6V
POWER BUDGET
PEAK=0.12A
AVG=0.12A
K48
RDS(ON)
CHANNEL
IMAX
10%1000PF
X7R16V
201
SOD-VESM-HFSSM3K15FV
MF
100K
201
1/20W1%
6
BGACSD68803W15
CRITICAL
201
5%
MF1/20W
0
603
6.3VX5R-CERM
4.7UF10%
0201
6.3VX5R
10%
0.015UF201
39K1/20WMF
1%
201
47K
MF1/20W1%
NOSTUFF
10K
201
1/20WMF
1%
RADAR:8537160376S0972 376S0612 Q8351
POWER: 3.3V MLC & 1.2V VRSYNC_DATE=N/ASYNC_MASTER=YOSH
PM_MLC_PWR_EN
PM_P3V3MLC_EN
PP3V3_MLC_OUT=PP3V3_MLC_HI
PM_P3V3MLCWR_SSR8354_SS
C83531
2
C83521
2
C8351
1 2
R83531
2R83521 2
R83511
2
Q8351
3
12
R83501
2
Q8350
A2
B1
B2
C1
A1
A3
B3
C2
C3
R83541 2
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OUTOUT
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THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DEBUG RESET ACCESS
PLACE OUTSIDE OF CAN?
LEFT AND RIGHT MOUNTING TABS
5%1/20WMF201
300
NOSTUFF
3005%1/20WMF201
NOSTUFF
0603RED-50MCD-20MA
NOSTUFF
1%1/20WMF201
1.5K
NOSTUFF
35 5
SMBRKT-MTG-TAB-MLB-K93K94
DEBUG AND MISCSYNC_MASTER=MIKE SYNC_DATE=N/A
PWR_ON_LED
PPBATT_VCC
FORCE_DFUPMU_SHDWN
R90001
2
R90011
2
LED9000A
K
R90021
2
MT1
1 2
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THE INFORMATION CONTAINED HEREIN IS THE
36
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DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PLATING SIZE: 1.4MM X 0.7MMDRILL SIZE: 1.1MM X 0.4MM
PLATED THROUGH HOLES
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
TH-NSP
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
TH-NSP
FCT/ICT TEST/BRACKETSSYNC_DATE=N/ASYNC_MASTER=MIKE
SL93001
SL93061
SL93051
SL93041
SL93031
SL93021
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36
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IV ALL RIGHTS RESERVED
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C
345678
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8 7 5 4 2 1
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
SPACING
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
I2C
NAND
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
Clock Signal Constraints
SPACING
NET_TYPE
PHYSICAL
USB
SPACING
XTAL
SPACING
ELECTRICAL_CONSTRAINT_SET PHYSICAL
DWI
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL SPACING
SPACINGPHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
JTAG
I2S
NET_TYPE
SPACINGELECTRICAL_CONSTRAINT_SET
PHYSICAL SPACING
NET_TYPE
VREF
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
SPACING
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
I1
I100
I101
I102
I103
I104
I105
I106
I107
I108
I109
I110
I111
I112
I113
I114
I115
I116
I117
I118
I119
I120
I121
I122
I123
I124
I125
I128
I129
I13
I130
I131
I136
I137
I138
I139
I14
I140
I141
I142
I143
I144
I145
I146
I147
I148
I149
I15
I150
I151
I152
I153
I156
I157
I158
I159
I16
I160
I161
I162
I163
I164
I165
I166
I167
I168
I169
I170
I171
I172
I2
I20
I3
I37
I4
I41
I42
I43
I44
I45
I46
I47
I48
I49
I5
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
I6
I61
I62
I63
I7
I8
I81
I82
I83
I84
I85
I88
I89
I90
I92
I93
I94
I95
I96
I98
I99
SYNC_DATE=N/ASYNC_MASTER=MIKE
CONSTRAINTS: ASSIGNMENTS
DWI 2:1_SPACING**
* 5:1_SPACING*USB
2:1_SPACINGI2S *I2S
3:1_SPACING*I2S *
5:1_SPACING* *CRYSTAL
5:1_SPACINGVREF * *
* 50_OHM_SENAND_50S
2:1_SPACING*NAND *
50_OHM_SEI2C_50S *
50_OHM_SECLK_50S *
5:1_SPACINGCLK * *
90_OHM_DIFF*USB_90D
45_OHM_SEI2S_90S *
1.5:1_SPACINGI2C **
JTAG * * 2:1_SPACING
USBUSB_90D ACC_PT_DK_CON_RX
USBUSB_90D USB_FS_P_ACC_RXUSBUSB_90D USB_FS_N_ACC_TX
USBUSB_90D ACC_PT_DK_CON_TX
USB_90D USB_FS_D_NUSB
USB_90D USB USB_D_N
USB_BB_D_NUSBUSB_90D
I2S I2S_AP_0_BCLKI2S_50S
I2S I2S_AP_0_DINI2S_50S
I2S_50S I2S L63_ASP_SDOUTI2S_50S I2S I2S_AP_0_DOUT
I2SI2S_50S I2S_AP_0_LRCK
I2S_50S I2S_AP_2_DOUTI2S
I2S_50S I2S L63_VSP_SDOUT
I2S_AP_3_LRCKI2SI2S_50S
I2C_50S I2C ISP_CAM_1_SCLI2C_50S ISP_CAM_1_SDAI2C
NANDNAND_50S F2WP_L
F3WP_LNANDNAND_50S
F3ALENANDNAND_50S
F3CE2_LNANDNAND_50S
F3AD<7..0>NANDNAND_50S
F2WE_LNAND_50S NAND
F2RE_LNANDNAND_50S
F2ALENANDNAND_50S
F2CLENANDNAND_50S
F2CE3_LNANDNAND_50S
F2CE2_LNANDNAND_50S
F2CE1_LNANDNAND_50S
F2CE0_LNANDNAND_50S
F2AD<7..0>NANDNAND_50S
NAND_50S NAND F1WP_L
NAND_50S NAND F1RE_LNAND_50S NAND F1WE_L
NAND_50S NAND F1CLENAND_50S NAND F1ALE
F1CE5_LNAND_50S NANDF1CE6_LNAND_50S NANDF1CE7_LNAND_50S NAND
F1CE4_LNAND_50S NAND
F1CE2_LNANDNAND_50S
F1CE0_LNANDNAND_50SF1CE1_LNANDNAND_50S
F1CE3_LNANDNAND_50S
NAND_50S NAND F0WP_LNANDNAND_50S F1AD<7..0>
F0RE_LNAND_50S NAND
NAND_50S NAND F0ALE
NAND_50S NAND F0WE_L
NAND_50S NAND F0CLE
F0CE4_LNANDNAND_50SF0CE5_LNAND_50S NANDF0CE6_LNAND_50S NANDF0CE7_LNAND_50S NAND
NAND_50S F0CE0_LNANDF0CE1_LNANDNAND_50SF0CE2_LNANDNAND_50SF0CE3_LNANDNAND_50S
F3WE_LNANDNAND_50S
F3RE_LNANDNAND_50S
F3CLENANDNAND_50S
F3CE3_LNANDNAND_50S
NANDNAND_50S F3CE1_LF3CE0_LNANDNAND_50S
I2C2_SCL_3V0I2CI2C_50S
I2C0_SDA_1V8I2C_50S I2C
I2C I2C1_SCL_1V8I2C_50S
I2S_50S I2S L63_XSP_SDOUT
I2SI2S_50S I2S_AP_2_BCLK
I2SI2S_50S I2S_AP_2_DIN
I2S I2S_AP_3_BCLKI2S_50S
I2S I2S_AP_3_DOUTI2S_50S
I2SI2S_50S I2S_AP_2_LRCK
PPVREF_DDR1_DQVREF
NAND F0AD<7..0>NAND_50S
CLK_32K_PMUCLKCLK_50S
I2C_50S I2C0_SCL_1V8I2C
ISP_AP_1_SDAI2C_50S I2CI2C2_SCL_3V0_ALSI2C_50S I2C
USBUSB_90D USB_PT_DK_CON_D_N
USB_90D USB_BB_D_PUSB
USB_90D USB_FS_D_PUSB
CRYSTAL XTAL_24M_O
DWI_AP_CLKDWI
DWI_AP_DODWI
I2SI2S_50S I2S_AP_3_DIN
DWI_AP_DIDWI
JTAG_AP_TDIJTAG
JTAG_AP_TRST_LJTAG
JTAG_AP_TCKJTAGJTAG_AP_TMSJTAG
JTAG_AP_TDOJTAGUSB_90D USB_PT_DK_CON_D_PUSB
USB_90D USB USB_D_P
PPVREF_DDR1_CAVREF
PPVREF_DDR0_CAVREFPPVREF_DDR0_DQVREF
24M_OCRYSTAL
XTAL_24M_ICRYSTAL
I2C2_SDA_3V0_ALSI2C_50S I2C
I2C2_SDA_3V0I2C_50S I2C
ISP_AP_1_SCLI2C_50S I2C
ISP_AP_0_SDAI2C_50S I2C
I2C I2C1_SDA_1V8I2C_50S
ISP_AP_0_SCLI2CI2C_50S
CLK_CAM_RF_RCLKCLK_50S
CLK CLK_CAM_RFCLK_50S
CLK_50S CLK_CAM_FF_CONNCLK
CLK_50S CLK_CAM_FF_FILTCLK
CLK CLK_CAM_FFCLK_50S
CLK_50S CLK_32K_GPSCLK
CLK_32K_WLANCLKCLK_50S
CLK_CAM_RF_FILTCLK_50S CLK
I2S_AP_0_MCKCLKCLK_50SI2S_AP_0_MCK_RCLK_50S CLKCLK_CAM_FF_RCLKCLK_50S
100 OF 106
A.0.0
051-8962
39 OF 42
28 29
11 28
11 28
28 29
4 11
4 28
11 31
5 19
5 19
19
5 19
5 19
5 19 30
19
5 19
25 26
25 26
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
6 12
5 25 26
5 10 19 35
5 25
19
5 19 30
5 19 30
5 19
5 19
5 19 30
8
6 12
18 35
5 10 19 35
7 26
25 26
28 29
11 31
4 11
4
5 35
5 35
5 19
5 35
4 10
4 10
4 28
4 28
4 10 28 29
4 28
8
8
8
4
4
25 26
5 25 26
7 26
7 25
5 25
7 25
7
7 27
25 26
7 26
31 35
30 35
25 27
5
5 19
7
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PHYSICALELECTRICAL_CONSTRAINT_SET
ANALOG VIDEO CONSTRAINTSAUDIO/SPEAKER
PHYSICAL
NET_TYPE
SPACING
MIPI
SPACINGPHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SPACING
NET_TYPE
SPACING
NET_TYPE
PHYSICALELECTRICAL_CONSTRAINT_SET
LVDS
DISPLAYPORT
PHYSICALELECTRICAL_CONSTRAINT_SET
PHYSICAL SPACING
NET_TYPE
NET_TYPE
SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
SDIO
SPI
SPACINGELECTRICAL_CONSTRAINT_SET
NET_TYPE
I174
I175
I176
I178
I200
I201
I202
I213
I214
I215
I219
I220
I221
I222
I223
I224
I231
I232
I233
I234
I235
I244
I245
I247
I248
I249
I250
I251
I252
I270
I271
I272
I273
I274
I275
I276
I277
I280
I287
I288
I289
I290
I291
I292
I293
I294
I311
I312
I315
I316
I327
I328
I329
I330
I331
I332
I341
I342
I343
I344
I345
I346
I347
I348
I353
I354
I355
I356
I357
I359
I360
I361
I362
I363
I364
I365
I366
I367
I371
I372
I91
I92
I93
I94
I95
I96
I97
I98
* 4:1_SPACINGMIPI *
**DP 5:1_SPACING
=50_OHM_SE* Y =STANDARD=50_OHM_SEVID_50S =STANDARD=50_OHM_SE
* 90_OHM_DIFFMIPI_100D
**ANALOG_VIDEO 5:1_SPACING
ANALOG_VIDEO *ANALOG_VIDEO 3:1_SPACING
* 90_OHM_DIFFLVDS_100D
**LVDS 4:1_SPACING
*DP_100D 90_OHM_DIFF
SDIO_CLK 4:1_SPACING* *
* 2:1_SPACING*SPI
*SPI_50S 45_OHM_SE
* 2:1_SPACING*SDIO
50_OHM_SESDIO_50S *
AUDIO 3:1_SPACING* *
SPEAKER * SPEAKER
AUDIO * 1:1_DIFFPAIR
CONSTRAINTS: ASSIGNMENTSSYNC_MASTER=MIKE SYNC_DATE=N/A
MIPI_100D MIPI MIPI0C_CAM_CLK_NMIPI_100D MIPI MIPI0C_CAM_CLK_PMIPI_100D MIPI MIPI0C_CAM_DATA_N<0>MIPI_100D MIPI MIPI0C_CAM_DATA_P<0>
MIPIMIPI_100D MIPI0C_AP_CLK_N
MIPIMIPI_100D MIPI0C_AP_DATA_N<0>MIPI_100D MIPI MIPI0C_AP_DATA_P<0>
MIPIMIPI_100D MIPID_AP_CLK_NMIPI MIPID_AP_CLK_PMIPI_100D
MIPIMIPI_100D MIPID_AP_DATA_P<2>MIPI_100D MIPI MIPID_AP_DATA_N<1>MIPI_100D MIPI MIPID_AP_DATA_P<1>
MIPI MIPID_AP_DATA_N<0>MIPI_100D
MIPI MIPID_AP_DATA_P<0>MIPI_100D
DP_100D DP DP_PT_DK_CON_TX_N<1>DP_100D DP DP_PT_DK_CON_TX_P<1>
DP_100D DP DP_EMI_AUX_P
DP_100D DP DP_EMI_TX_N<0>
DP DP_AP_TX_N<1>DP_100D
DP_100D DP DP_AP_TX_P<1>
LVDS LVDS_DATA_CONN_P<2..0>LVDS_100D
MIPIMIPI_100D MIPID_AP_DATA_N<2>MIPI MIPID_AP_DATA_P<3>MIPI_100D
MIPI_100D MIPID_AP_DATA_N<3>MIPI
BUF_C_YANALOG_VIDEOVID_50S
DAC_AP_OUT3ANALOG_VIDEOVID_50S
DAC_AP_OUT2ANALOG_VIDEOVID_50S
VIDEO_EMI_C_YANALOG_VIDEOVID_50S
VIDEO_EMI_CVBS_PBANALOG_VIDEOVID_50S
BUF_Y_PRANALOG_VIDEOVID_50S
BUF_CVBS_PBANALOG_VIDEOVID_50S
VID_50S ANALOG_VIDEO VIDEO_EMI_Y_PR
VID_50S VIDEO_PT_DK_CON_C_YANALOG_VIDEO
VID_50S VIDEO_PT_DK_CON_Y_PRANALOG_VIDEO
LVDS LVDS_DATA_P<2..0>LVDS_100D
LVDS LVDS_DATA_N<2..0>LVDS_100D
LVDS LVDS_DATA_CONN_N<2..0>LVDS_100D
LVDS LVDS_CLK_PLVDS_100D
LVDS LVDS_CLK_NLVDS_100D
LVDS_100D LVDS LVDS_CLK_CONN_PLVDS_100D LVDS LVDS_CLK_CONN_N
DP_100D DP DP_AP_TX_P<0>DP DP_AP_TX_N<0>DP_100D
DP DP_AP_AUX_PDP_100D
DP_100D DP DP_EMI_TX_P<1>DP_100D DP_EMI_TX_N<1>DP
DP_100D DP DP_EMI_AUX_NDP_100D DP DP_PT_DK_CON_TX_P<0>
DP_100D DP_PT_DK_CON_AUX_PDP
DP_100D DP DP_PT_DK_CON_AUX_N
DAC_AP_OUT1ANALOG_VIDEOVID_50S
VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_CVBS_PB
DP_100D DP DP_EMI_TX_P<0>
DP_100D DP DP_PT_DK_CON_TX_N<0>
MIPIMIPI_100D MIPI0C_AP_CLK_P
MIPI1C_AP_DATA_P<0>MIPIMIPI_100DMIPI1C_AP_DATA_N<0>MIPIMIPI_100DMIPI1C_AP_CLK_PMIPIMIPI_100DMIPI1C_AP_CLK_NMIPIMIPI_100D
MIPI_100D MIPI MIPI1C_CAM_CLK_NMIPI_100D MIPI MIPI1C_CAM_CLK_P
MIPI_100D MIPI MIPI1C_CAM_DATA_P<0>MIPI_100D MIPI MIPI1C_CAM_DATA_N<0>
DP_100D DP DP_AP_AUX_N
SDIO_50S SDIO_CLK SDIO_WL_CLK
SDIO_50S SDIO SDIO_WL_CMDSDIO_50S SDIO SDIO_WL_DATA<3..0>
SPI_GRAPE_CS_LSPI_50S SPI
SPI_GRAPE_SCLKSPI_50S SPI
SPI_50S SPI SPI_GRAPE_MISO
SPI_GRAPE_MOSISPI_50S SPI
SPI_50S SPI SPI_IPC_MISO
SPI_50S SPI SPI_IPC_MOSI
SPI_50S SPI SPI_IPC_SCLK
SPI_50S SPI SPI_IPC_MRDY
AUDIOAUDIO RIGHT_CH_OUT_REFAUDIO RIGHT_CH_PAUDIO
AUDIOAUDIO SSM2375_R_IN_N
AUDIOAUDIO EXT_MIC_REF
AUDIO RIGHT_CH_OUT_PAUDIO
AUDIO SSM2375_L_IN_NAUDIO
AUDIO SSM2375_L_IN_PAUDIO
LEFT_CH_PAUDIO AUDIO
AUDIO AUDIO SSM2375_R_IN_P
LEFT_CH_OUT_PAUDIOAUDIO
AUDIOAUDIO LEFT_CH_OUT_REF
AUDIO AUDIO EXT_MIC_P
SDIO_50S SDIO_CLK SDIO_WL_CLK_R
101 OF 106
A.0.0
051-8962
40 OF 42
25 27
25 27
25 27
25 27
7 27
7 27
7 27
7 14
7 14
7 14
7 14
7 14
7 14
7 14
28 29
28 29
13 28
13 28
7 10 13
7 10 13
16
7 14
7 14
7 14
11
7 11
7 11
10 11 28
10 11 28
11
11
10 11 28
28 29
28 29
14 16
14 16
16
14 16
14 16
16
16
7 10 13
7 10 13
7 13
13 28
13 28
13 28
28 29
28 29
28 29
7 11
28 29
13 28
28 29
7 27
7 26
7 26
7 26
7 26
25 26
25 26
25 26
25 26
7 13
5 30
5 30
5 30
5 17
5 17
5 17
5 17
5 31
5 31
5 31
5 31
19 20
20
20
19 23
19 20
20
20
20
20
19 20
19 20
19 23
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_BOARD_INFO
VERSIONALLEGRO
(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
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II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
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BGA AREA PHYSICAL RULES
90 OHMS
100 OHMSDIFFERENTIAL PAIR PHYSICAL RULES
0.114 MM ~ 4.5 MIL
0.125 MM ~ 5 MIL
0.140 MM ~ 5.5 MIL
0.15 MM ~ 6 MIL
0.18 MM ~ 7 MIL
0.3 MM ~ 12 MIL
MLB CONSTRAINTS
45 OHMS
50 OHMS
DEFAULT/BGA SPACING RULES
REGULAR SPACING RULES
NOTES:
0.075 MM ~ 3 MIL
0.089 MM ~ 3.5 MIL
0.102 MM ~ 4 MIL
0.25 MM ~ 10 MIL
1.0 MM = 39.37 MIL
0.2 MM ~ 8 MIL
0.4 MM ~ 16 MIL
0.33 MM ~ 13 MIL
*NOTE: ASSUMING 0.060MM DIELECTRIC THICKNESS
POWER/GND SPACING RULES
PHYSICAL CONSTRAINTS SPACING CONSTRAINTS
SINGLE-ENDED PHYSICAL RULES
50 OHMS - CLEAR ON TOP AND BOTTOM
50 OHMS - CLEAR ON LAYER 2 AND 5
AUDIO PHYSICAL RULES
Y 0.060 MMBGA_PHY 0.075 MM* 0.060 MM =STANDARD 0.076 MM
BGA_PHYBGA*
NO_TYPE,BGA,BGA06-06TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM 15.2MM
DEFAULT =45_OHM_SE* Y 0 MM 0 MM30 MM=45_OHM_SE
BGA* BGA_SPA*
BGA_SPA* BGACLK
**SWITCHNODE SWITCHNODE
GND_P1SPACINGGND **
PWR_P1SPACING* *PWR
0.08 MMDEFAULT * ?
=DEFAULTSTANDARD * ?
=DEFAULT*BGA_SPA ?
*1:1_SPACING ?0.060 MM
0.090 MM1.5:1_SPACING ?*
2:1_SPACING ?0.120 MM*
?0.150 MM2.5:1_SPACING *
?3:1_SPACING * 0.180 MM
0.240 MM4:1_SPACING ?*
?*5:1_SPACING 0.300 MM
0.5 MM ?*0P5MM_SPACING
* ?0.64 MM0P64MM_SPACING
* 900PWR_P1SPACING 0.1 MM
* 0.5 MM 1000SWITCHNODE
TOP,BOTTOM 0.2 MMSWITCHNODE 1000
GND_P1SPACING 9500.1 MM*
=DEFAULT=DEFAULTYSTANDARD =DEFAULT* =DEFAULT 12.7 MM
3:1_SPACING* *ANLG
0P08_SPACING * ?0.080 MM
3.0 MM50_OHM_SE YTOP,BOTTOM 0.085 MM 0.085 MM
SYNC_DATE=N/ASYNC_MASTER=MIKE
CONSTRAINTS: MLB RULES
45_OHM_SE Y 3.0 MMISL2,ISL3,ISL8,ISL9 0.055 MM 0.055 MM
0.060 MM45_OHM_SE Y 3.0 MM0.060 MMISL4,ISL5,ISL6,ISL7
0.060 MMN*45_OHM_SE 3.0 MM0.060 MM
0.050 MM50_OHM_SE * N 3.0 MM0.050 MM
50_OHM_SE_RF Y 3.0 MM0.240 MM 0.240 MMTOP
0.060 MM0.060 MMISL4 3.0 MM50_OHM_SE Y
50_OHM_SE Y 3.0 MM0.090 MM 0.090 MMISL2,ISL9
SPEAKER Y* 0.08 MM0.3 MM 0.19MM 10 MM 0.08 MM
100_OHM_DIFF YTOP,BOTTOM 0.076 MM 0.210 MM0.076 MM 0.210 MM
0.300 MM0.057 MM 0.300 MMY 0.057 MM =STANDARDN100_OHM_DIFF
Y 0.095 MM 0.200 MM 0.200 MM0.095 MMTOP,BOTTOM90_OHM_DIFF
0.200 MMY =STANDARD 0.100 MM0.054 MM 0.054 MM90_OHM_DIFF ISL2,ISL3,ISL8,ISL9
0.100 MM=STANDARDY 0.200 MM0.060 MM 0.060 MM90_OHM_DIFF ISL4,ISL5,ISL6,ISL7
=STANDARDY1:1_DIFFPAIR 0.08 MM* =STANDARD =STANDARD 0.08 MM
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THE INFORMATION CONTAINED HEREIN IS THE
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DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
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NOTICE OF PROPRIETARY PROPERTY:
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345678
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CONSTRAINTS: RF RULESSYNC_DATE=N/ASYNC_MASTER=MIKE
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