Io School of Microelectronic Engineering Lecture 1 Introduction to IC Fabrication.
Transcript of Io School of Microelectronic Engineering Lecture 1 Introduction to IC Fabrication.
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What is Semiconductor Process Technology? The technology to produce IC microchips
IC chips are the backbone of the computer industry and have spurred related technologies such as software and internet
Every product of the information age is an offspring of IC technology
IC chips increasingly control functions in cars, TVs, VCRs, cameras, mobile phones, toys, etc.
The current technology is as a result of years of research and development, taken many thousands of scientists, engineers and technicians.
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First Transistor, Bell Lab 1947
John Bardeen and Walter Brattain, demonstrateda solid state device made from germanium. Theyobserved that when electrical signals were appliedto contacts on germanium, the output power waslarger than the input. These results were publishedIn 1948.
William Shockley, found out how the bipolar transistorfunctioned and published the theory in 1949.
Three of them shared the Nobel Prize in physics in1956,
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Semiconductor industry developed rapidly and germanium based transistor quickly replaced vacuum tubes in electronics equipment due to:
smaller size lower power consumption lower operating temperature quicker response time
Single crystal silicon and germanium based devices introduced in 1950 and 1952 respectively (better defect control, hence higher yield).
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Shockley left Bell Labs in 1956, to start his own lab in San Francisco Bay, California. Nowadays known as Silicon Valley. His lab has attracted talented scientist such as Robert Noyce and Gordon Moore.
Gordon Moore and Robert Noyce left Shockley in 1957 to start Fairchild Semiconductor.
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First IC Device by Jack Kilby, Texas Instruments 1958
1st fabricated by Bell Labs in 1958. Jack Kilby demonstrated functional IC, fabricated on germanium strip consists of;
one transistor one capacitor 3 resistors
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First Silicon IC Chip by Robert Noyce, Fairchild Camera, 1961
Fairchild Semiconductor produced the 1st commercialICs in 1961. This IC consists of only 4 transistors sold for USD 150 a piece.
NASA was the main customer.
In 1968, Robert Noyce cofounded Intel Corp. withAndrew Groove and Gordon Moore.
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Limit of IC SizeIs there a limit for the minimum feature size?
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IC Manufacturing
A very complicated process, involves; Circuit design Manufacturing material Clean room technology, processing, equipment Wafer processing technology Die testing Chip packaging and final test
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IC Manufacturing Flow
Design
Mask info to MASK-SHOP + GDSII file
Mask making
Generate runcard
Wafer Preparation
Front-end Processes (individual transistor)
Deposition
Oxidation
Diffusion
Photolithography
Etch (wet and dry)
Implantation
Backend Process Deposition (oxide, nitride etc) Metalization Rapid Thermal Process Lithography & Etch
Test (Parametric and Functional) Packaging Final Test
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Architectural Design – Defines the application operating system and devides modules for system.
SDA
GND A2 A0A1
SCL WP VCC
Charge Pump
16K-bits Memory Cell
Timer
Control Logic (Master)
EEPROM Design Layout
E/Wcircuit
E/Wcircuit
Decoder Xe
Decoder Xr
Dec Y
Dat
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ddre
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lock
Dec
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Logic Design – Puts logic units such as adders, gates, inverters and registers into each module and run subroutines in each module .
Circuit / Transistor Design – Individual transistors are laid out in each logic unit.
Layout – To transfer from schematic to layout
pMOS
nMOS
VDD
VSS
S
S
D
D
VIN VOUT
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IC Design: 1st IC
1st IC design by hand (Jack Kilby)
Currently, hundreds of designers workon single product to design, validateand lay outed will take several monthsto complete with the help of CADtools.
Main considerations; performance die size design time and cost testability
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IC Design: State of The Art ICCMOS Inverter - basic building block of digital MOS design
Layout
Cross section
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Mask / Reticle After IC design is completed, generated layout image is printed on a piece of quartz glass coated with a layer of chromium. A laser beam projects the layout image onto the photoresist coated chrome glass surface. Photon change the chemistry of the exposed photoresist via a photo chemical reaction, and later dissolved in a base developer solution. A pattern etching removes the chromium at the exposed area. Therefore, it transfers the image of the IC layout to the quartz glass. This is done at mask shop
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Mask / Reticle Mask – Covers the whole wafer, used in projection, proximity and contact lithography technique. Reticle – Covers only part of the wafer, employed in step and repeat lithography technique.
MASK RETICLE
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Typical Wafer Fabrication Process Flow Around 500 process steps to complete IC fabrication Involves 20 masking steps
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Wafer Yield
The ratio between number of good wafers after finishing all the process steps, and total number of starting wafers .
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Die Yield
The ratio between number of good dies per total of dies on the tested wafer after functional probe test.
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Packaging Yield
The ratio between number of good chips after finishing all the packaging steps, and total of chips packaged.
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Overall Yield
Wafer yield depends mainly on processing and wafer handling. Careless handling and robot malfunction could break wafers Faulty process such as misaligned during lithography, large amount of particles, poor process uniformity, etc can also ruin wafers.
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Defects and Yield
Y – overall yield D – defect density (minimum level determined by facilities) A – chip area (die size) n – number of processing steps
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Cleanroom Structure
Main features; raised floor laminar air flow HEPA filters higher pressure controlled humidity and temperature
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Wafer Test
Parametric Test (Wafer Acceptance Test Data)
Functional Test (Die Yield)
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Packaging
4 Main Purposes;
to provide physical protection for the IC chip
to provide a barrier layer against chemical impurities and moisture
to connect the IC chip to the electrical circuit board
to dissipate heat generated during chip operations
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Main Packaging Steps
Wafers coated with protective layers on the surface, mechanically polished on the wafer backside to reduce thickness (600 to 300 um)
A thin layer of gold is coated at the wafer backside
Protective layer at the wafer surface is removed, and wafer backside is taped to on a solid frame. Then wafer sawing process.
Die sorting (to pick up good dies)
Die attach (to attach good dies to a packaging socket)
Wire bonding