Surface MEMS Fabrication Details Dr. Lynn Fuller, Adam ... · Surface MEMS Fabrication Details Page...

© November 1, 2017 Dr. Lynn Fuller

Surface MEMS Fabrication Details

Rochester Institute of Technology

Microelectronic Engineering

ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING


Dr. Lynn Fuller, Adam Wardas, Casey Gonta, Patsy Cadareanu

Webpage: http://people.rit.edu/lffeeeMicroelectronic Engineering

Rochester Institute of Technology82 Lomb Memorial DriveRochester, NY 14623-5604

Email: [email protected] webpage: http://www.rit.edu/kgcoe/microelectronic

11-1-2017 SurfaceMEMsFabricationDetails2017.ppt

http://people.rit.edu/~lffeee

mailto:[email protected]

http://www.rit.edu/kgcoe/microelectronic





OUTLINE

IntroductionDevice Cross SectionMaskmakingStepper JobsFabrication DetailsSignal ProcessingPackaging TestingSummaryReferencesHomework





INTRODUCTION

This document provides detailed information on RIT’s surface micromachine process. This process is capable of making many different types of MEMS devices. This MEMS fabrication process is CMOS compatible (with some modifications) back end module that can be added to realize compact microsystems (CMOS plus MEMS). This version is a simplified 4 or 5 photo level process to take advantage of 4 levels per plate maskmaking and to minimize the time to fabricate the devices.





GENERIC DEVICE CROSS SECTION

Starting Wafer

FieldOxide

Bottom Poly

Metal Layer

Bottom Poly 1 (Red) Layer 1Sacrificial Oxide (Blue Outline) Layer 2Contact Cut (White) Layer 6Metal (Blue) Layer 7Outline (Yellow Outline) Layer 9

Sacrificial Layer

Outline is only for layout, drawing a 4.5mm by 4.5mm outline, the maximum area for individual device designs .





MEMS MULTICHIP PROJECT TEMPLATE

4.5mm by 4.5mmdesign spacefor each project

4 different projects

Total 10 mm by 10 mm including 1 mm for sawing into 4 chips. Wafer sawing is easier if all chips are the same size

10

mm

5 mm





MEMS MULTICHIP PROJECT TEMPLATE

4.5mm by 4.5mmdesign spacefor each project

4 different projects

Total 10 mm by 10 mm including 1 mm for sawing into 4 chips. Wafer sawing is easier if all chips are the same size

10

mm

5 mm

Your

Design





2017 MULTICHIP PROJECT FINAL LAYOUT

10

mm

Total 10 mm by 10 mm including 1 mm for sawing into 4 4.5mm by 4.5 mm chips.





MASK ORDER FORM

x

MEMS-2017-Final.gds 410mm x 10mmDr Fuller

RIT

X yes, 4 levels per plate





MASK ORDER FORM DETAILS

Reticle

Number

Reticle

Name

Design

Layer .gds

#’s

Boolean Function Dark/

Clear

Comment

1 Poly1 1 None Clear Mirror

2 Cut 6 6 Inverted Dark Mirror

3 SacOx 2 None Clear Mirror

4 Metal 7 None Clear Mirror

Design Layer 9 Out (outline) is not used. It is only for placement of projects on the multi-project reticle template.





SURFACE MEMS 2017 FABRICATION PROCESS

16. ET29 – Etch Oxide 17. ET07 - Resist Strip, Recipe FF18. CL01 – RCA Clean19. PH03 – level 3 Sac Layer Define20. ETXX –HF Dip21. ME01 – Metal Deposition - Al22. PH03 – level 4 Metal -2um23. ET55 – Metal Etch – wet etch24. SAW1– Saw wafers ½ way through24. ET07 – Resist Strip and Release, wet?25. TE01 – wafer level testing26. Packaging and Testing27. SEM1 – Pictures and videos

11-1-17

1. Starting wafer2. PH03 – level 0, Marks3. ET29 – Zero Etch4. ID01-Scribe Wafer ID, D1…5. ET07 – Resist Strip, Recipe FF6. CL01 – RCA clean7. OX04 – 6500Å Oxide Tube 18. CV01 – LPCVD Poly 5000Å9. IM01 – Implant P31, 2E16, 100KeV10. PH03 – level 1 Poly11. ET08 – Poly Etch12. ET07 – Resist Strip, Recipe FF13. CL01- RCA Clean 14. OX05 – 700Å Dry Oxide15. PH03 – level 2 Contact Cut





STARTING WAFER – SCRIBE ID01

Starting Wafer





SSI COAT AND DEVELOP TRACK FOR 6” WAFERS

Use Recipe: COAT.rcp and DEVELOP.rcp





RECIPES FOR RESIST COAT AND DEVELOP

Level Level

Name

Resist Coat Recipe Develop

Recipe

Resist

Thickness

0 Zero OIR-620 Coat Develop 1.0um

1 Poly 1 OIR-620 Coat Develop 1.0um

2 CC OIR-620 Coat Develop 1.0um

3 Sac Layer S1827 MEMSCOAT1 MEMSDEV1 3.0um

4 Metal 1 S1827 MEMSCOAT2 Hand Develop 4.5um

MEMSCOAT2.rcp no HMDS, 2500rpm, 30sec, Hand Dispense, 110°C, 1min, Exposure for S1827, 525mj/cm2, Focus +2.0, NA=0.48, s=0.45, Hand Develop, no hardbake, no HMDS,

MEMSCOAT1.rcp 4000rpm, 30sec, Hand Dispense, 110°C, 1min Exposure for S1827, 525mj/cm2, Focus +2.0, NA=0.48, s=0.45MEMSDEV.rcp has 200 second develop time, hardbake 140°C

SacrificialLayer

Metal





PHOTORESIST PROCESSING

SPIN COAT

OIR 620-10

Resist

3250rpm, 30 sec.

SOFT BAKE

90 °C

60 sec.

DEHYDRATE BAKE/

HMDS PRIMING

HMDS Vapor

Prime

140 °C, 60 sec.

DEVELOP.RCP

POST EXPOSURE BAKE

110 °C, 60 sec.

HARD BAKE

120 °C, 60 sec.

COAT.RCP

DEVELOP

DI Wet

CD-26 Developer

48sec. Puddle,

30sec. Rinse,

30sec., 3750rpm

Spin Dry





ASML 5500/200

NA = 0.48 to 0.60 variables= 0.35 to 0.85 variable

With Variable Kohler, orVariable Annular illuminationResolution = K1 l/NA

= ~ 0.35µm for NA=0.6, s =0.85

Depth of Focus = k2 l/(NA)2

= 1.0 µm for NA = 0.6i-Line Stepper l = 365 nm

22 x 27 mm Field Size





STEPPER JOB

Mask Barcode:

Stepper Jobname: MCEE770-MEMS4XLevel 0 (combi reticle)Level Clearout (combi reticle)

Level Poly 1Level CCLevel SacOxLevel Metal

Level MEMS-Test (no alignment)

After photo prior to etch inspect the alignment marks.

They have to be perfect. If not rework the photo step.





DRYTEK QUAD RIE TOOL





ZERO ETCH FOR ASML ALIGNMENT MARKS

Recipe Name: ZEROETCHChamber 3Power 200WPressure 100 mTorrGas 1 CHF3 50 sccmGas 2 CF4 25 sccmGas 3 Ar 0 sccmGas 4 O2 10 sccm

Max Time = 120 seconds

Silicon Etch Rate 650 Å/min 8.8 um L/S 8 um L/S





SCRIBE WAFER WITH ID NUMBER

Wafer has alignment marks etched in two locations.

Scribe on back of wafer

near the wafer flat

ID numbers D1, D2…etc.

D1

FrontBack





ASHER, SCRIBE, RCA CLEAN & SRD

Gassonics Asher

Recipe FF

RCA Clean Bench

O2 + Energy = 2 OO is reactive and will combinewith plastics, wood, carbon,

photoresist, etc.





RCA CLEAN

DI waterrinse, 5 min.

H20 - 50HF - 130 sec.

HPMHCL - 1part

H2O2 - 1partsH2O - 17parts70 °C, 15 min.

SPIN/RINSEDRY

APMNH4OH - 1partH2O2 - 1partsH2O - 17parts70 °C, 15 min.







USING EXCEL SPREADSHEET FOR OXIDE GROWTH CALCULATIONS

These spreadsheets are available on Dr. Fullers webpage.





BRUCE FURNACE RECIPE 406 – WET OXIDE 6,500Å

1100°C

800 °C

Boat Out Boat In Boat Out

Load Push Stabilize Ramp-Up Soak Anneal Ramp-Down Pull

Recipe #406

800 °C

25 °C

Any

0 lpm

none

800 °C

At the end of a run the furnace returns to Interval 0 which is set for boat out, 25 °C and no gas flow. The furnace waits in that state until someone aborts the current recipe or loads a new recipe.

Wet Oxide Growth, Target 6,500 Å, Tube 1

Interval 0 Interval 1 Interval 2 Interval 3 Interval 4 Interval 5 Interval 6 Interval 7 Interval 8

12 min 15 min 30 min 5 min 65 min 5 min 60 min 12 min

10 lpm 10 lpm 5 lpm 5 lpm 3.6/2 lpm 15 lpm 10 lpm 15 lpm

N2 N2 N2 O2 O2/H2 N2 N2 N2





BRUCE FURNACE

Tube 1 Steam Oxides

Tube 2 P-type Diffusion

Tube 3 N-type Diffusion

Tube 4 Dry Oxides and

Gate Oxides

Tube 1

Tube 2

Tube 3

Tube 4





TENCORE FT-300 SPECROMAP

Record:

Mean

Std Deviation

Min

Max

No of Points





AFTER 6500Å OXIDE GROWTH

Starting Wafer

6500 Å





DEPOSIT POLYSILICON

Poly Target 5000ALPCVD, 610C, Rate ~64Å/minTime~78 minDo not use log sheet for rate/time

Recipe POLY 610Temp = 610°CPressure = 300 mTorrSilane Flow = 100 sccm

Substrate





POLYSILICON DOPING

Ion Implant P31Dose = 2E16 cm-2Energy = 100KeVTime ~20min at 400 µA

Substrate





SSI COAT AND DEVELOP TRACK FOR 6” WAFERS

Use Recipe: Coat.rcp and Develop.rcp






Level Level

Name


Recipe

Resist

Thickness








SacrificialLayer

Metal





ASML 5500/200

NA = 0.48 to 0.60 variables= 0.35 to 0.85 variable

With Variable Kohler, orVariable Annular illuminationResolution = K1 l/NA

= ~ 0.35µm for NA=0.6, s =0.85

Depth of Focus = k2 l/(NA)2

= 1.0 µm for NA = 0.6i-Line Stepper l = 365 nm

22 x 27 mm Field Size





STEPPER JOB

Mask Barcode:


Level Poly 1Level CCLevel SacOxLevel Metal






AFTER PHOTORESIST COAT, EXPOSE & DEVELOP





AFTER POLY1 ETCH

Drytek Quad

Recipe FACPOLY

Etch Rate ~1150Å/min

5000Å Poly





2 OF 4 CHAMBERS IN THE DRYTEK QUAD RIE TOOL





PLASMA ETCHING IN THE DRYTEK QUAD





ANISOTROPIC POLY GATE ETCH RECIPE

Anisotropic Poly Gate Etch Recipe

SF6 30 sccm, CHF3 30 sccm, O2 5 sccm, RF Power 160 w, Pressure 40 mTorr,

1900 A/min (Anisotropic), Resist Etch Rate 300 A/min, Oxide Etch Rate 200 A/min

Recipe Name: FACPOLY Step 2Chamber 2Power 160 wattsPressure 40 mTorrGas SF6Flow 30 sccmGas CHF3Flow 30 sccmGas O2Flow 5 sccmPoly Etch Rate 1150 Å/minPhotoresist Etch Rate: 300 Å/minOxide Etch Rate: 200 Å/min

Endpoint See Video

https://people.rit.edu/lffeee/Videos.htm

https://people.rit.edu/lffeee/Videos.htm





STRIP RESIST, RCA CLEAN





GROW 700Å DRY OXIDE

This oxide is to insulate the poly

so that metal can cross poly and

not make connection.





BRUCE FURNACE RECIPE 270 – 700Å DRY OXIDE

1000°C

800 °C

Boat Out Boat In Boat Out

Load Push Stabilize Ramp-Up Soak Anneal Ramp-Down Pull

12 min 15 min 20 min 93 min 5 min 40 min 15 min

10 lpm 10 lmp 5 lpm 10 lpm 15 lpm 10 lpm 5 lpm

N2 N2 O2 O2/ N2 N2 N2

Recipe #270

Interval 0 Interval 1 Interval 2 Interval 3 Interval 4 Interval 5 Interval 6 Interval 7

800 °C

25 °C

Any

0 lpm

none

800 °C

At the end of a run the furnace returns to Interval 0 which is set for boat out, 25 °C and no gas flow. The furnace waits in that state until someone aborts the current recipe or loads a new recipe.

Dry Oxide Growth, Target 700 Å

Verified: 3-1-04






Level Level

Name


Recipe

Resist

Thickness








SacrificialLayer

Metal





AFTER CUT PHOTO AND BOE ETCH

Substrate





TEST STRUCTURES

Lithographic overlay and resolution test structure

Electrical Tests:ResistanceSheet ResistanceContact Resistance





RESIST STRIP

Substrate





STEPPER JOB

Mask Barcode:


Level Poly 1Level CCLevel Sac Layer Level Metal







Level Level

Name


Recipe

Resist

Thickness







MEMSCOAT1.rcp 4000rpm, 30sec, Hand Dispense, 110°C, 1min Exposure for S1827, 525mj/cm2, Focus +2.0, NA=0.48, s=0.45Then Flood expose wafer edge using black transparency mask thenMEMSDEV.rcp, 200 second develop time, hardbake 140°C

SacrificialLayer

Metal





BLACK PLASTIC MASK – FLOOD EXPOSE WAFER EDGE





AFTER SAC LAYER PHOTO AND DEVELOP

Substrate





PRE METAL HF DIP

SPIN/RINSEDRY

H20 - 50HF - 130 sec.






SPUTTER ALUMINUM

CVC 601 Sputter Tool

(no radiant heating

during pump down)

Pressure = 5mTorr

Power = 2000 Watts

Time = 50 min

Thickness = ~ 1.5um





METAL DEPOSITION

Substrate






Level Level

Name


Recipe

Resist

Thickness







MEMSCOAT1.rcp 4000rpm, 30sec, Hand Dispense, 110°C, 1min Exposure for S1827, 525mj/cm2, Focus +2.0, NA=0.48, s=0.45Then Flood expose wafer edge using black transparency mask thenMEMSDEV.rcp, 200 second develop time, hardbake 140°C

SacrificialLayer

Metal





METAL PHOTO

Substrate





METAL ETCH

Substrate





K&S 780 WAFER SAW

Saw ½ way

through wafer.





WAFER SAW RECIPE

Block 01 - Align on 3nd cut at top of bottom chip, no cuts but shift by -10mm after align

Height 0.80000mm

Cut Depth 0.5000mm (leaving 0.3000 mm of wafer uncut)

Number of cuts = 0000

Block 02 - X cuts (horizontal cuts parallel to wafer flat)

Height 0.80000mm



Block 03 - Align on 3rd at the top of bottom chip, no cuts but shift by -10mm after align

Height 0.80000mm



Block 04 - Y cuts (vertical cuts perpendicular to the wafer flat)

Height 0.80000mm



other parameters on next page….





SAW RECIPE – OTHER PARAMETERS

Blade Exposure 7.4922

Auto Height Rate 499

Spindle speed 20,000

Angle 0.0

Start Cut -33.4

Cut Length 175.00

Index ??

Cut Count ??

X entry speed 2.0

X cutting speed 3.0

Z speed 0.3





AFTER SAWING AND REMOVAL OF GOOD CHIPS

Wafer Sawing Movie





WAFER AFTER SAWING READY FOR RELEASE





RESIST STRIP AND RELEASE

Substrate

AcetoneIsopropyl AlcoholSlow Pull

or Low power O2 plasma





TEST EQUIPMENT

Manual Prober





SINGLE RESISTOR SENSOR AMPLIFIER DESIGN

-V

-

+

+V

-V

R1

R4

Vout

-

+

+V

-V

+V

267

0.00004%/°C with gain of 1000 and 100C





SINGLE SUPPLY OSCILLATOR (MULTIVIBRATOR)

-

+Vo

C

+V

R2R1

R

VT

+VR3

Vo

t

t1

+V

0

Let R1 = 100K, R2=R3=100K

and +V = 3.3

Then VT = 2.2 when Vo = 3.3

VT = 1.1 when Vo = 0





UNIVERSAL PUMP & FLOW SENSOR ASSEMBLY

1” by 3” PCB 0.0125” thick with 0.005”copper

Pin strip header

Hose nipples

Plastic cover





CROSSECTION

Pin strip header

Hose nipples

ThermosettingGlue on Plastic cover

1” by 3” PCB 0.0125” thick with 0.005”copper

MEMS chip mounted flush with PCB surface, wire bonds from MEMS chip to copper traces

Photoresist (film) channel wallsThickness 50µm to 150µm





AFTER WIRE BONDS, HEADER AND NIPPLES





CLEAR FIELD MASKS

Need dark field masks for Anchor or CC

Otherwise use negative resist





USING NEGATIVE RESIST

1. Coat wafers with n-LOF-2020 Image Reversal Resist, Use COATNLOF recipe on the SSI track

HMDS prime: 140C, Dispense for 30s, Prime for 60sManually dispense photoresistSpin at 2500 RPM, Spin for 60s, Thickness ~2100nm = 2.1umSoft Bake at 110C, Bake for 60s

2. Expose on the ASML Stepper – use same mask as for etch process (clear field)Dose = 66 mJ/cm2 i-line (365nm), Focus = 0, NA = 0.60, Sigma=0.625

3. Develop on SSI Track using recipe DEVNLOFPEB (Image Reversal Bake) at 110C for 60s Spin and dispense developer for 5s, Dispense developer for 5s, Puddle develop for 70s, Spin and rinse for 30s at 1000 RPM. Spin dry for 30s at 3750 RPM, Do not hard bake. It can damage the sidewall profile. Hard Bake time = 0s

4. Etch

5. Remove Photoresist





USING NEGATIVE RESIST





SUMMARY

This project allows students to see the entire process for design, fabrication, packaging and testing of a MEMS based Microsystem.





REFERENCES

1. Dr. Lynn Fuller’s webpage2. more





HOMEWORK – FABRICATION DETAILS

1. Draw a series of pictures that show the crossection and layout

for your design project. From starting wafer to test. Not all of

the steps but for most of the steps.

2. Provide a list of all recipes and a short description.

3. What data should be collected ie. at step 7 record oxide

thickness, at step 9 take picture of resolution, at step ? …..

4. Discuss how your device will be packaged.

5. Discuss how the devices you make will be tested. Describe

any electronic circuits

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