Introduction - University of Washington€¦ · Web viewNoise, Crosstalk, and Power Consumption...
Transcript of Introduction - University of Washington€¦ · Web viewNoise, Crosstalk, and Power Consumption...
Noise, Crosstalk, and Power Consumption
OverviewIn this lesson we will
Examine a high-level view of noise and noise sources in digital systems. Introduce problem of power supply and ground noise and some of the root causes. Examine methods for mitigating power supply and ground noise. Examine both board level attack and a distributed or local attack. Analyze crosstalk and inductive coupling. Briefly examine ground planes and power consumption.
The Real World AgainIdeal systems
Switch in 0 time Noise free No prop delay Consume no power
Etc.Real systems
Have all these problems
Need to be aware of such problemsNeed to have tools to deal with them
Important to rememberNo two systems alikeVariation in physical world attributes
Means must understand root cause of problems
NoiseNoise in electrical circuits
Unwanted signals arising from number of sourcesSignals often random in nature
Potential sources External electrical sources Coupled in from
MachineryElectric lightsRadio and televisionTelecomm equipment
Internally generatedClocksSwitching
Reflected in power distribution
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Coupling between signalsCapacitiveInductive
Thermal
Problem tends to worsen with Increasing frequency Decreasing signal edges or other electrical features
Problem exacerbated as denominators decrease Partial solution: reduce di or dv
Let's Look at several of these Examine some ways to help solve
Keep in mind there is no perfect solution
Power Supply and Ground Noise
Common Path NoiseWhen signal sent from source to destination
Must return via ground path
Common path noise is product of Returning signal current and ground impedance
Consider the following circuitGraham and Johnson page 263
In distributed systemValue of parasitic inductance increasing with module separation
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didt
, dvdt
In both circuitsReturn current goes through common ground pathEither can cause noise to be generated via
Ground inductance
Fundamentally we’re dealing with Ohm’s law
To ensure low common path noiseMust have low impedance ground connections between gates
More generally the signal path has three components1. The ground path2. The power path3. Path between power and ground
Noise can arise from voltage drops in any of these segmentsGraham and Johnson 266 267
Such recognition gives rise to following three general rules for dealing with such problems
1. Zg - Use low impedance (key word here) ground connections between gates - a ground plane works very well.
2. Zp - Impedance between power pins on any two gates should be as low as impedance between ground pins.
3. Zs - Must be a low impedance path between power and ground.
We'll talk about ways of achieving each of these
Power Distribution WiringAs we've seen power supply wiring has
Resistive component Inductive component
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ResistanceLet’s look at the resistance of the
Power supply wiring firstImportant to recognize
Where power supply isWhat the wiring is
Resistance of wiring easy to calculateExpected operating current knownIf resistance is problem
Get larger diameter wireAlso pure resistance
Not a function of frequency
Power supply may also be designed with remote senseSense the level at far end of distributionAutomagically adjust
InductanceGraham and Johnson page 265
Effects of inductance harder problem to deal with
Rapidly changing signalsActing across power distribution inductanceInduce voltage shifts between
Supply and logic it feedsSuch shifts are more sudden and larger
Than those arising from wiring resistance
Noise given by basic relationship v=L di
dtAs dt decreases → V increases
Some array logics support control of output rise and fall times
We have three potential approaches to deal with problem1. Use low inductance wiring2. Use logic immune to power supply noise3. Reduce size of charging currents
Do these help
1. L - Inductance is logarithmic function of wire diameterAlmost impossible to solve problem
Getting larger wire alone
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2. Logic - Differential logic signals almost completely immunePower supply fluctuationNot cheapNot particularly practical in many casesSome vendors moving in this direction
3. Reduce di/dt - two ways to accomplishIncrease denominatorReduce numerator
Reducing magnitude of charging currents lower level signalsInvolves board level filtering
Let's look at problem in following circuitGraham and Johnson page 271
Assume We are switching to a logic high must charge capacitorRise time of 5 ns50 pf load capacitor
5-7 unit loads
Compute max di/dt
From
i=C dVdT
Plus a little calculus we get
max didt
=1. 52 ΔV(T rise )2
C=1.5 x 107 A /sec
Assuming typical TTL signal →ΔV = 4.5V
Assume we have two parallel power distribution paths Power Ground plane
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Based upon such a configurationNext compute the inductance of the power supply wiring L according to
Lpsw=10 .16 X ln ( 2HD )=164 nH
L InductanceX Length of wire Assume 10 inH Height above ground Assume 0.1 inD Diameter of wire Assume 18 AWG - 0.04in
We now compute peak noise voltageNote: we’ll see that below certain frequencies
Impedance of PSW is sufficiently low We don’t need to do anything
Since
V=Lpswdidt
V noise=Lpsw ( didt )max
=(1.5 x 107 ) (164 x 10−9 )=2. 5V
To solve problemGraham and Johnson page 272
Install board level bypass C2 as shownAssumes
The power supply is not on the board C2 is installed on the board - generally at the card edge
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If impedance of C2 lower than power supply wiringFrom KCL majority of charging current for C1will flow through it
Rather than the system power supply wiring
In addition original parasitic inductanceSplit into two pieces
L1A piece must be smaller than the original L1Therefore produce smaller noise voltage drop
Computing Board Level Bypass CapWe compute board level bypass cap as follows
1. Estimate max step change in supply current - I due to gate switchingThis will flow through the psw
Don't know when gates will switch Assume all N gates switch simultaneously at some known frequency
Parasitic capacitors all in parallel
ΔI max= N CΔV signal
Δt
ΔI max= N CΔV signal
τ rise
2. Determine max power supply noise logic can handle - Vnoise
3. Max common path impedance is going to be
X max=ΔV noise max
ΔI max
Remember - this is an impedance
Typically we can allocate all of the impedance to one lumped value
If not must split up as follows(a) Ground connection(b) Power connection(c) Path between power and ground
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4. Figure inductance in power supply wiring - LPSW
Combine with Xmax to find frequency below which power supply wiring is adequate
That is - a low enough impedance
X L= j ω L
|X L|= ω L = X max=ΔV noise max
ΔImax=2 π F Lpsw
Want to determine frequency we start to get into troubleGives us a worst case number
If all gates switch together at frequency F = Fpsw substituting 3 into 4
Fpsw=( ΔV L
ΔI L ) 12 π Lpsw
From 4
|X L|=ΔV L
ΔI L= X max
FPSW=Xmax
2 π LPSW
Will get less noise than Vnoise and power supply wiring adequateSignal can travel through psw and noise will be below Vnoise max
5. Below FPSW power supply wiring is fine – don’t need board level bypass. Above FPSW must add bypass cap to take over - To lower the impedance.
Compute value of cap that has impedance Xmax at FPSW as
XC= 1j ω C
=Xmax
ω = 2π F …let F = Fpws
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Local Bypass CapacitorsEvery printed circuit board needs
Relatively large bypass cap to counteract Inductance of power supply wiring
Single perfect cap on each boardCould completely solve distribution problem
We can compute the max frequency at which such a cap is effectiveA good cap should be effective between
Fpsw and Fbypass
Fboard bypass=X max
2 π LC 2
Fboard bypass will be driven by LC2
Unfortunately no cap perfectAs we know every cap has some series inductance
For the one we just added we have - LC2
Impedance of LC2 increases with frequency
Cap also has parasitic resistor Denoted equivalent series resistance – ESR
Approximately 0.1 – 1.1 Ω
Full capacitor impedance given as:
XC (F )=ESR+ j(−1ωC
+ωL)From which we compute magnitude of cap impedance
|XC ( F )|=( ( ESR )2+( −12 π FC
+2 π FL)2
)1/2
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As we saw earlier Such inductance causes impedance to increase rather than decrease
At high frequencies
Extent of problem depends upon Value of Fknee
F knee=0 .5
τ rise
Impedance which must be maintained
Best way to guarantee low impedance above Fbypass Add another cap with lower series resistance
Remember how resistors in parallel addTotal will be less than smallest
We accomplish this byParalleling a lot of small capacitors
Sprinkle parallel array around circuit cardRemember impedances in parallel
This becomes the third piece of our solution
We now see that three factors dominate impedance between power and ground
Low frequencies - inductance of power distribution wiring 0 to Fpsw
Middle frequencies - impedance of card level bypassFpsw to Fbypass
High frequencies - impedance of distributed cap arrayFbypass to Fknee
We design cap array as follows
1. Want system to work up to Fknee. Calculate how much inductance can tolerate at high frequency
|X L|=|Lω|=|2 π FL|
Fknee=0.5T r
Ltot=X max
2 π Fknee
=Xmax Tr
π
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2. Look up or measure series inductance of bypass caps (C3).Typical value around 1 - 5nH. Surface mount - through hole
Since Lequivalent for N parallel inductors is
Lequivalent=Li
N
we must put put N in parallel to get Ltotal
Thus we have
Ltot=LC 3
N
Which is what we want – configuration reduces total inductance
Use this figure to compute number of bypass caps
Total array capacitance must have impedance less than Xmax at frequencies down to Fbypass. Recall LC2 is board level bypass.
from above
From,
XC= 1j ω C
with XC = Xmax and = 2 Fbypass
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4. Calculate capacitance of each element of the array
ExampleLet's consider CMOS board of 100 gates. Assume 10 pF loads and 5ns rise times.
Fknee=0 .55 ns
Let the series inductance of cap be 5 nH and assume we want Xmax = 0.1
Thus
Ltot=Xmax T r
π=0 .159 nH
N=LC 3
Ltot
= 5 nH0.159 nH
=32
Fbypass=Xmax
2 π LC 2
= 0 .12 π 5 nH
=3.18 MHz
Carray=1
2 π Fbypass Xmax
=0.5 μF
C element=Carray
N=0.016 μF
Power and Ground PlanesParallel power and ground planes provide 3rd level of bypass capacitance
Power and ground planes have Zero lead inductance No ESR - equivalent series resistance
Help to reduce power and ground noise at high frequencies
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Compute capacitance as follows
r - Relative electric permittivity of insulatorAssume 4.5 for epoxy PCB FR4 material
A - Area of shared power-ground plane in2
d - Separation between planes
Crosstalk and LoopsWe know from
Ampere's LawCurrent flowing in wire will produce magnetic field
Faraday's and Lenz's workCircuit moving in magnetic field has induced current
Work of Gauss and othersCharge and potential difference between two conducting surfaces
Related by quantity called capacitance
From these we see Mother Nature is conspiring against us
When we have adjacent conducting pathsCapacitive and inductive physics
Couples signals from one circuit into the other
Any time we have two circuitsWe have mutual capacitanceVoltages in one circuit create electric fields
Such fields affect other circuit
Any time we have two loopsWe have mutual inductanceCurrent in one loop creates magnetic field
Such fields affect other loop
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Crosstalk
Crosstalk arises from mutual capacitance and inductance between circuits
Will examine each component separately
Consider simple circuitGraham and Johnson page 26Let's only look at capacitanceWe model circuit as follows
Intuitively we seeSince can't change voltage across cap instantaneouslySignal on A must appear on B
The mutual capacitance CM injects current IM into circuit BProportional to rate of change of voltage in circuit A, VA
Can write simplified approximation as
I M=CMdV A
dtIM is the crosstalk current
Valid under following assumptions Coupled current is much smaller than primary current and does not
load circuit A Coupled signal voltage in B smaller than signal on A Capacitor is large impedance compared to circuit B ground impedance
Directs where current flows
Can estimate crosstalk as fraction of driving voltage VA given Known mutual capacitance CM Fixed circuit rise time Tr
Known impedance in receiving circuit RB
Using Thevenin model1. Derive max change in voltage per unit time from change in Circuit A
dV A
dt=
ΔV A
Tr2. Compute mutual capacitive current
I M =CM
ΔV A
T r
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3. Compute the crosstalk current in Circuit B as the impedance in circuit times the induced current
Induced crosstalk voltage given asV crosstalk= I M RB
4. Compute the crosstalk signal as the ratio between The induced voltage in B with respect to the change in A
V crosstalk
ΔV A=
I M RB
ΔV A=
RB CM
T r
V crosstalk=ΔV A(RBC M
T r )Preventing or Reducing Crosstalk
To prevent such coupling we have several alternatives
GuardingGround trace routed so as to cut pathGuard trace grounded at one endCapacitance still existsCannot couple in
Twisted PairBy twisting conductors
Net crosstalk from alternating plus and minus couplingCancels
Ground Plane or Ground GridProvides return path directly under traceLowest inductance
Smallest loop areaMinimizes magnetic field interacting with other tracesGround plane best grid provides good alternative
LoopsGraham and Johnson page 28
Any electronic circuit contains loopsIt's the only way they work
Again from our studies of electromagnetic physicsChanging electromagnetic field passing through circuit
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Induces current in circuit
Such fields are everywhereRadio and television stationsElectric lights
Let's look at following simple circuit
The mutual inductance LM injects voltage VM into loop BProportional to rate of change of voltage in circuit A
Can write simplified approximation as
V crosstalk=LMdi A
dtThe above expression is valid under following assumptions
Induced voltage across LM smaller than primary signal voltage and attaching LM does not load circuit A
Coupled signal current in circuit B smaller than current in circuit A Secondary impedance is small compared to impedance to ground of circuit B
Can estimate crosstalk as fraction of driving voltage VA given Known mutual inductance LM Fixed circuit rise time Tr
Known impedance in driving circuit RA
1. Derive max change in voltage per unit timedV A
dt= ΔV
T r2. Assume loop A resistively damped by RA and current and voltage proportional
to each other Compute current in A
dV A
dt=RA
di Adt
ΔV A
τ rise
=R AdiA
dtdiA
dt=
ΔV A
RA τ rise
3. Compute mutual inductive noise - induced voltage
V crosstalk=LMΔ V A
RA T r
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4. Compute the crosstalk signal as the ratio between The induced signal and the causal signal
V crosstalk
ΔV A
= Crosstalk=LM
RA T r
To prevent such coupling we have several alternatives
When laying out circuitKeeps such loops as small as possible
Non-existent if possible
Circuit A is preferable to Circuit B
Power ConsumptionDepends upon
Logic familyImplementationFrequency of operationLoad on the deviceSupply voltage
Comprised of two componentsStatic - DCDynamic - AC
Compute as
P=(CL+Co )V 2 f +idc V
V Supply Voltageidc DC currentCL External capacitive loadCo Internal output capacitancef Frequency of operation - switching frequency
Frequency dependent portion arisesFrom totem pole output configurationBoth devices on for short time
When ON both conducting
CMOSDC
Top or bottom device OFFVery low power consumption
With logic lowSink current coming from gate circuit of succeeding device
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With logic highSource current going to gate circuit of succeeding device
ACBoth devices ON for short intervalSink current now through both devices to ground
TTLDC
Top or bottom device OFFHigher power consumption
With logic lowSink current coming from emitter or diode circuit of succeeding device
With logic highSource current going to emitter or diode circuit of succeeding device
ACBoth devices ON for short intervalSink current now through both devices to ground
Summary
In this lesson we Examined a high-level view of noise and noise sources in digital systems. Introduced problem of power supply and ground noise and some of the root
causes. Examined methods for mitigating power supply and ground noise. Examined both board level attack and a distributed or local attack. Analyzed crosstalk and inductive coupling. Briefly examined ground planes and power consumption.
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