Introduction to IC Test

EL/CCUT T.-C. Huang May 2004

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Introduction to IC TestIntroduction to IC Test

Tsung-Chu Huang(黃宗柱 )

Department of Electronic Eng.Chong Chou Institute of Tech.

Email: [email protected]

2004/05/24


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1. Basic Concepts about Memory/Storage2. Introduction to RAM/ROM Structure3. Reduced Functional Memory/Fault Models4. RAM Test5. ROM Test6. IDDQ Test for Memory7. Parametric Test8. Dynamic Test9. Random Test10.MBIST

Introduction to Memory TestingOutline


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Typical Storage Hierarchy

Archive II

Archive I

Main Memory

L2 Cache

L1 Cache

Register

Optical disk

Magnetic disk

DRAM

SRAMDRAM

SRAM

FF


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Moore’s Law on Transistor Counts


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Moore’s Law on Memory

1985 20001017 bits

1020 bits


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MOS Memory Learning Curve

310$

bits1210 bits1310 bits1410 bits1510

410$

510$


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Taxonomy

1. by Access Structure1. Random Access Memory (RAM)2. Serial Access Memory (SAM)3. Content Access Memory (CAM)

2. by Alterability1. RAM: R/W Memory, SRAM, DRAM, CCD2. ROM3. EPROM4. EEPROM5. Filed Alterable ROM, e.g., Flash

3. by Device: BJT, NMOS, CMOS, CCD


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Basic CCD

1 12 2 23 3 34 441 1 12 2 2341


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Basic Static RAM (SRAM)

Word Line

Bit Line Bit Line


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Basic SRAM Architecture

Memory Array

ColumnsC M 2

RowsR N 2

Row

D

ecoder

Column Decoder

NR

WL

BL

Control

Ro

w A

ddre

ss B

uffe

r

NN

Column Address Buffer

M

M M

0b0b1cb1cb

0w

1Rw

WR /

CS

SA

inD outD


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A Simple Sense Amplifier (SA)

Bit Bit

CS

VDD

Typically, the SA must be sensitive enough to read about 10mV.


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Historical Evolution of DRAM

Write Select

Read

Read Select

WriteRead

R/W Select

Write

Write Select

Read Select

Data Data

R/W Select


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Historical Evolution of DRAMBasic Planar and Trench DRAM Cells

WordBitPlanar Cell

Trench CellWordBit


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Basic ROM Architecture

Word Line

Bit Line


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Reduced Functional Memory Model

0 0 1 1 0

1 0 1 0 1

0 0 0 0 1

0 0 1 1 1

0 1 0 0 1

0 1 1 0 1

0 0 0 1 0

0 0 1 0 0

1 1 0

1 0 1

0 0 0

1 0 0

1 0 0

0 0 0

1 0 1

1 0 1

RowAddressDecoder

ColumnAddressDecoder

Re

ad/W

rite L

ogic

D: Data

A: Address

C: Cell Array


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1. Stuck-At Faults• Cell stuck• Driver stuck• Read/write line stuck• Chip-select line stuck• Data line stuck• Open in data line

2. Transition Faults• Cell can be set to 0 but not to 1 or vice versa.

3. Coupling Faults• Short between data lines• Crosstalk between data lines

4. Neighborhood Pattern Sensitive Faults• Pattern sensitive interaction between cells

5. Address-decoder Faults• Address line stuck• Open in address line• Shorts between address lines• Open decoder• Wrong access• Multiple access

Reduction of Functional Faults


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1. Address Decoder Faults2. Memory Cell Faults

1. Single Cell Faults• Single-Cell Stuck-At Faults (SCSF)• Single-Cell Transition Faults (SCTF)

2. Dual-Cell Faults• Coupling Faults (CF)

3. Multiple-Cell Faults• Neighbor Cell Faults• Single Line Faults• Neighbor Line Faults

Reduced Functional FaultsFault Models


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Fault Levels and Assumptions

NPSFCF

TF

SAF

read & non-transition write operationswill not cause an error;transition write operation may causean error.

1. Inversion coupling faults2. Idempotent coupling faults3. Bridging coupling faults4. State coupling faults

Base cell


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Coupling Functional FaultsCoupling Relations

},,,,,{

),(: )0,0(: )1,1( ),(: )0,1(: )1,0(: Notations

lh

xxwwlh:wxxwww

• Assume w(x, y) denotes a write y operation to a cell containing an x.• <I/F> denotes a fault in a single cell where I describes the sensitizing

input and F describes the fault value.• <I1, I2, …, In-1; In/F> denotes a fault involving n cells where I1, I2, …,

In-1 describes conditions on the n-1 cells to sensitize the fault in cell n and In describes the condition for the fault to be sensitized in cell n.

},,,1,0{},,,,,{ :I/F lh


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• Classified by Cell Count k and Affected Position Count p.• r: the corresponding row; c: the corresponding column• n = R x C, the total number of cells.

Coupling Functional FaultsA. J. van de Goor, 1991

kp

1 row column n

1 k1p1 k1pr k1pc k1pn

2 k2p1 k2pr k2pc k2pn

I kip1 kipr kipc kipn

n knp1 knpr knpc knpn


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March TestSuk, 1981

}

;

){;0;1(

)(

operations

aanafor

operations

• A march test consists of a finite sequence of march element that is a finite sequence of operations applied to every cell in memory before proceeding to the next cell.

• Notation of March Tests:

}

;

){;;0(

)(

operations

anaafor

operations

.irrelevant isdirection the,or


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March TestSuk, 1981

• Operations of March Tests:• w0: write zero to the cell,• w1: write one to the cell,• r0: read and detect whether the result is 0, • r1: read and detect whether the result is 1.

• Example: the simplest model (non-coupling SAF)

11 00 1100 rwrw)rwr(w

• For the non-coupling SAF, 2n wr-operations are needed.


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Traditional RAM Test• Zero-One:

• Not all TF, CF are detected, 4x2a length (a-bit address)

• Checkboard: • additionally detects shorts btw adjacent cells.

• GALPAT (Galloping pattern) and Walking 1/0• Sliding Diagonal• Butterfly

11 00 rwrw


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Multiple RAM Fault March Tests• Test-US: MATS, MATS+

• Modified Algo. Test Seq. for unlinked SAFs.

• Test-UT: Marching 1/0, MATS++

• Test-UCin: March X• Test-UCid: March C- (C)• Test-LCid: March A• Test-LTin: March Y• Test-LTCid: March B

11 00 rwrw 11 00 rwrw

11000 1100111 00 rwrrwrwrwrrwrw

0011 00 rwrwrw

0011 00 rwrwrw

00 11 0)0(0 11 00 rwrwrrwrwrw 01001 0110 1101 00 wwrwwwrwwrwwwrw

000111 00 rrwrrwrw

01001011011001100 wwrwwwrwwrwrwrwrw


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Comparison on Fault Coverage

0

20

40

60

80

100

Zero-O

ne

Slidi

ng D

iagon

al

GALCOL

MAT

S-OR

MAT

S-AN

D

MAT

S+

March

ing 1/

0

March

C

March

A

March

B

TLSN

PSF1

G


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Memroy BIST Architecture

CUT

CUT

CUT

CUT

ORATPG

ORATPG

ORATPG

DIST DIST

BISTC

Em

bedded

Separat

e

Centralized Distributed

TPG: Test Pattern Generator, ORA: Output Result AnalyzerCUT: Circuit under Test, BISTC: BIST Controller

Microprocessor based BIST is possible for SoC Test.


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Schmoo Plot• To show the parametric relations during parameter test.

parameter1

parameter2

Lack

Failed

Worked


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Concurrent Test and Partitioning• Partitioning is frequently used to reduce the power

dissipation, time response and to provide possible concurrency for most circuits.

• Generic Memory Partitioning:


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RAM Self-Repair• To promote the product yield.

2r rows

2c columns

spare rows

spare columns


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IDDQ TestingBasic Concept

VDD

Current Sensor

IDD

IDD

t

IDD

t


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Classification of Random Testfor RAMs

RAM

A

W

D

SA

DDDDRRRR

DDRRDDRRDRDRDRDR

D: DeterministicR: Random


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PRPG and SISR/MISR(reviews)

D1

C1

+

D2

C2

+

D3

C3

+

D4

C4

+

Dn-1

Cn-1

+

Dn

Cn=1

Reset all FFs


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Introduction to ROM Tests

• In Logical ROM Test, only read operations are concerned.

• However, production tests for PROMs and EPROMs are concerned with ascertaining that the device can contain any data that may need some specialized tests.

• Most RAM test algorithms can be used/modified for ROMs.

• Useful Test Methods:• Parity Checking• Checksum (e.g., JEDEC standards)• Cyclic Redundancy Checking (CRC) (e.g., using LFSR

)


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Introduction to Dynamic Tests

• Dynamic faults are electrical faults the causes of which are time dependent and internal to the chip.

• Classification of Dynamic Faults:1. Recovery Faults

Sense Amplifier Recovery (SAR) Write Recovery (WR)

2. Retention Faults Sleeping sickness Refresh line stuck at Static data loss

3. Imbalance Faults Bit-line precharge voltage imbalance fault

• To test dynamic faults, the characteristics of most algorithms are to repeat some operations for many times.

Introduction to IC Test

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