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Transcript of Introduction to Analog-Digital-Converter Dr.-Ing. Frank Sill Department of Electrical Engineering,...
Introduction toIntroduction to
Analog-Digital-ConverterAnalog-Digital-Converter
Dr.-Ing. Frank SillDepartment of Electrical Engineering, Federal University of Minas Gerais,
Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil
http://www.cpdee.ufmg.br/~frank/
Analog Digital Converter 2Copyright Sill, 2008
AgendaAgenda
Introduction Characteristic Values of ADCs Nyquist-Rate ADCs Oversampling ADC Practical Issues Low Power ADC Design
Analog Digital Converter 3Copyright Sill, 2008
IntroductionIntroduction
ADC = Analog-Digital-Converter Conversion of audio signals (mobile micro,
digital music records, ...) Conversion of video signals (cameras,
frame grabber, ...) Measured value acquisition (temperature,
pressure, luminance, ...)
Analog Digital Converter 4Copyright Sill, 2008
ADC - SchemeADC - Scheme
Sample & Hold
Quantizationfsample
Analog Digital
Analog input can be voltage or current (in the following only voltage) Analog input can be positive or negative (in the following only positive)
Analog Digital Converter 5Copyright Sill, 2008
2. Characteristic Values of ADCs2. Characteristic Values of ADCs
Which values characterize an ADC? What kind of errors exist? What is aliasing?
Analog Digital Converter 6Copyright Sill, 2008
ADC ValuesADC Values
Resolution N: number of discrete values to represent the analog values (in Bit) 8 Bit = 28 = 256 quantization level, 10 Bit = 210 = 1024 quantization level
Reference voltage Vref: Analog input signal Vin is related to digital output signal Dout through Vref with:
Vin = Vref · (D02-1 + D12-2 + … + DN-12-N)
Example: N = 3 Bit, Vref = 1V, Dout = ‘011’
=> Vin = 1V · ( 2-2 + 2-3) = 1V · (0.25 + 0.125) = 0.375V
ADCVin Dout = D0D1…DN-1
Vref
Analog Digital Converter 7Copyright Sill, 2008
ADC Values cont’dADC Values cont’d
VLSB : Minimum measurable voltage difference in ideal case (LSB – least significant Bit) VLSB = Vref / 2N
Vin = VLSB (D02N-1 + D12N-2 + … + DN-120)
Example: N = 3 Bit, Vref = 1V, Dout = ‘011’
=> VLSB = 1V / 23 = 0.125V
=> Vin = 0.125V · ( 21 + 20) = 0.125V · 3 = 0.375V
ΔV: Voltage difference between two logic level Ideal: all ΔV = VLSB
VFSR : Difference between highest and lowest measurable voltages (FSR – full scale range)
Analog Digital Converter 8Copyright Sill, 2008
ADC Values cont’dADC Values cont’d
SNR: Signal to Noise Ratio Ratio of signal power to noise power
ENOB: Effective Number of Bits Effective resolution of ADC under observance of all noise and
distortions
SINAD (SIgnal to Noise And Distortion) → ratio of fundamental signal to the sum of all distortion and noise (DC term removed)
Comparison of SINAD of ideal and real ADC with same word length
02.676.1SINAD
ENOB
, 10logsignal signal
dbnoise noise
P PSNR SNR
P P
Analog Digital Converter 9Copyright Sill, 2008
Ideal ADCIdeal ADC
000
001
010
011
100
101
110
111
8refV
Dig
ital O
utpu
t Dou
t
Analog Input Vin
7
8 refV4
8 refV
ΔV, VLSB
VFSR
Analog Digital Converter 10Copyright Sill, 2008
Further ADC Values Further ADC Values
Bandwidth: Maximum measurable frequency of the input signal
Power dissipation Conversion Time: Time for conversion of an analog
value into a digital value (interesting in pipeline and parallel structures)
Sampling rate (fsamp): Rate at which new digital values are sampled from the analog signal (also: sample
Errors: Quantization, offset, gain, INL, DNL, missing codes, non-monotonicity…
Analog Digital Converter 11Copyright Sill, 2008
Quantization Error Quantization Error εε
000
001
010
011
100
101
110
111
inV
2LSBV
2LSBV
7
8 refV
Dou
t
2 2LSB LSBV V
Analog Digital Converter 12Copyright Sill, 2008
Quantization Error (3-Bit Flash)Quantization Error (3-Bit Flash)
Eugenio Di Gioia, Sigma-Delta-A/D-Wandler, 2007
sample
sample
Am
plitu
deE
rror
Analog Digital Converter 13Copyright Sill, 2008
Offset ErrorOffset Error
Parallel shift of the whole curve E.g. caused by difference in ground line voltages
offset
000
001
010
011
100
101
110
111
8refV 4
8 refV7
8 refV
Dou
t
inV
Analog Digital Converter 14Copyright Sill, 2008
Gain ErrorGain Error
Corresponds to too small or to large but equal ΔV E.g. caused by too small or too large Vref
gain
000
001
010
011
100
101
110
111
8refV 4
8 refV7
8 refV
Do
ut
inV
Analog Digital Converter 15Copyright Sill, 2008
Differential Non-Linearity (DNL)Differential Non-Linearity (DNL)
Deviation of ΔV from VLSB value (in VLSB) Defined after removing of gain E.g. Caused by mismatch of the reference elements
000
001
010
011
100
101
110
111
8refV 4
8 refV7
8 refV
Dou
t
inV
1
2 LSBDNL V
1
2 LSBDNL V
VLSB
VLSB
1 1
2 2LSB LSBDNL V V V
1 1.5
2 LSB LSBDNL V V V
Analog Digital Converter 16Copyright Sill, 2008
Integral Non-Linearity (INL)Integral Non-Linearity (INL)
Deviation from the straight line (best-fit or end-point) (in VLSB) Defined after removing of gain and offset E.g. caused by mismatch of the reference elements
000
001
010
011
100
101
110
111
8refV 4
8 refV7
8 refV
Dou
t
inV
1
2 LSBINL V
1
4 LSBINL V
Analog Digital Converter 17Copyright Sill, 2008
Missing CodesMissing Codes
Some bit combinations never appear Occurs, if maximum DNL > 1 VLSB or maximum INL > 0.5 VLSB
000
001
010
011
100
101
110
111
8refV 4
8 refV7
8 refV
Do
ut
inV
Missing Code
Analog Digital Converter 18Copyright Sill, 2008
Non-MonotonicityNon-Monotonicity
Lower conversion result for a higher input voltage Includes that same conversion may result from two separate
voltage ranges
000
001
010
011
100
101
110
111
8refV 4
8 refV7
8 refV
Dou
t
inV
Non-Monotonicity
Ideal curve
Analog Digital Converter 19Copyright Sill, 2008
AliasingAliasing
Too small sampling rate fsamp (under-sampling) can lead to aliasing ( = frequency of reconstructed signal is to low)
Nyquist criterion: fsamp more than two times higher than highest
frequency component fin of input signal: fsamp > 2·fin
Input signal (with fin)
Reconstructed output signal
Measured data points (sample rate: fsamp)
Analog Digital Converter 20Copyright Sill, 2008
3. Nyquist-Rate ADCs3. Nyquist-Rate ADCs
How can Nyquist-rate ADCs be grouped? What is a dual slope ADC? What is a successive approximation ADC? What is an algorithmic ADC? What is a flash ADC? What is a pipelined ADC? What are the pros and cons of the
Nyquist-rate ADCs?
Analog Digital Converter 21Copyright Sill, 2008
Nyquist-Rate ADCsNyquist-Rate ADCs
Sampling frequency fsamp is in the same range as frequency fin of input signal
Low-to-medium speed and high accuracy ADCs Integrating
Medium speed and medium accuracy ADCs Successive Approximation Algorithmic
High speed and low-to-medium accuracy ADCs Flash Two-Level Flash Pipelined
Analog Digital Converter 22Copyright Sill, 2008
Integrating (Dual Slope) ADCsIntegrating (Dual Slope) ADCs
Phase 1: Integration (capacitor C1) of Vin in known time Tload Qload = Vin / R1 · Tload
Phase 2: Integration of reference voltage -Vref until Vout = 0 and estimation of time ΔT Qref = -Vref / R1 · ΔT = -Qload => Vin = Vref · ΔT / Tload
Independent of R1 und C1!
Vin
-Vref
S1
S2
C1
Controllogic Counter
Comparator
D0
D1
D2
D3
DN-1Integrator
Vout
R1
Analog Digital Converter 23Copyright Sill, 2008
Integrating (Dual Slope) ADCs cont’dIntegrating (Dual Slope) ADCs cont’dV
olta
ge
Time
Vin3
Vin2
Vin1
Phase 1 Phase 2
ΔT1
ΔT2
ΔT3
Tload
constant slope
slope depends on Vin
Analog Digital Converter 24Copyright Sill, 2008
Integrating ADCs: pros and consIntegrating ADCs: pros and cons
Simple structure (comparator and integrator are the only analog components)
Low Area / Low Power
Slow
Time intervals are not constant
Analog Digital Converter 25Copyright Sill, 2008
Successive Approximation ADCSuccessive Approximation ADC
Generate internal analog signal VD/A
Compare VD/A with input signal Vin
Modify VD/A by D0D1D2…DN-1 until closest possible value
to Vin is reached
S&HLogic
DAC
D0 D1 DN-1
Vin
Vref
VD/A
Analog Digital Converter 26Copyright Sill, 2008
Successive Approximation ADC cont’dSuccessive Approximation ADC cont’d
S&HLogic
DAC
D0 D1 DN-1
Vin
Vref
VD/A
Comparsion of VD/A with2
Vref
2 in
VrefV
2 in
VrefV
Comp. w. 4
Vref Comp. w. 3
4
Vref
4 in
VrefV
4 in
VrefV 4 in
VrefV
4 in
VrefV
Analog Digital Converter 27Copyright Sill, 2008
Successive Approximation ADC cont’dSuccessive Approximation ADC cont’d
P. Fischer, VLSI-Design - ADC und DAC, Uni Mannheim, 2005
Iterations
inV
8refV
4
8 refV
7
8 refV
1. 2. final result
VD/A
100
110
010
111
101
011
001
111
110
101
100
011
010
001
0003.
Analog Digital Converter 28Copyright Sill, 2008
Successive Approx.: pros and consSuccessive Approx.: pros and cons
Low Area / Low Power
High effort for DAC
Early wrong decision leads to false result
Analog Digital Converter 29Copyright Sill, 2008
Algorithmic ADCAlgorithmic ADC
Same idea as successive approximation ADC Instead of modifying Vref → doubling of error
voltage (Vref stays constant)
Vin S&H
S&HX2
S1
Vref/4
-Vref/4S2
D0 D1 DN-1
Shift register
Analog Digital Converter 30Copyright Sill, 2008
Algorithmic ADC con’tAlgorithmic ADC con’tStart
Sample V = Vin, i = 1
Di = 1
V > 0
Di = 0
V = 2(V - Vref/4) V = 2(V + Vref/4)
i = i+1
i > N
Stop
yes
no
yes
Vin
S&H
X2
S1
Vref/4-Vref/4
S2
D0 D1 DN-1
Shift register
no
S&H
D.A.. Johns, K. Martin, Analog Integrated Circuit design, John Wiley & Sons, 1997
Analog Digital Converter 31Copyright Sill, 2008
Algorithmic ADC: pros and consAlgorithmic ADC: pros and cons
Less analog circuitry than Succ. Approx. ADC
Low Power / Low Area
High effort for multiply-by-two gain amp
Analog Digital Converter 32Copyright Sill, 2008
Flash ADCFlash ADC
Vin
Vref
Over range
D0
D1
DN-1
(2N-1) to N encoder
R/2
R
R/2
R
R
R
R
R
R
Vin connected with 2N comparators in parallel
Comparators connected to resistor string
Thermometer code R/2-resistors on bottom
and top for 0.5 LSB offset
Analog Digital Converter 33Copyright Sill, 2008
Some Flash ADC design issuesSome Flash ADC design issues
Input capacitive loading on Vin
Switching noise if comparators switch at the same time
Resistors-string bowing by input currents of bipolar comparators (if used)
Bubble errors in the thermometer code based on comparator’s metastability
Analog Digital Converter 34Copyright Sill, 2008
Flash ADC: pros and consFlash ADC: pros and cons
Very fast
High effort for the 2N comparators
High Area / High Power
Recommended for 6-8 Bit and less
Analog Digital Converter 35Copyright Sill, 2008
Two-Level Flash ADCTwo-Level Flash ADC
Conversion in two steps:
1. Determination of MSB-Bits and reconverting of digital signal by DAC
2. Subtraction from Vin and determination of LSB-Bits F.e. 8-Bit-ADC: Flash: 28=256 comparators, Two-level:
2·24 = 32 comparators
N/2-Bit Flash ADC x2N
MSB (D0 … DN/2-1) LSB (DN/2 … DN-1)
N/2-Bit Flash ADC
gain amp
VinN/2-Bit DAC
Analog Digital Converter 36Copyright Sill, 2008
Two-Level Flash ADC: pros and consTwo-Level Flash ADC: pros and cons
Same throughput as Flash ADC Less area, less power, less capacity loading
than Flash ADC Easy error-correction after first stage
Larger latency delay than Flash ADC Design of N/2-Bit-DAC
Currently most popular approach for high-speed/medium accuracy ADCs
Analog Digital Converter 37Copyright Sill, 2008
Pipelined ADCsPipelined ADCs
Extension of two-level architecture to multiple stages (up-to 1 Bit per stage)
Each stage is connected with CLK-signal Pipelined conversion of subsequent input signals First result after m CLK cycles (m - amount of stages)
Stages can be different
Stage 1 Stage 2 Stage mVin,0 Vin,1 Vin,m-1
CLK
D0 – Dk-1 Dk – D2k-1 Dmk – DN-1
Analog Digital Converter 38Copyright Sill, 2008
Pipelined ADCs: SchemePipelined ADCs: Scheme
k-Bit ADC
k-Bit DAC
x2k
k Bits
Vin,i
Stage 1
S&H
Stage 2 Stage mVin,0
Vin,i+1
Vin,1 Vin,m-1
Time Alignment & Digital Error Correction
D0 D1 DN-1
CLK
CLK
Analog Digital Converter 39Copyright Sill, 2008
Pipelined ADC: pros and consPipelined ADC: pros and cons
High throughput
Easy upgrade to higher resolutions
High demands on speed and accuracy on gain amplifier
High CLK-frequency needed
High Power
Analog Digital Converter 40Copyright Sill, 2008
4. Oversampling ADCs4. Oversampling ADCs
What are the problems of the quantization noise?
How does oversampling work? What is noise shaping? What is a sigma-delta ADC?
Analog Digital Converter 41Copyright Sill, 2008
Quantization Error Quantization Error ε ε (recap)(recap)
000
001
010
011
100
101
110
111
inV
2LSBV
2LSBV
7
8 refV
Dou
t
2 2LSB LSBV V
Analog Digital Converter 42Copyright Sill, 2008
Quantization NoiseQuantization Noise
Quantization error ε with probability density p(ε) can be approximated as uniform distribution
/ 2
/ 2
1
1ˆ
LSB
LSB
V
V
LSB
p d
pV
p(ε)
2LSBV
2LSBV ε
p̂
Analog Digital Converter 43Copyright Sill, 2008
Quantization Noise cont’dQuantization Noise cont’d Quantization noise reduces Signal-Noise-Ration (SNR) of ADC Estimation of SNR with Root Mean Square (RMS) of input signal (Vin_RMS) and of noise signal (Vqn_RMS)
SNR = Vin_RMS / Vqn_rms
Every additional Bit halves VLSB → Vqn_RMS decreases by 6 dB with every new Bit F.e. Vin is sinusoidal wave → SNR = (6.02 N + 1.76) dB
1/ 21/ 2 / 2
2 2_
/ 2
1
12
LSB
LSB
V
LSBqn RMS
LSB V
VV p d d
V
Analog Digital Converter 44Copyright Sill, 2008
Quantization Noise cont’dQuantization Noise cont’d
Quantization noise can be approximated as white noise Spectral density Sε(f) of quantization noise is constant
over whole sampling frequency fs
Quantization noise power
Sε(f)
2sf
2sf f
1
12LSB
s
VS
f
/ 2 2
2
/ 212
s
s
f
LSB
f
VP S f df
Analog Digital Converter 45Copyright Sill, 2008
Quantization Error (3-Bit Flash, recap)Quantization Error (3-Bit Flash, recap)
Eugenio Di Gioia, Sigma-Delta-A/D-Wandler, 2007
sample
sample
Am
plitu
deE
rror
Analog Digital Converter 46Copyright Sill, 2008
Oversampling (OS)Oversampling (OS)
Quantized signal is low-pass filtered to frequency f0
elimination of quantization noise greater than f0
Oversampling rate (OSR) is ratio of sampling frequency fs to Nyquist rate of f0
2sf
2sf fH(f)
|H(f)|
0
2f0
2f
1Vin(f)
02sfOSRf
Analog Digital Converter 47Copyright Sill, 2008
OS in Frequency DomainOS in Frequency Domain
Pow
er
fs/2 = OSR·f0/2f0/2 f
Digital filter response
Oversampling
Po
we
r
f0/2 f
Signal amplitude
Average quantization noise
Analog Digital Converter 48Copyright Sill, 2008
Oversampling cont’dOversampling cont’d
Quantization noise power Pε results to:
Doubling of fs increases SNR by 3 dB Equivalently to a increase of resolution by 0.5 Bits
F.e. Vin is sinusoidal wave SNR = (6.02 N + 1.76 + 10log [OSR]) dB
0
0/ 2 / 2 222 2
/ 2 / 2
1( ) ( )
12s
sf f
LS
f
B
f
VP S f H f df S df
OSR
Analog Digital Converter 49Copyright Sill, 2008
OS signal reconstructionOS signal reconstruction
Signal results from relation of “0”s and “1”s
n
Nyquist -ADC
Oversampling - ADC
1V
0.66 V
0.33 V
Nyquist - ADC
Oversampling 00000011111111110000000
0.33 0.33
x[n]
2 2
_
0.33 0.33
2RMS NyquistV 2 2 2 2
_
5 1 7 0 5 1 7 0
24RMS OversamplingV
Analog Digital Converter 50Copyright Sill, 2008
Noise Shaping (NS)Noise Shaping (NS)
Next trick: feedback loop Quantization noise signal is negative coupled with input
Based on high gain of closed-loop at low frequencies: Quantization noise reduced at low frequencies Quantization noise is ”shaped” = moved to higher frequencies
H(z)
Integrator Quantizer
DAC
X YE
1 1
1 1H
Y X E X HH H
Analog Digital Converter 51Copyright Sill, 2008
Noise Shaping cont’dNoise Shaping cont’d
Oversampling and noise shaping: Doubling of fs increases SNR by 9 dB
Equivalently to a increase of resolution by 1.5 Bits
F.e. Vin is sinusoidal wave SNR = (6.02 N + 1.76 – 5.17 + 30log [OSR]) dB
up to fin = 100 kHz (and more)
1-Bit Quantizer (Comperator) 1-Bit DAC
Analog Digital Converter 52Copyright Sill, 2008
OS and NS in Frequency DomainOS and NS in Frequency Domain
Pow
erfs/2 = OSR·f0/2f0/2 f
Digital filter response
Oversampling
Pow
er
fs/2f0/2 f
Oversampling and noise shaping
Po
we
r
f0/2 f
Signal amplitude
Average quantization noise
Analog Digital Converter 53Copyright Sill, 2008
DAC
Comparator
Vref = 2.5 V
Vin = 1.2 V
inv t t dt inv t t
Sigma Delta ADC Example Sigma Delta ADC Example
1.2
-1.3
3.7
-1.3
1.2
-0.1
3.6
2.3
1
0
1
1
2.5-2.5 2.52.5
Analog Digital Converter 54Copyright Sill, 2008
Sigma Delta ADC Example (Curves)Sigma Delta ADC Example (Curves)
http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma_D.html
H(z)
Integrator1B
it -QuantizerCLK
DA
C
Analog Digital Converter 55Copyright Sill, 2008
Sigma Delta ADC: pros and consSigma Delta ADC: pros and cons
High resolution
Less effort for analog circuitry
Low speed
High CLK-frequency
Currently popular for audio applications
Analog Digital Converter 56Copyright Sill, 2008
5. Practical issues5. Practical issues
What are the performance limitations of ADCs?
What are the differences between PCB- and IC-designs?
Are there hints to improve the ADC design?
What are S&H circuits?
Analog Digital Converter 57Copyright Sill, 2008
Performance LimitationsPerformance Limitations
Analog circuit performance limited by: High-frequency behavior of applied components Noise
Crosstalk (analog ↔ analog, analog ↔ digital) Power supply coupling Thermal noise (white noise)
Parasitic components (capacitances, inductivities) Wire delays
Analog Digital Converter 58Copyright Sill, 2008
Parasitic Component ExampleParasitic Component Example
Effect of 1pF capacitance on inverting input of an opamp:
Mancini, Opamps for everyone, Texas Instr., 2002
Analog Digital Converter 59Copyright Sill, 2008
Noise Demands ExamplesNoise Demands Examples
Example 1: Vref = 5V, 10 Bit resolution
VLSB = 5V / 210 = 5V / 1024 = 4.9 mV
Every noise must be lower than 4.9 mV
Example 2: Vref = 5V, 16 Bit resolution
VLSB = 5V / 216 = 5V / 65536 = 76 µV
Every noise must be lower than 76 µV
Analog Digital Converter 60Copyright Sill, 2008
PCB- versus IC-DesignPCB- versus IC-Design
PCB: Printed Circuit Board, IC: Integrated Circuit Noise in PCB-circuits much higher than in ICs Influences of parasitics in PCB-circuits much
higher than in ICs High-frequency behavior of PCB-circuits much
worse than of ICs Wire delays in PCB much higher than in ICs
High accuracy, high speed, high bandwidth ADCs only possible in ICs!
Analog Digital Converter 61Copyright Sill, 2008
For PCB and IC: Keep ground lines separate! Don’t overlap digital and analog signal wires!
Don’t overlap digital and analog supply wires! Locate analog circuitry as close as possible to the I/O
connections! Choose right passive components for high-frequency
designs! (only PCB)
Some Hints for Mixed Signal DesignsSome Hints for Mixed Signal Designs
Mancini, Opamps for everyone, Texas Instr., 2002
Analog Digital Converter 62Copyright Sill, 2008
Sample and Hold CircuitsSample and Hold Circuits
S&H circuits hold signal constant for conversion A sample and a hold device (mostly switch and
capacitor) Demands:
Small RC-settling-time (voltage over hold capacitor has to be fast stable at < 1 LSB)
Exact switching point (else “aperture-error”) Stable voltage over hold capacitor (else “droop error”) No charge injection by the switch
Analog Digital Converter 63Copyright Sill, 2008
6. Low Power ADC Design6. Low Power ADC Design
What are the main components of power dissipation?
How can each component be reduced? What are the differences between power
and energy?
Analog Digital Converter 64Copyright Sill, 2008
Power DissipationPower DissipationTwo main components: Dynamic power dissipation (Pdyn)
Based on circuit’s activity Square dependency on supply voltage VDD
2
Dependent on clock frequency fclk
Dependent on capacitive load Cload
Dependent on switching probability α
Pdyn = VDD2 · Cload · fclk · α
Static power dissipation (Pstatic) Constant power dissipation even if circuit is inactive Steady low-resistance connections between VDD und GND
(only in some circuit technologies like pseudo NMOS) Leakage (critical in technologies ≤ 0.18 µm)
Analog Digital Converter 65Copyright Sill, 2008
Low Power ADC DesignLow Power ADC Design
Reduction of VDD: Highest influence on power (P ~ VDD
2)
Sadly, delay increases (td ~ 1/VDD )
Sadly, loss of maximal amplitude → SNR goes down Possible solutions:
Different supply voltages within the design Dynamic change of VDD depending on required
performance
Reduction of fclk: Dynamic change of fclk
Analog Digital Converter 66Copyright Sill, 2008
Low Power ADC Design cont’dLow Power ADC Design cont’d
Reduction of Cload: Cload depends on transistor count and transistor size,
wire count and wire length Possible Solutions:
Reduction of amount evaluating components Sizing of the design = all transistor get minimum
size to reach desired performance Intelligent placing and routing
Analog Digital Converter 67Copyright Sill, 2008
Low Power ADC Design cont’dLow Power ADC Design cont’d
Reduction of α: Activity = possibility that a signal changes within one
clock cycle Possible Solutions:
Clock gating → no clock signal to inactive blocks High active signals connected to the end of blocks
Asynchronous designs
Analog Digital Converter 68Copyright Sill, 2008
Which ADC for Low Power?Which ADC for Low Power?
If low speed: Dual Slope ADC Area is independent of resolution Less components Problem: Counter
If medium / high speed: mixed solutions Popular: pipelined ADC with SAR Pipelined solutions allows reduction of VDD
Long latency but high throughput
Analog Digital Converter 69Copyright Sill, 2008
Power vs. EnergyPower vs. Energy
Power consumption in Watts Power = voltage · current at a specific time point Peak power:
Determines power ground wiring designs and Packaging limits
Impacts of signal noise margin and reliability analysis
Energy consumption in Joules Energy = power · delay (joules = watts * seconds) Rate at which power is consumed over time Lower energy number means less power to perform a
computation at the same frequency
Analog Digital Converter 70Copyright Sill, 2008
Power vs. Energy cont’dPower vs. Energy cont’d
Watts
time
Power is height of curve
Watts
time
Energy is area under curve
Approach 1
Approach 2
Approach 2
Approach 1
Analog Digital Converter 71Copyright Sill, 2008
Power vs. Energy: Simple ExamplePower vs. Energy: Simple Example
VDD I (each gray block) Delay Power Energy
Flash 1 V 1 µA 1 ns 4 µW 4 fJ
2L-Flash 1 V 1 µA 2.5 ns 2 µW 5 fJ
VDDVin
I
Vin
VDD
I
Flash 2L-Flash
Shaded blocks are ignored
Dissipation for one input signal:
Analog Digital Converter 72Copyright Sill, 2008
Low Power ADCs ConclusionLow Power ADCs Conclusion
There is no patent solution for low power ADCs! Every solution depends on the specific task. Before optimization analyze the problem:
Which resolution?Which speed?What are the constraints (area, energy, VDD, Vin,…)?
Which technology can be used?
Think also about unconventional solutions (dynamic logic, asynchronous designs, …).
Analog Digital Converter 73Copyright Sill, 2008
Open QuestionsOpen Questions
Is there another way to design low power ADCs? Is it recommended to reduce the analog part and
put more effort in the digital part? How do I achieve a high SNR with low power
ADCs? Is it better to have only one block with high
frequency or many blocks with low frequency? How can asynchronous designs help me? How do I realize a low power ADC in sub-micron
technologies?
Analog Digital Converter 74Copyright Sill, 2008
Basic ADC LiteratureBasic ADC Literature
[All02] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design”, Oxford University Press, 2002
[Azi96] P.M. Aziz, H. V. Sorensen, J. Van der Spiegel, "An Overview of Sigma-Delta Converters" IEEE Signal Processing Magazine, 1996
[Eu07] E. D. Gioia, “Sigma-Delta-A/D-Wandler”, 2007
[Fi05] P. Fischer, “VLSI-Design 0405 - ADC und DAC”, Uni Mannheim, 2005
[Man02] Mancini, “Opamps for everyone”, Texas Instr., 2002
[Joh97] D. A. Johns, K. Martin, “Analog Integrated Circuit design”, John Wiley & Sons, 1997
[Tan00] S. Tanner, “Low-power architectures for single-chip digital image sensors”, dissertation, University of Neuchatel, Switzerland, 2000.
Analog Digital Converter 76Copyright Sill, 2008
Signal ReconstructionSignal Reconstruction
Continuous time (input signal):
Discrete (reconstructed by ADC):
/ 2 2
_
/ 2
( )T
RMS ct
T
v tV dt
T
v(t)
time
2
0_
[ ]n
iRMS discrete
x nV
n
x[n]
n
RMS: root mean square
Analog Digital Converter 77Copyright Sill, 2008
Voltage supply reduction Voltage supply reduction [Tan00] [Tan00]
For analog design, it is shown that a voltage supply reduction does not always lead to a power consumption reduction for several reasons: Threshold of MOS
transistors. Loss of maximal amplitudes
(SNR degradation). Limits of conduction in
analog switches. Low speed of MOS
transistors. Limited stack of transistors.
0
0.5
1
1.5
2
2.5
3
0 1 2 3 4 5 6
Supply Voltage [V]
Po
we
r D
iss
ipa
tio
n [
mW
/MS
/s]
Power consumption of 10-bit S-C 1.5 bit/stage pipelined ADCs infunction of the voltage supply.
[Tan00] S. Tanner, Low-power architectures for single-chip digital image sensors, dissertation, University of Neuchatel, Switzerland, 2000.