Internal Block Diagram of 8086

8/18/2019 Internal Block Diagram of 8086

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8086 Microprocessor

• It is a 16 bit μp.

• 8086 has a 20 bit address bus can access upto

220 memory locations ( 1 MB) .

• It can support upto 64 I!" ports.

• It pro#ides 14$ 16%bit re&isters.

• It has multiple'ed address and data bus


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Architecture of 8086

Internal Block Diagram of 8086

• Internal bloc dia&ram can be partitioned

to 2 parts

– Bus Interace *nit (BI*)

– +'ecution *nit(+*)


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8086 – Internal Architecture

D H

S I

I n t e r n a l b u s

I P

C L

C o n t r o l S y s t e m

C S

A H

C H

S S

A L U

Q u e u e

D S

5

O p e r a n d s

2

A L :

3

F l a s

!

I n t e r n a l " u s

" I U

#

D L

$ e m o r yI n t e r % a & e

S P

" H

' S

" L

D I

I n t e r n a l b u s

" P

5

' U

• EU - Execution Unit

– General Purpose Registers

– Pointer Registers

– Index Registers

– ALU

– Flags

• BIU-Bus Interface Unit

– Segment Registers

• CS, DS, ES, SS, IP

– Queue

• Memory Addressing

– Segment Base

– !!set


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EU & BIU

• ,he 8086 -* lo&ic has been partitioned into t/o unctional

units namely Bus Interace *nit (BI*) and +'ecution *nit (+*)

• ,he maor reason or this separation is to increase the

processin& speed o the processor

• ,he BI* has to interact with memor an! input an!

output de#ices in etchin& the instructions and data reuired

by the +*

• +* is responsible or e"ecuting the instructions o the

pro&rams and to carry out the reuired processin&


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E"ecution Unit

• -ontrol unit is responsible or the co%ordination o

all other units o the processor

• 3* perorms #arious arithmetic and lo&ical

operations o#er the data

• ,he instruction decoder translates the

instructions etched rom the memory into aseries o actions that are carried out by the +*


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7

AH AL

BH BL

CH CL

DH DL

SP

BP

SI

DI

8 bits 8 bits

16 bits

Accumulator

Base

Count

Data

Stack Pointer

Base Pointer

Source Index

Destination Index

AX

BX

CX

DX

Pointer

Index

8 bits 8 bits

16 bits

Accumulator

Base

Count

Data

Stack Pointer

Base Pointer

Source Index

Destination Index

E#E$U%I' U'I% – )eneral /urpose .egisters


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• Each of these 61(it registers arefurther su(!i2i!e! into two 81(itregisters+

)eneral /urpose .egisters

A3 A-

B3 B-

$3 $-

D3 D-

A#

B#

$#

D#

8


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• A# .egister, A# register is also known asaccumulator register that stores operan!s forarithmetic operation like !i2i!e!* rotate+

• B# .egister, %his register is mainl use! as a(ase register+ It hol!s the starting (ase locationof a memor region within a !ata segment+

• $# .egister, It is !e4ne! as a counter+ It is

primaril use! in loop instruction to store loopcounter+

• D# .egister, D# register is use! to containI5 port a!!ress for I5 instruction+

)eneral /urpose .egisters

9


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E"ecution Unit 1.egisters

• eneral re&isters are used or temporary stora&e

and manipulation o data and instructions

• ccumulator re&ister consists o t/o 8%bit

re&isters 3 and 5$ /hich can be combined

to&ether and used as a 16%bit re&ister

• ccumulator can be used or I!" operations andstrin& manipulation


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• Base re&ister consists o t/o 8%bit re&isters B3 and B5$

/hich can be combined to&ether and used as a 16%bit

re&ister B

• B re&ister usually contains a data pointer used or based$based inde'ed or re&ister indirect addressin&

• -ount re&ister consists o t/o 8%bit re&isters -3 and -5$

/hich can be combined to&ether and used as a 16%bit

re&ister -

• -ount re&ister can be used as a counter in strin&

manipulation and shit!rotate instructions


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• 7ata re&ister consists o t/o 8%bit re&isters 73

and 75$ /hich can be combined to&ether and

used as a 16%bit re&ister 7

• 7ata re&ister can be used as a port number in I!"

operations

• In inte&er 2%bit multiply and di#ide instructionthe 7 re&ister contains hi&h%order /ord o the

initial or resultin& number


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/ointer & In!e" .egister

7+ tack /ointer /7*

97+ Base /ointer B/7*

:7+ ource In!e" I7*

;7+ Destination In!e" DI7+

14


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16

EXECUTION UNIT – Fla !eister

• A flag is a flip flop whih i!"iat#s so$# o!"itio!s p%o"&#" b'

th# #(#&tio! of a! i!st%&tio! o% o!t%ols #%tai! op#%atio!s of

th# )* +

• I! 8,86 -h# )* o!tai!s

a 16 bit flag %#gist#%

9 of th# 16 a%# ati.# flags a!" %#$ai!i!g 7 a%# &!"#fi!#"+

6 flags i!"iat#s so$# o!"itio!s/ stat&s flags

0 flags –o!t%ol lags

U U U U <

D<

I< %< < >< U A<

U /< U $<

Carr"

O#er $lo% DirectionInterru&t

Tra&

Sin

'eroAuxiliar"

Parit"

U ( Unused


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17

Flag Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Carry Flag

This flag is set, when there isa carry out of MS in case of

a!!ition or a "orrow in caseof su"traction#

Parity Flag

This flag is set to 1, if the lower"yte of the result contains e$ennu%"er of 1&s ' for o!! nu%"erof 1&s set to (ero#

Auxiliary Carry Flag

This is set, if there is a carry fro% thelowest ni""le, i#e, "it three !uringa!!ition, or "orrow for the lowestni""le, i#e, "it three, !uringsu"traction#

Zero Flag

This flag is set, if the result ofthe co%)utation or co%)arison)erfor%e! "y an instruction is(ero

Sign Flag

This flag is set, when theresult of any co%)utation

is negati$e

Trap Flag*f this flag is set, the )rocessor

enters the single ste) e+ecution%o!e "y generating internalinterru)ts after the e+ecution ofeach instruction

Interrupt Flag

auses the 8086 to recogni(ee+ternal %as- interru)ts' clearing *.

!isa"les these interru)ts#

Direction FlagThis is use! "y string %ani)ulation instructions# *f this flag "itis /0&, the string is )rocesse! "eginning fro% the lowesta!!ress to the highest a!!ress, i#e#, auto incre%enting %o!e#

therwise, the string is )rocesse! fro% the highest a!!resstowar!s the lowest a!!ress, i#e#, auto incre%enting %o!e#

Over flow Flag

This flag is set, if an o$erflow occurs, i#e, if the result of a signe!o)eration is large enough to acco%%o!ate in a !estination

register# The result is of %ore than 7"its in si(e in case of 8"itsigne! o)eration an! %ore than 15"its in si(e in case of 16"it

sign o)erations, then the o$erflow will "e set#


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18

BIU7

-ontains

• 61(te Instruction ?ueue ?7• %he egment .egisters $* D* E* 7+

• %he Instruction /ointer I/7+

• %he A!!ress umming (lock @7


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BIU – Instruction Bte?ueue

• 8086 instructions #ary rom 1 to 6 bytes

• ,hereore etch and e'ecution are tain& place

concurrently in order to impro#e the perormance

o the microprocessor

• ,he BI* eeds the instruction stream to the

e'ecution unit throu&h a 6 byte preetch ueue


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BIU – Instruction Bte?ueue

• +'ecution and decodin& o certain instructions !o not

reuire the use of (uses

• 9hile such instructions are e'ecuted$ the BIU fetches up

to si" instruction (tes or the ollo/in& instructions(the subseuent instructions)

• ,he BI* store these preetched bytes in a :rst%in%:rst out

re&ister by name instruction byte ueue

• 9hen the +* is ready or its ne't instruction$ it simply

reads the instruction byte(s) or the instruction rom the

ueue in BI*


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Instruction /ointer

• ,he Instruction ointer (I) in 8086 acts as a ro&ram

-ounter.

• It points to the a!!ress of the ne"t instruction to (e

e"ecute!.

• Its content is automatically incremented /hen the

e'ecution o a pro&ram proceeds urther.

• ,he contents o the I and -ode ;e&ment


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22

egmente!Memor

Co"# s#g$#!t 364B

Data s#g$#!t 364B

)(t%a s#g$#!t 364B

Sta s#g$#!t 364B

)

*B

()e memory *n an +,+-.++ based

system *s oran*/ed as semented

memory0

()e CPU +,+- *s able to address

!$byte o% memory0

()e Complete p)ys*&ally a1a*lable

memory may be d*1*ded *nto a

number o% lo*&al sements0

+++++

FFFFF

P,"sical *emor"


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egment, =set'otation

• ,he total addressable memory si>e is 1MB

• Most o the processor instructions use 16%bit

pointers the processor can e?ecti#ely address

only 64 B o memory

• ,o access memory outside o 64 B the -* uses

special se&ment re&isters to speciy /here thecode$ stac and data 64 B se&ments are

positioned /ithin 1 MB o memory


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• %here are four segment registers in Intel 8086@

7+ $o!e egment .egister $7*

97+ Data egment .egister D7*:7+ tack egment .egister 7*

;7+ E"tra egment .egister E7+

egment .egisters

24


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• A segment register points to the starting

a!!ress of a memor segment+

•


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$o!e segment $7,1

• It is a 61(it register containin& address o 64 B

se&ment /ith processor instructions.

• ,he processor uses $ segment or all accesses to

instructions reerenced by instruction pointer I/7

register.

• -; re&ister cannot (e change! !irectl. ,he -;

re&ister is automaticall up!ate! !uring far

Cump$ ar call and ar return instructions

egment .egister

26


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tack segment 7,1

• It is a 61(it register containin& address o 64B

se&ment /ith pro&ram stac.

• By deault$ the processor assumes that all data

reerenced by the stack pointer /7 an! (ase

pointer B/7 registers is located in the stac

se&ment.

• ;; re&ister can (e change! !irectl usin& "

instruction.

egment .egister

27


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Data segment D7,1


se&ment /ith pro&ram data.

• By deault$ the processor assumes that all data

reerenced by general register B# an! in!e"

register I* DI7 is located in the data se&ment.

egment .egister

28


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E"tra segment E7,1


se&ment$ usually /ith pro&ram data.

• By deault$ the processor assumes that the DI

register reerences the +; se&ment in strin&

manipulation instructions.

egment .egister

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ummar o eg s ers pe ne o


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00

ummar o eg s ers pe ne o/

A- A.

B- B.

C- C.

D- D.

SP

BP

SIDI

F.A/S

D

EC

O

D

E

!

A.U

AX

BX

CX

DX

EUEU

Timin

control

SP

BP

De$ault Assinment

BIUBIU

IP

CS DS ES SS

0UEUE

IP BX

DI

SI

DI

Internal Block Diagram of 8086

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