Pin diagram 0f 8086 Microprocessor or The hardware model of 8086.docx

7/24/2019 Pin diagram 0f 8086 Microprocessor or The hardware model of 8086.docx

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Pin diagram 0f 8086 Microprocessor or The hardware model of 8086

Friday, November 18, 2011 Microprocessor and Assembly Language Programming 2 CommentsPin diagram o 808!microprocessor

"#e 808! is a 1!$bit microprocessor intended to be used as t#e CP% in a microcomputer& "#e808! Microprocessor$ 'nternal Arc#itectures#o(s t#e details o internal arc#itecture& Follo(ingigure s#o(s t#e logical pin diagram o 808! microprocessor& All t#e signals can be classiiedinto si) groups* 1& Po(er supply and re+uency signals& 2& Cloc signal -& Address bus& .& /atabus& &Mode selection& !& Control and status signals& & )ternally initiated signals, includinginterrupts&

Fig* 808! and pin diagram

1. Power supply and frequency signals

3cc is on pin .0 supplies 43 po(er supply&Pin 1 and 20 or ground reerence&

2. Clock signal

Pin 15 or cloc input 6CL7* an 808! re+uires a cloc signal rom some e)ternal, crystal$controlled cloc generator to sync#roni9e internal operations in t#e processor (it# ma)imumre+uencies ranging rom M:; to 10 M:;&

. Mul!iple"ed address#da!a $us

A/0 t#roug# A/1 are used at t#e start o mac#ine cycle to send out addresses and later in t#emac#ine cycle t#ey are used to send or receive data& 6"#is is also no(n as multiple)ing t#e

bus& :o(ever, t#e$lo( order address bus can be separated rom t#ese signals by using a latc#&%. Mul!iple"ed address &us

"#e 808! #as . signal lines A1!


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MNMX>>>>>>>>>>input on pin --& ' pin is asser!edhigh, t#en t#e 808! (ill unction in minimum mode, andpins 2. t#roug# -1 (ill #ave t#e unctions s#o(n in parent#eses ne)t to t#e pins i&e&

INTA>>>>>>>>>>>>>>,AL,

DEN>>>>>>>>>>>>,DT>>>,M>>>>>,WR>>>>>>>>>,

:L/A, and :?L/& ' t#e 808! is in minimum mode in systems, it (ors as a singlemicroprocessoron t#e system buses&' t#e

MNMX>>>>>>>>>>pin is asserted lo(, t#en t#e 808! is in ma"imum mode& 'n t#is mode pins 2. t#roug# -1 (ill#ave t#e unctions described by t#e mnemonics ne)t to t#e pins i&e& @=1, @=0,

S0>>>>>>,

S1>>>>>>,S2>>>>>>,LOCK>>>>>>>>>>>>>>>,

RQ>>>>>>>>>>>>>>>>>,and

RQ>>>>>>>>>>>>>>>>>&' t#e 808! is in ma)imum mode in systems, it #as !wo or moremicroprocessors sharing !hesame &uses and t#is mode is calledmul!iprocessor mode.

6. Con!rol and s!a!us signal

"#is group o signals is to identiy t#e nature o t#e operations& "#ese signals are as ollo(s&a& AL$ Address Latc# nable 6pin 2* t#is is a positive going pulse generated every time t#e

808! begins an operation 6mac#ine cycle&"#is output signal indicates t#e availability o t#evalid address is on t#e address>>>>>>>

6pin -2 ead* "#is is read control signal 6active lo(& "#is signal indicates t#at t#e selected '


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&DEN>>>>>>>>>>>>

6pin 2! /ata nable signal* it is used to enable bidirectional buers on t#e data bus, (#en /N islo(& i&e& it send data out on t#e data bus and read t#e data in on t#e data bus&

g&

DTR>>>>6pin 2 /ata transmit>>>

is #ig#, t#e 808! is used to decide t#e direction in (#ic# t#e buers are enabled t#roug#t#e /N t#e 808! transmit t#e data to ?M, AM, or ports& (#en

DTR>>>>is lo(, t#e buers (ill allo( data to come in rom ?M, AM, and ports&

BHE>>>>>>>>>>>>


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t#e CP% to perorm arit#metic and logical 6AN/, ?, N?", compare, etc unctions&

"#e 808! CP% is organi9ed as t(o separate processors, called t#e us 'nterace %nit 6'% andt#e )ecution %nit 6%& "#e '% provides :


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*TC/ - *3*C,T*

Alt#oug# t#e 808!


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t#e 8088 or t(o 6(it# t#e 808! additional bytes& "#e advantage o t#is pipelined arc#itecture ist#at t#e % can e)ecute instructions almost continually instead o #aving to (ait or t#e '% toetc# a ne( instruction&

"#ere are t#ree conditions t#at (ill cause t#e % to enter a H(aitH mode& "#e irst occurs (#enan instruction re+uires access to a memory location not in t#e +ueue& "#e '% must suspendetc#ing instructions and output t#e address o t#is memory location& Ater (aiting or t#ememory access, t#e % can resume e)ecuting instruction codes rom t#e +ueue 6and t#e '% canresume illing t#e +ueue&

"#e second condition occurs (#en t#e instruction to be e)ecuted is a HumpH instruction& 'n t#iscase control is to be transerred to a ne( 6nonse+uential address& "#e +ueue, #o(ever, assumest#at instructions (ill al(ays be e)ecuted in se+uence and t#us (ill be #olding t#e H(rongHinstruction codes& "#e % must (ait (#ile t#e instruction at t#e ump address is etc#ed& Notet#at any bytes presently in t#e +ueue must be discarded 6t#ey are over(ritten&

?ne ot#er condition can cause t#e '% to suspend etc#ing instructions& "#is occurs duringe)ecution o instructions t#at are slo( to e)ecute& For e)ample, t#e instruction AAM 6A=C''Adust or Multiplication re+uires 8- cloc cycles to complete& At our cycles per instructionetc#, t#e +ueue (ill be completely illed during t#e e)ecution o t#is single instruction& "#e '%(ill t#us #ave to (ait or t#e % to pull over one or t(o bytes rom t#e +ueue beore resumingt#e etc# cycle&

A subtle advantage to t#e pipelined arc#itecture s#ould be mentioned& ecause t#e ne)t severalinstructions are usually in t#e +ueue, t#e '% can access memory at a some(#at HleisurelyH pace&"#is means t#at slo($mem parts can be used (it#out aecting overall system perormance&

P45-M)5 M4*

As a programmer o t#e 808! or 8088 you must become amiliar (it# t#e various registers in t#e% and '%&


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"#e data group consists o t#e accumulator and t#e E, CE, and /E registers& Note t#at eac#can be accessed as a byte or a (ord& "#us E reers to t#e 1!$bit base register but : reers onlyto t#e #ig#er 8 bits o t#is register& "#e data registers are normally used or storing temporaryresults t#at (ill be acted on by subse+uent instructions&

"#e pointer and inde) group are all 1!$bit registers 6you cannot access t#e lo( or #ig# bytesalone& "#ese registers are used as memory pointers& =ometimes a pointer reg (ill be interpreted

as pointing to a memory byte and at ot#er times a memory (ord& As you (ill see, t#e 808!


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7*5M*T* M*M4

ven t#oug# t#e 808! is considered a 1!$bit processor, 6it #as a 1!$bit data bus (idt# itsmemory is still t#oug#t o in bytes& At irst t#is mig#t seem a disadvantage*

B#y saddle a 1!$bit microprocessor (it# an 8$bit memoryI

Actually, t#ere are a couple o good reasons& First, it allo(s t#e processor to (or on bytes as(ell as (ords& "#is is especially important (it# '


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"#e diagram is called a memory map& "#is is because, lie a road map, it is a guide s#o(ing #o(t#e system memory is allocated& "#is type o inormation is vital to t#e programmer, (#o mustno( e)actly (#ere #is or #er programs can be saely loaded&

Note t#at some memory locations are mared reserved and ot#ers dedicated& "#e dedicated

locations are used or processing speciic system interrupts and t#e reset unction& 'ntel #as alsoreserved several locations or uture :


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any given instant a ma)imum o 2! 7 6!.7 K . bytes o memory can be utili9ed& As (e (illsee, t#e contents o t#e segment registers can only be speciied via =


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== K 1! 4 EEEE&

-9-T-5*7 4 7*5M*T* M*M4

=egmented memory can seem conusing at irst& B#at you must remember is t#at t#e programop$codes (ill be etc#ed rom t#e code segment, (#ile program data variables (ill be stored int#e data and e)tra segments& =tac operations use registers P or =P and t#e stac segment& As(e begin (riting programs t#e conse+uences o t#ese deinitions (ill become clearer&

An immediate advantage o #aving separate data and code segments is t#at one program can(or on several dierent sets o data& "#is is done by reloading register /= to point to t#e ne(data& Per#aps t#e greatest advantage o segmented memory is t#at programs t#at reerencelogical addresses only can be loaded and run any(#ere in memory& "#is is because t#e logicaladdresses al(ays range rom 00000# to 0FFFF#, independent o t#e code segment base& =uc#programs are said to be relocatable, meaning t#at t#ey (ill run at any location in memory& "#e

re+uirements or (riting relocatable programs are t#at no reerences be made to p#ysicaladdresses, and no c#anges to t#e segment registers are allo(ed&

E))))))))))))))))))))))))))))))))))))))))))))))))))))))

8086 pin diagram descrip!ion


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8086 Pin diagram -nd *"plana!ion

"#e 808! can operate in t(o modes t#ese are t#e minimum mode and ma)imum mode &Forminimum mode, a uni+ue processor system (it# a single 808! and or Ma)imum mode a multiprocessor system (it# more t#an one 808!&

M#M3: is an input pin used to select one o t#is mode &when M#M3 is hight#e 808!operates in minimum mode &'n t#is mode t#e 808! is conigured to support small singleprocessor system using a e( devices t#at t#e system bus &(#en M#M3 is low 808! isconigured to support multiprocessor system&

"#e -0:-1' lines are a 1!bit multiple)ed addressed or data bus& /uring t#e 1 stcloc cycleA/0$A/1 are t#e lo( order 1!it adders& "#e 808! #as a total o 20 address line ,t#e upper .lines are multiple)ed (it# t#e state signal t#at is-16#7 ; -1(#7% ; -18#7' ; -1< #76&/uring t#e


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irst cloc period o a best cycle t#e entire 20bit address is available on t#ese line& /uring allot#er cloc cycles or memory and i


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/4 and /4-

a #ig# on t#e :?L/ pin indicates t#at anot#er master is re+uired to tae over t#e =


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B#en Lo(, it indicates t#at 808! is in control o t#e bus& /uring a H:old acno(ledgeH cloc

period, t#e 808! tri$states t#e =! pin and t#us allo(s anot#er bus master to tae control o t#e

status bus&

S3 & S4:

Lines are decoded as ollo(s*

-1(#7% -16#7 unc!ion

0 0 )tra segment access

0 1 =tac segment access

1 0 Code segment access

1 1 /ata segment access

Ater t#e irst cloc cycle o an instruction e)ecution, t#e A1


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"#e ead strobe indicates t#at t#e processor is perorming a memory or '


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eady is t#e acno(ledgement rom t#e addressed memory or '


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'ndicates t#at t#e processor is perorming a (rite memory or (rite '? cycle, depending on t#e

state o t#e M


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ma)imum mode 6i&e&& MN


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0 0 No operation

0 1 First byte o opcode rom +ueue

1 0 mpty t#e +ueue

1 1 =ubse+uent byte rom +ueue

"able .

O2 (O)

't indicates to anot#er system bus master, not to gain control o t#e system bus (#ile L?C7 is

active Lo(& "#e L?C7 signal is activated by t#e HL?C7H prei) instruction and remains active

until t#e completion o t#e instruction& "#is signal is active Lo( and loats to tri$state ?FF

during G#old acno(ledgeG& )ample*

L?C7 EC:O reg&, Memory Q egister is any register and memory O"0 Q is t#e address o t#e semap#ore&

'0 a$d '1 (I/O): 'e+uest/>ra$t

"#ese pins are used by ot#er processors in a multi processor organi9ation& Local bus masters o

ot#er processors orce t#e processor to release t#e local bus at t#e end o t#e processors currentbus cycle& ac# pin is bi$directional and #as an internal pull up resistors& :ence t#ey may be let

un$connected&

Pin diagram 0f 8086 Microprocessor or The hardware model of 8086.docx

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