Intel 8086 Architecture -...

Microprocessors (A)80x86 Family Overview1

Dr. Martin LandHadassah CollegeFall 2004

Intel 8086 Architecture



“The x86 isn’t all that complex — it just doesn’t make a lot of sense.”

Mike Johnson, Leader of 80x86 Design at AMD, Microprocessor Report (1994)



Features of a Specific CPU

Main Memory

Registers

MAR MDR+PCIRDecoderStatusWord

Address DataPC - program counterIR - instruction register

MAR- memory address registerMDR- memory data register

ALU Subsystem

System Bus

INOUT

ALU Operation

1

23

ALU Result Flag

What kind of instructions?Which operations?Which data types?What addressing modes?

How is memory organized?How many address bits?How many data bits?How many registers?



8086 Feature Overview

CISC-type microprocessorMany Data types

Bit ByteWord (16-bits) Double-word (32-bits)Strings Packed BCD (2 digits per byte)

Many Instruction typesALU, Transfer, Control, Stack, Function, String, I/O …

Many Addressing modesRegister, Direct, Based, Indexed, Base+Index+Offset, I/OSegmented Memory model

8 “General Purpose” Registers4 Segment Registers for segment addressesSingle shared bus for Address and Data I/O



8086 CPU I/O

Single shared bus for Address and Data I/OFirst transfer Address, then transfer Data or Instruction

Data bus width: 16-bit Logical Addressing: Segmented Memory model

16-bit Segment Address (SEG)16-bit Byte Offset (OFFSET)

External Address bus width: 20-bit physical address

SegmentAddress

Byte Offset Segment

Byte

PhysicalByte

Address

RAM

Limit



Segmented Addresses

Physical Addresses20 bits wide5 hexadecimal characters wideE2345h = 1110 0010 0011 0100 0101

Segment Base AddressPhysical Address of first byte in segmentMust start on paragraph boundaries

Paragraph = 16 bytes = 10h bytesSegment Address must end in 0h

Segment Registers hold upper 16 bits (4 hex characters) of Segment Base Address

SegmentAddress

Byte Offset Segment

Byte

PhysicalByte

Address

RAM

Limit



Four 64 KB Segments Defined

Code Segment (CS) ⎯ holds program codeStack Segment (SS) ⎯ holds user stackData Segment (DS) ⎯ holds program dataExtra Segment (ES) ⎯ holds extra program data



Segment and Status Registers

Code CS Data DS Stack SS Extra ES

15 0

Status Register 15 0

Segment Registers hold Segment Addresses



General Registers

AH AL AX Accumulator BH BL BX Base CH CL CX Count DH DL DX Data

15 8 7 0

Stack Pointer SP Base Pointer BP Source Index SI Destination Index DI Instruction Pointer IP 15 0

General Registers can hold data and Byte Offsets



Physical Memory Addresses

20-bit external physical address space220 Bytes = 1,048,576 Bytes = 1 MByte

Logical address stored internally as SEG:OFFSETSEG stored in Segment RegisterOFFSET formed from General Registers and

ImmediatePhysical Base Address of segment = SEG × 10hPhysical Byte Address = SEG × 10h + Offset

16-bit offset ⇒ 64 KB maximum segment size0 Offset (216–1)=(64×1024–1)= 65,535≤ ≤



Segment Base

Determined by value in segment registerSegment physical base addresses begin at 16 byte intervalsSegments can overlapSame byte can be in different segments Example

CS = 0001 and DS = 0002Code Segment physical base address = 00010Data Segment physical base address = 00020CS:0025 → Byte Address = 00010+0025 = 00035DS:0015 → Byte Address = 00020+0015 = 00035



Default Segments

Memory Access Physical Address Instruction Fetch CS×10h+IP Stack Operation SS×10h+SP String Destination ES×10h+DI String Source DS×10h+SI

General Data Access

BP SI Effective Address (EA) BX + DI + Displacement

Default Physical Address = DS×10h + Effective Address (If BP is used in EA, then Physical Address = SS×10h + EA) DS may be over-ridden to CS, ES, SS



Segmentation Example: Instruction Fetch

Code SegmentAddress = 10000 h

Byte Offset = 0057 Code Segment

Code Byte

Physical ByteAddress = 10057 h

RAM

Limit = 1FFFF h

Instruction Fetch ⇒ Logical Address = CS:IPCS = 1000 ⇒ Code Segment Physical Address = 10000 hIP = 0057Logical Address = CS:IP = 1000:0057



Segmentation Example: MOV AX,[BX]

Data SegmentAddress = 21000 h

Byte Offset = 0123 Data Segment

Data Byte


RAM

Limit = 1FFFF h

MOV Instruction ⇒ DSEffective Address = BXLogical Address = DS:BX = 2100:0123



Segmentation Example: MOV AX,[BX+SI+7]

Data SegmentAddress = 21000 h

Byte Offset = 112A Data Segment

Data Byte

Physical ByteAddress = 2212A h

RAM

Limit = 1FFFF h

MOV Instruction ⇒ DSEffective Address = BX+SI+7Logical Address = DS:BX+SI+7 = 2100:0123 + 1000 + 7

= 2100:112A



Segmentation Example: MOV AX,[BP+SI+2]

Stack SegmentAddress = 41000 h

Byte Offset = 1242 Stack Segment

Stack Byte


RAM

Limit = 1FFFF h

MOV Instruction with BP ⇒ SSEffective Address = BP+SI+2Logical Address = SS:BP+SI+7 = 4100:0240 + 1000 + 2

= 4100:1242



Default Segment Register Assignments

Memory Reference Default Segment

Alternate Segment Offset

Instruction Fetch CS NONE IP Stack Operation Instruction SS NONE SP

General Data Instruction DS CS, ES, SS Effective Address

General Data Instruction with BP Used As Pointer

SS CS, ES, DS Effective Address

String Instruction Source DS CS, ES, SS SI

String Instruction Destination ES NONE DI



Advantages of Segmented Memory

Relocatable codeEffective Addresses are relative to segment

locationsPhysical Segment Byte addresses defined

relative to a start address Segment addresses adjusted at load time by

Operating SystemCan switch segment by switching segment register

value



Status RegistersBit Position Name Function

0 CF Carry Flag 2 PF Parity Flag - set for even number of 1 s in low order byte 4 AF Carry on low order 4-bits of AL 6 ZF Zero Result 7 SF Sign of Result 8 TF Stops after next instruction and resets TF (for single step) 9 IF Interrupt Enable 10 DF Causes string instructions to autodecrement index register

(otherwise, autoincrement) 11 OF Overflow



Addressing Modes

Register CX ← DX Immediate AX ← 1000H Register Indirect AX ← [BX] Direct (Absolute) AX ← [1000H] Indexed: SI or DI + Displacement AX ← [SI + 6] Based: BX or BP + Displacement AX ← [BX + 6] Based and Indexed AX ← [BX + SI] Based and Indexed with Displacement AX ← [BX + SI + 6] String Automatic



Instruction Types

ALU operationsMostly 2 operand operations (changes one of the inputs)Defined for byte or word operationsSome require operands to be in specific registers

Transfer operationsString operationsControl operations

Conditional and unconditional branchLoopSubroutine

Stack operations



Implementation

Address/DataBus Control

Decoderand

Control

StatusWord

ALU

Main Memory

GeneralRegisters

ExecutionUnit(EU)

BusInterface

Unit(BIU)+CS

DSSSESIP

AH ALBH BLCH CLDH DL

BPSPSIDI

SegmentRegisters

andInstruction

Pointer

123456

InstructionQueue

System Bus



The80x86

ProcessorFamily



8088 processor

8-bit machine similar to 8086 Single data/address bus20-bit external address bus8-bit external data busUsed in first IBM PC and PC-XT



80186

Updated version of 8086Separate external data and address busesNever used in a PCStill used as imbedded controller



80286

16-bit external data bus24-bit external address bus (16 MB address space)Supports all 8086 featuresProtected mode

Segments defined in tablesTasks defined in tablesPrivate segment for each task

Used in PC-AT (1984)



80386 (1985)

32-bit external data bus32-bit external address bus (4 GB address space)Supports all 80286 featuresIncludes support for virtual memory and pagingFirst processor to support Windows and Unix



80486 (1989)

Supports all 80386 featuresIncludes internal FPU (Floating Point Unit)Pipelined execution for faster processingIncludes 8 or 16 KB of cache



Pentium (1993)

Supports all 80486 featuresDual pipeline for faster executionIncludes 16 KB of cacheIncludes MMX unit for processing vector

instructions



Pentium-Pro (1995)

Supports all Pentium features (except MMX)36-bit external address bus (64 GB address space)Internal RISC language

Compiles x86 instructions to “micro-ops”Multiple execution units for “micro-ops”

Up to 2 MB of cache



P6 Family

Pentium II ⎯ Pentium Pro with MMX Pentium III ⎯ Enhanced FPUPentium 4 ⎯ Superpipelined (more overlapping of

instructions)

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