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    Integrated Clock Gating Cell

    Posted on February 18, 2014 by Sini Mukundanin Physical Design// 10 Comments

    Clock gating is a common technique for reducing clock power by shutting off the clock to modules by aclock enable signal.Clock gating functionally requires only an AND or OR gate. Consider you wereusing an AND gate with clock. The high EN edge may come anytime and may not coincide with a clockedge. In that case the output of the AND gate will be a 1 for less time than the clocks duty cycle. You inturn end up with a glitch in your clock signal.

    To avoid this, aspecial kind of clock gating cells are used, that synchronizes the EN with a clock edge.These are call integrated clock gating cells or ICG.

    There are two commonly used ICG cell types.

    Using AND gate with high ENThe following designuses a negative edge triggered latch to synchronize the EN signal to theCLK. The GCLK is available only when the latch o/p is high. GCLK is held low when EN is low.

    http://vlsi.pro/wp-content/uploads/2014/02/ICG_AND.pnghttp://vlsi.pro/wp-content/uploads/2014/02/ICG_AND.pnghttp://vlsi.pro/wp-content/uploads/2014/02/ICG_AND.pnghttp://vlsi.pro/wp-content/uploads/2014/02/ICG_AND.pnghttp://vlsi.pro/wp-content/uploads/2014/02/ICG_AND.pnghttp://vlsi.pro/author/sinim/http://vlsi.pro/category/back-end/physical-design-pnr/http://ask.vlsi.pro/http://vlsi.pro/category/front-end/verification/simulation-based/http://vlsi.pro/category/front-end/verification/assertion-based-verification/http://vlsi.pro/category/front-end/http://vlsi.pro/category/back-end/physical-design-pnr/http://vlsi.pro/category/back-end/http://vlsi.pro/wp-content/uploads/2014/02/AND_ICG_tim.pnghttp://vlsi.pro/wp-content/uploads/2014/02/ICG_AND.pnghttp://vlsi.pro/category/back-end/physical-design-pnr/http://vlsi.pro/author/sinim/http://ask.vlsi.pro/http://vlsi.pro/category/vlsi/http://vlsi.pro/category/front-end/verification/simulation-based/http://vlsi.pro/category/front-end/verification/equivalence-checking/http://vlsi.pro/category/front-end/verification/assertion-based-verification/http://vlsi.pro/category/front-end/verification/http://vlsi.pro/category/front-end/http://vlsi.pro/category/back-end/scripts/http://vlsi.pro/category/back-end/physical-design-pnr/http://vlsi.pro/category/back-end/http://vlsi.pro/

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    Using OR gate with high EN

    The following design uses a positive edge triggered latch. GCLK is held high when EN is low.Notethat the latch o/p is inverted at the OR input. Hence, the clock is passed through when this i/p getsa low.

    ctsicg

    10 Comments on Integrated Clock Gating Cell

    1. pramod // December 22, 2014 at 1:39 pm// Reply

    How timing checks are done on reg to clg paths? Why there are two setup time(clk gating andnochange) and two hold times are coming for this path? Can you please tell me?

    2. Anil // January 14, 2015 at 10:06 am// Reply

    Hi Sini ,

    About Latest Posts

    Sini MukundanStaff Engineerat Texas Instruments

    Sini is an expert on physical design flow and related methodologies. Outside work, she is an avid

    reader and generally loves being lazy.

    http://in.linkedin.com/in/sinimukundanhttp://vlsi.pro/author/sinim/http://vlsi.pro/author/sinim/http://vlsi.pro/integrated-clock-gating-cell/?replytocom=16250#respondhttp://vlsi.pro/integrated-clock-gating-cell/?replytocom=14734#respondhttp://vlsi.pro/tag/icg/http://vlsi.pro/tag/cts/http://vlsi.pro/wp-content/uploads/2014/02/OR_ICG_tim.pnghttp://vlsi.pro/wp-content/uploads/2014/02/ICG_OR.png

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    Does Latch o/p waveform delayed by 1 clock cycle compare to enable though it is level sensitivelatch? If so what is the reason?

    Regards,Anil

    Sini// January 14, 2015 at 12:31 pm// Reply

    It wont be held another one cycle, but if the change occurred when the clock was not active,it will be held. I think the timing diagrams are a bit off. Assume the EN going low after thenegative edge of the clk in the last timing diagram above.

    3. Seth // March 30, 2015 at 6:36 am// Reply

    The timing waveforms are wrong. You dont show the transparent phase of the latch output.

    4. ethan // May 18, 2015 at 12:17 pm// Reply

    Hi, sini,I got some questions about ICG,

    In posedge synchronous design, we often use AND gate with high EN.But the clock is held low when enable is low. Posedge FFs constitute of two latchs, clk = 0 makesthe first latch toggle all the time.How can this power saved?

    Regards,ethan

    5. Sangeetha // September 1, 2015 at 8:56 am// Reply

    Is OR gate based clock gating used only when driving a negative edge triggered flip flop andAND gate based clock gating only used for positive edge triggered flip-flops?

    6. Sarath Chandra // December 13, 2015 at 7:20 pm// Reply

    Hi sini,

    How come edge trigger word is used in latches?For latches it should be level triggered.Hope my question is a valid one.

    Sini Mukundan // December 13, 2015 at 7:47 pm// Reply

    In common usage yes. But flip flop is also an edge sensitive latch. This is the nomenclatureusually used for ICG cells, as one is an enable signal.

    7. Himavanth // January 19, 2016 at 5:52 pm// Reply

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    what is static and dynamic clock gating

    8. nirmal // March 31, 2016 at 12:52 pm// Reply

    Hi SiniIn AND based clock gating, there is a possibility of clock pulse cut off before clock period. But inlatch based clock gating, there is a possibility of losing a clock pulse entirely if latch setup timing

    is violated(meaning lath enable comes just after clock edge). Am i right?

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