ELEC 7770 Advanced VLSI Design Spring 2010 Clock Skew Problem

Spring 2010, Feb 19 . . .Spring 2010, Feb 19 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2010Spring 2010Clock Skew ProblemClock Skew Problem

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html

mailto:[email protected]

http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html


Single ClockSingle Clock

FF A FF BComb.

CK

Data_in Data_out

CKA

CKA CKB

CKB

Single-cycle path delay


Multiple ClocksMultiple Clocks

FF A FF BComb.Data_in Data_out

CKA

CKA CKB

CKB

Multi-cycle path delay


Clock SkewClock Skew

Skew is the time delay of clock signal at a flip-Skew is the time delay of clock signal at a flip-flop with respect to some time reference.flop with respect to some time reference.

For a given layout each flip-flop has a skew, For a given layout each flip-flop has a skew, measured with respect to the a common measured with respect to the a common reference.reference.

Skews of flip-flops separated by combinational Skews of flip-flops separated by combinational paths affect the short-path and long-path paths affect the short-path and long-path constraints.constraints.


Skews for Single-Cycle PathsSkews for Single-Cycle Paths

CombinationalBlockDelay:

FFi

CKi

FFj

CKj

xi xj

xi and xj are arrival times of clock edges

δ(i,j) ≤ d(i,j) ≤ Δ(i,j)


Short-Path Constraint (Double-Clocking)Short-Path Constraint (Double-Clocking)

CKi

CKj

si

sj

intendedNot intended

Thj

si + δ(i,j) ≥ sj + Thj

δ(i,j)

Tck


Long-Path Constraint (Zero-Clocking)Long-Path Constraint (Zero-Clocking)

CKj

CKi

si

sj

intended Not intended

Tsj

si + Δ(i,j) ≤ sj + Tck – Tsj

Δ(i,j)

Tck


Maximum Clock FrequencyMaximum Clock FrequencyLinear program:

Minimize Tck

Subject to:

For all flip-flop pairs (i,j),

si + δ(i,j) ≥ sj + Thj

si + Δ(i,j) ≤ sj + Tck – Tsj


Finding Clock SkewsFinding Clock Skews

FFi

Ci

Ri

FFj

Cj

Rj

FFk

Ck

RkCK

si

sj

sk

Use Elmore delay formula to calculate si, sj, sk.


Interconnect Delay: Elmore Delay ModelInterconnect Delay: Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks with W. Elmore, “The Transient Response of Damped Linear Networks with

Particular Regard to Wideband Amplifiers,” Particular Regard to Wideband Amplifiers,” J. Appl. PhysJ. Appl. Phys., vol. 19, ., vol. 19, no.1, pp. 55-63, Jan. 1948.no.1, pp. 55-63, Jan. 1948.

CKi j k

Ri Rj Rk

Ci Cj CkShared resistance:Rii = RiRij = Rji = RiRik = Rki = RiRjj = Ri + RjRjk = Rkj = Ri + RjRkk = Ri + Rj + Rk


Elmore Delay CalculationElmore Delay Calculation

Delay at node k, sk = 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )

= 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck]


Finding Finding δδ(I,j) and (I,j) and ΔΔ(I,j)(I,j)

A1

B3

C1

D2

E1

F1

J1

G2

H3

, -, -

, - 0, 0

, -, -

, -, -

i

j

k

3, 3

, -

, -

4, 4

5, 5

6, 7

6, 8

, -9, 10

Minimum delayMaximum delay


Maximum Clock Frequency for Maximum Clock Frequency for Tolerance Tolerance ±q/2 in Skew±q/2 in Skew

Linear program: Minimize Tck

Subject to: For all flip-flop pairs (i,j),

si + δ(i,j) ≥ sj + Thj + q

si + Δ(i,j) ≤ sj + Tck – Tsj – q

Where q is a constant

si are variables, simin ≤ si

Tck is a variable


Maximum Tolerance for Given Clock Maximum Tolerance for Given Clock FrequencyFrequency

Linear program: Maximize q

Subject to: For all flip-flop pairs (i,j),

si + δ(i,j) ≥ sj + Thj + q

si + Δ(i,j) ≤ sj + Tck – Tsj – q

Where Tck is a constant

si are variables, simin ≤ si

q is a variable


TradeoffsTradeoffs

Increasing clock period Tck

Incr

easi

ng s

kew

tole

ranc

e q

No

solu

tion

beca

use

ofze

ro s

lack

.


Clock Skew ProblemClock Skew Problem

N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.

J. P. Fishburn, “Clock Skew Optimization,” J. P. Fishburn, “Clock Skew Optimization,” IEEE IEEE Trans. ComputersTrans. Computers, vol. 39, no. 7, pp. 945-951, , vol. 39, no. 7, pp. 945-951, July 1990.July 1990.

ELEC 7770 Advanced VLSI Design Spring 2010 Clock Skew Problem

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