Instructions for Lab 1: Quick Tool- · PDF fileInstructions for Lab 1: Quick Tool-Tutorial ......

Instructions for

Lab 1: Quick Tool-Tutorial

SMD106 Project in Digital Synthesis

2002-01-14

Linus Svensson ([email protected]) Åke Östmark ([email protected])

Department of Computer Science and Electrical Engineering Embedded Internet Systems Laboratory

SMD106 Project in Digital Synthesis Lab 1: Quick Tool-Tutorial

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1 INTRODUCTION............................................................................................... 3

2 SETTING UP THE ENVIRONMENT ............................................................. 3

3 DESIGN ENTRY ................................................................................................ 4

4 SYNTHESIS FLOW ........................................................................................... 5

4.1 SPECIFY LIBRARIES......................................................................................... 7 4.2 GETTING HELP................................................................................................ 8 4.3 READ DESIGN. ................................................................................................ 8 4.4 DEFINE DESIGN ENVIRONMENT & SET DESIGN CONSTRAINTS......................... 9 4.5 OPTIMIZE THE DESIGN .................................................................................. 10 4.6 ANALYZE AND RESOLVE DESIGN PROBLEMS................................................. 10 4.7 WRITING SDF FILE....................................................................................... 11 4.8 SAVE THE DESIGN DATABASE ....................................................................... 11 4.9 SCRIPTS........................................................................................................ 11

5 CREATING A SILICON ENSEMBLE LIBRARY DATABASE AND DESIGN DATABASE............................................................................................... 13

5.1 CREATING A LIBRARY DATABASE................................................................ 14 5.2 CREATING THE DESIGN DATABASE .............................................................. 15

6 FLOORPLANNING AND POWER PLANNING ......................................... 17

6.1 FLOORPLANNING.......................................................................................... 17 6.2 POWER PLANNING........................................................................................ 19

7 PLACEMENT ................................................................................................... 21

7.1 PLACEMENT WITH QPLACE ......................................................................... 21

8 CLOCK TREE .................................................................................................. 23

8.1 CLOCK TREE GENERATION (CTGEN) ........................................................... 23

9 ROUTING.......................................................................................................... 26

9.1 SPECIAL, CLOCK AND SIGNAL ROUTING ...................................................... 26

10 GENERATING A GDSII FILE................................................................... 30

11 CLEANING UP THE ENVIRONMENT.................................................... 30

12 SUBMISSION................................................................................................ 30


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1 Introduction In this lab you will go through an entire ASIC design flow, from HDL code to tape-out. The lab is a tutorial for the two main tools used in the course, Synopsys Design Compiler 2000.05-1 and Cadence Silicon Ensemble 5.2. These tools are somewhat complex and the purpose is not to get full understanding of the tools, but rather to get familiar with them. The ASIC design flow used is a simplified flow and it will not produce an error free chip, but it will give you the big picture of what it is all about. Since the focus is on the tools, the HDL code used in the design entry step is given. The lab can be done either individually or in groups of two.

2 Setting Up the Environment The files needed for the lab can be found at / di gcad/ smd106/ 2002/ l ab1/ l ab1. z i p. The zip-file contain the following directories and files: Directory Files Descr iption syn alu.v

define_opcodes.v Given source code for lab1.

.synopsys_dc.setup Synopsys setup file. layout se.ini Initialisation file for Silicon Ensemble. lib_035.gcf General Constraint Format file. corner_supply.def Design Exchange Format file with info

regarding the corner and supply cells. alu_io_place_file.ioc Contains information about the placement of the

IO pads. alu_synth.v Mapped netlist. alu_constraints.sdf Standard Delay Format Constraints file. zoom1 Used to zoom in on the VDDI pad. zoom2 Used to zoom in on the VSSI pad. layout/Scripts core_filler.mac Script that places core filler cells. io_filler.mac Script that places IO filler cells. layout/dbs Directory to store Cadence database files

(empty).

Table 1: Contents of lab1.zip

Documentation for Synopsys can be found at / di gcad/ synopsys/ 2000. 05/ doc/

onl i ne/ t op. pdf . Documentation for Cadence can be found at / di gcad/ smd106/ 2002/ doc/ l ayout . Please note that the documents for Silicon Ensemble are version 5.1 and 5.3, while the program itself is version 5.2. More documentation for Cadence can be accessed with the openbook utility (type openbook & at the command prompt).


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3 Design Entry The design in this tutorial is a 16-bit ALU. The ALU has an on-chip 512*32 bit memory for store and load operations.

DATA 16 ALUOUT32

OPCODE

11

RESET

CLOCK

Figure 1: The ALU.

The memory block is instantiated by using two instances of a 256*32 memory, previously generated by a RAM compiler. You will:

• Read in the Verilog HDL description of the ALU design (al u. v) into Synopsys Design Analyzer.

• Set up some constraints and synthesize the design.

• Save the design as al u_synt h. v , which you will read into Cadence Silicon Ensemble later on.

• Create a constraints file that can be used for timing driven placement and routing in Cadence Silicon Ensemble (Qplace/Wroute) later on.

You will run the tutorial on the Alcatel 0.35 µm CMOS process.


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4 Synthesis flow Design Compiler is the core of the Synopsys synthesis software products. It comprises tools that synthesize your HDL designs into optimised technology-dependent, gate-level designs. It supports a wide range of flat and hierarchical design styles and can optimise both combinational and sequential designs for speed, area, and power. Figure 2 shows a simplified overview of the Design Compiler synthesis process.

Synopsys Design Compiler

VERILOG source

VHDL source

Other formats

Mapped, Technology- Dependent Netlist

Figure 2: Design Compiler Overview.

Synopsys Design Compiler provides three interfaces:

• Design Compiler command-line interface, dc_shel l . This is the original Design Compiler command language and is specific to Synopsys. This shell mode is referred to as the dcsh mode.

• dc_shel l - t command line interface

This Design Compiler command language is based on the Tool Command Language (Tcl) and includes certain command extensions needed to implement specific Design Compiler functionality. This shell mode is referred to as the Tcl mode.

• Design Compiler GUI, desi gn_anal yzer . Design Analyzer uses a graphical user interface (GUI) with menus, dialog boxes, and so forth to implement Design Compiler commands. It also provides graphical displays, such as design schematics.

Both dc_shel l and dc_shel l - t interfaces provide capabilities similar to UNIX command shells, including such capabilities as variable assignments, conditional execution of commands, and control flow commands. However, in this tutorial, we use the Design Compiler GUI. Design Compiler reads and writes design files in all the standard electronic design automation (EDA) formats, including Synopsys internal database (. db) and equation (. eqn) formats. Figure 3 shows the basic synthesis flow. Also listed are the basic dc_shel l commands, commonly used in each step of the basic flow. For example, the commands anal yze, el abor at e, and r ead_f i l e are used in the step that reads design files into memory. All the commands shown can take options, but no options


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are shown in the figure. (Note. The first step can be seen as the design entry to the synthesis process. You do not develop your HDL files with the Design Compiler tools).

Develop HDL Files

Specify Libraries

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Design Rule Constraints set _max_t r ansi t i on set _max_f anout set _max_capaci t ance

Design Optimization Constraints cr eat e_cl ock set _c l ock_l at ency set _pr opagat ed_cl ock set _c l ock_uncer t ai nt y set _c l ock_t r ans i t i on set _i nput _del ay set _out put _del ay set _max_ar ea

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Figure 3: Basic synthesis flow with commands commonly used in each step of the flow.


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4.1 Specify libraries. Start Design Compiler by following these steps:

• Change directory to: lab1/syn • design_analyzer &

Go to Setup -> Defaults … when the program starts to view the library objects as in Figure 4.

Figure 4: The Defaults screen with library objects

.

The library objects will have been setup via the Synopsys init file, . synopsys_dc. set up in the Synopsys root directory, your home directory and in the current working directory, Example from the . synopsys_dc. set up (in your working directory). sear ch_pat h = sear ch_pat h + { ads_i nst _di r + / ads98. 1/ cmos035/ v1. 8/ syn98. 2 l i nk_l i br ar y = { MTC45000_WL_TYP. db } l i nk_l i br ar y = l i nk_l i br ar y + { MTC45000. db } l i nk_l i br ar y = l i nk_l i br ar y + { MTC45100. db } l i nk_l i br ar y = l i nk_l i br ar y + { SPS3_256x32m4. db } t ar get _l i br ar y = { MTC45000_WL_TYP. db } t ar get _l i br ar y = t ar get _l i br ar y + { MTC45000. db } t ar get _l i br ar y = t ar get _l i br ar y + { MTC45100. db } t ar get _l i br ar y = t ar get _l i br ar y + { SPS3_256x32m4. db } symbol _l i br ar y = { MTC45000. sdb }


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The link and target libraries are the technology libraries that define the vendor’s set of cells (cell pin names, design rules etc.). Design Analyzer uses the symbol library to show the schematics of the design. The MTCxxxx. db are the core and I/O cells for the Alcatel CMOS 0.35µm process. The SPS3_256x32m4. db is the memory block. Synopsys generates a lot of information. All executed commands and system response messages are recorded in the files vi ew_command. l og and command. l og. The f i l ename_l og_f i l e will contain all the filenames read in by desi gn_anal yzer or dc_shel l , including db, script, verilog, and vhdl or include files for one invocation of the program.

4.2 Getting help There is an on-line help menu button in the upper right corner of the Design Analyzer GUI window. You can use select Help->Command to look up information about commands. Help about commands is also accessible from the Command Window (Setup -> Command Window…) where you type man command_name to get the same information. The online help seems not to be working properly, use di gcad/ synopsys/ 2000. 05/

doc/ onl i ne/ t op. pdf instead.

4.3 Read design. You can use the anal yze and el abor at e commands to read the RTL-design.

• The anal yze command reads the HDL-file and checks it for errors. Create and stores the file(s) into an intermediate format.

• The el abor at e command creates a technology independent design from the intermediate files.

• The r ead_f i l e command reads all input formats. (precompiled designs…) (If the r ead_f i l e command is used to read RTL-files, the analyze and elaborate functions are combined.)

To read in the source file, select:

File->Read…

and select the file al u. v . A window will open, named Verilog, and show the result of the command e.g. inferred memory devices (flip-flops, latches), errors and/or warnings. Hit Cancel in the Verilog window to close it. In the Synopsys Design Analyzer window, there should be an icon for ALU, DEFINE_OPCODES, SPS3_512*32m4. The design view in the Design Analyzer window does not display hierarchy, it simply displays an icon for each design loaded in the Design Analyzer memory. The Y=A+B icon represents designs that are not yet mapped to gates, and now the ALU should have this icon. You can navigate through hierarchy and view different views of the design by using the buttons on the left hand side of the Design Analyzer window or by double-clicking an icon.


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Note. Design Compiler does not automatically save the designs loaded in memory. If you want to save these designs before exiting, you have to save the design to disk.

4.4 Define design environment & Set design constraints After you read in the design into Design Compiler, you specify the design environment. Design Compiler requires that you model the environment of the design to be synthesized. This model comprises the external operating conditions (manufacturing process, temperature, and voltage), loads, drives, fanouts, and wire load models. You model the environment in which the design is expected to operate by setting attributes. See Figure 5 for commands used to define the design environment. The design constraints define the design goals for timing (clocks, clock skews, input delays, and output delays) and area.

Figure 5: Commands used to define the design environment.

4.4.1 Setting output load. Load values are used to model the capacitive load on the output ports of the module. Go to Symbol View for the ALU design (double-click the icon). To select the one output bus, select:

Edit->Select…

In the Select By Name form, change type to Output Por ts.

Click Apply and the Cancel in the form. The output port should now be selected.

To set the output load to 0.1 pF, select:

Attr ibutes -> Operating Environment ->Load

In the Load form, enter 0.1 in the Capacitive Load field, then Apply and Cancel.

4.4.2 To set the operating conditions To set the operating conditions for the ALU design, select:

Attr ibutes -> Operating Environment ->Operating Conditions…

In the operating conditions from, select:

NOM (MTC45000)


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The operating conditions will be set to nominal conditions. (You can use the r epor t _l i b command in the Command Window to list the operating conditions defined in a technology library.

4.4.3 Set the wire load model Wire load models estimates the effect of wire length and fanout on the resistance, capacitance and areas of nets. To set the wire load model of the ALU design, select:

Attr ibutes -> Operating Environment ->Wire Load…

In the Wire Load form, select:

top_5 (MTC45000_WL_TYP)

4.4.4 Specifying a clock Select the CLOCK pin of the ALU design, then select:

Attr ibutes -> Clock -> Specify…

In the form, enter 50 in the Period field. Click Apply, and then Cancel. This will set the clock period to 50 ns.

4.5 Optimize the design You use

Tools-> Design optimization…

to invoke Design Compiler’s synthesis and optimization process. Don’ t change any setting from the Design Optimization window. Select OK, which will bring up the Compile Log. In the start of the Compile Log, Synopsys prints out information about DesignWare libraries, which are reusable components integrated to the Synopsys environment. The rest of the log shows the progress of the synthesis process and finally, the design is transferred to ALU. db (in memory). You can ignore any warnings for now. You can close the Compile Log window and take a look at the schematic of the design. The icons should now have a gate as symbols, indicating that the design has been mapped to a target-depended (Alcatel 0.35 µm) library.

4.6 Analyze and resolve design problems

4.6.1 To generate and view reports A number of reports can now be generated. To generate and view reports of the ALU design, go to the Symbol view of the ALU, then select:

Analysis -> Report…

Select Constraints and Timing in the Report window. Click Set Options… and select All Violations. Select OK , the Apply. View the report output. The design should not have any violating constraints and the path with the max delay should have a (positive) slack of approximately 0.28 ns.


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4.6.2 Highlight critical path Go to the Schematic view of the ALU, then select:

Analysis -> Highlight -> Cr itical Path

The critical path will be highlighted.

4.7 Writing SDF file To write a Standard Delay Format (SDF) Constraints file that can be used later for timing driven placement in Silicon Ensemble (Qplace, WRoute), go to the Symbol View for the ALU design, then select:

File -> Save Info -> Constraints…

Set 100 in the Max Paths field, then OK .

4.8 Save the design database To create a Verilog HDL gate-level netlist (al u_synt h. v), select:

File -> Save As…

In the Save File form, enter al u_synt h. v for filename and Verilog for format. The design can now be imported by the physical design step. Note: In this lab, a synthesized netlist is provided for you. If you take a look at the source code (al u. v) you will find that some of the operations have been removed. The purpose is to reduce the run-time of the synthesis, only mapping some of the ALU-operations. You will find the pre-mapped netlist (and SDF file) that should be used later on in the l ab1/ l ayout / directory. You are now done with the synthesis part of lab1 and can exit Design Analyzer and continue with Place & Route.

4.9 Scripts In reality, you use scripts to synthesize the design. The following script is an example of some commands. / * Read i n HDL f i l e. * /

r ead - f or mat ver i l og al u. v

/ * Set cur r ent desi gn * /

cur r ent _desi gn ALU

/ * Set out put l oad * /

set _l oad 0. 1 f i nd( por t , " ALUOUT* " )

/ * Set oper at i ng condi t i ons * /

set _oper at i ng_condi t i ons - l i br ar y " MTC45000" " NOM"


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/ * Run desi gn opt i mi zat i on * /

compi l e - map_ef f or t l ow

/ * Save desi gn as ver i l og f or mat * /

wr i t e - f or mat ver i l og - hi er ar chy - out put al u_synt h. v

/ * Wr i t e St andar d Del ay For mat ( SDF) Const r ai nt s f i l e * /

wr i t e_const r ai nt s - max_pat h_t i mi ng - f or mat sdf - max_pat hs 100 -

out put al u_const r ai nt s. sdf

To r un a scr i pt i n dcsh mode, you coul d use, assumi ng t he scr i pt t o

be i n t he scr i pt di r ect or y:

$/ syn>dc_shel l - f . / scr i pt s/ xxx. scr > some_f i l e. l og


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5 Creating a Silicon Ensemble Library Database and Design Database

Before the physical layout can be started, an appropriate library database must be created. The library database describes the technology (process) and the macro cells required to generate the physical description of the design. By importing Library Exchange Format (LEF) files and Compiled Timing Library Format (CTLF) files a library database can be created. A design database can be created by importing netlist files, which can be in either Verilog or Design Exchange Format (DEF) files, constraint files and Design Exchange Format (DEF) files. See Figure 6.

LEF (Library Exchange Format)

MTC45000.lef MTC45100.lef

SPS3_256x32m4.lef

CTLF (Compiled Timing

Library Format) lib_035.gcf

Library Database lib_035

Verilog MTC45000.v MTC45100.v

SPS3_256x32m4.v alu_synth.v SDF

(Standard Delay Format)

alu_constraints.sdf

DEF (Design Exchange

Format) corner_supply.def

Design Database netlist

Figure 6: Creating a Library Database and a Design Database.

Section 5 will show how to create a library database and then a design database using these files.


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5.1 Creating a Library Database Start Silicon Ensemble by following these steps:

• Change directory to: l ab1/ l ayout / • seul t r a –m=200 &

5.1.1 Importing Library Exchange Format (LEF) Files. The library database is created using one or several LEF files. A LEF file contains information about the library being used and is normally provided by the foundry for the technology you are using (i.e. Alcatel).

• Select File -> Import -> LEF… • Change directory to: / di gcad/ smd106/ 2002/ l ab1/ LEF • Select MTC45000. l ef and click on Apply • Select MTC45100. l ef and click on Apply • Select SPS3_256x32m4. l ef and click on Apply • Click Cancel to close the Import LEF form.

Note: The MTC45000. l ef file contains information about the Alcatel CMOS 0.35µm core cells. The MTC45100. l ef file contains information about mid-profile IO cells. The SPS3_256x32m4. l ef file contains information about a 1kB memory macro cell.

5.1.2 Importing Compiled Timing Library Format (CTLF) Files After the LEF files for the process have been read in, the timing information for the library must be read in. The timing information is stored in CTLF files that are provided by the foundry (i.e. Alcatel).

• Select File -> Import -> Timing L ibrary… • Double click l i b_035. gcf (this General Constraint Format (GCF) library file

gives Silicon Ensemble the path to the CTLF file, which is then loaded automatically).

5.1.3 Saving the Library Database The library database now contains information about the Alcatel CMOS 0.35µm process and a 1kB memory macro cell.

• Select File -> Save As… • Enter design name l i b_035 • Select Keep Editing Current Design and click OK


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5.2 Creating the Design Database

5.2.1 Importing Verilog Files Netlists can be imported from either Design Exchange Format (DEF) or Verilog files. In this tutorial the Verilog file created from Synopsys Design Compiler (al u_synt h. v) is used. Note: If this is not the first time importing a Verilog file in this directory, the files cds. l i b and van. r pt must be deleted.

• Select File -> Import -> Ver ilog… • Fill out the form according to Figure 7. The Verilog Source Files field should

contain the following files: o / di gcad/ smd106/ 2002/ l ab1/ VERI LOG/ MTC45000. v o / di gcad/ smd106/ 2002/ l ab1/ VERI LOG/ MTC45100. v o / di gcad/ smd106/ 2002/ l ab1/ VERI LOG/ SPS3_256x32m4. v o al u_synt h. v

Figure 7: The Import Verilog form.

• Click OK

5.2.2 Importing Standard Delay Format (SDF) Constraints File An SDF constraints file is read in to define timing constraints for the design. Alternatively, if you have timing constraints in a GCF constraints file, you can use them instead.

• Select File -> Import -> SDF… • Double click al u_const r ai nt s. sdf


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5.2.3 Adding Corner and Supply Cells to the Database. The design needs corner and supply cells. In this step the netlist information for the corner and supply cells are read from a DEF file and added to the database. The Initialize Floorplan command, that will be used later, automatically place these cells once they are in the database.

• Select File -> Import -> DEF… • Double click cor ner _suppl y. def

5.2.4 Saving the Design Database The design database now contains general information about the Alcatel CMOS 0.35µm process and specific information about the ALU design.

• Select File -> Save As… • Enter design name net l i s t • Select Keep Editing Current Design and click OK


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6 Floorplanning and Power Planning

6.1 Floorplanning Floorplanning is used to predict and assess the effects of physical layout before a design is placed and routed, thus speeding up the design process by reducing the number of iterations to a minimum.

6.1.1 Initialising a Floorplan A number of variables are set and an initial floorplan is created. The variables will have a significant impact on the final die size. The most significant factor is the row utilisation number that should be between 70% and 90% for a three-layer design, and 90% or more for a five-layer design.

• Select Floorplan -> Initialize Floorplan • Fill out the form according to Figure 8

Figure 8: The Initialize Floorplan form

• Click Calculate and check the result (take the opportunity to test different settings to get a feeling for how the values effect the final area).

• Click OK to initialise the floorplan • Select all objects in the Vs column (i.e. Region, Group, etc.) and click on the

Fit button to view the floorplan

6.1.2 Placing I/O Cells Before any of the blocks are placed, the I/O cells must be placed. They can be placed either automatically or with the aid of an IO Placement file. In this tutorial a pre-generated IO file is used.


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• Select Place -> IOs… • Select Placement Mode I /O Constraint File • Use the constraint file al u_i o_pl ace_f i l e. i oc • Click OK • Enter execut e Scr i pt s / i o_f i l l er . mac; at the command window (the

Alcatel 0.35µm process requires that I/O Filler cells must be placed between the IO Pads)

6.1.3 Placing Blocks If the design contains blocks they should be placed before the standard cells are placed. The blocks can be placed either automatically or by manually moving them into position. In this tutorial the automatic method is used.

• Select Place -> Blocks… • Select Timing Dr iven Placement • Click Var iables • Set QPLACE.BLOCK.KEEPOUT.X to 50 • Set QPLACE.BLOCK.KEEPOUT.Y to 50 • Click OK in the Environment Variables form (this will set a distance of 50µm

between blocks for power and signal routing) • Click OK in the Quick Place Blocks form (this takes rather long time)

6.1.4 Cutting Rows Around Blocks The core rows must be cut back from the blocks to allow power and signal routing around the blocks.

• Select Floorplan -> Update Core Rows… • Ensure that the Global Block Halo is set to 50.00 • Click OK

6.1.5 Saving the Floorplan Database The floorplan database now contains completed floorplanning but no power planning.

• Select File -> Save As… • Enter design name f l oor pl an_no_pp • Select Keep Editing Current Design and click OK


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6.2 Power Planning After initialising the floorplan, placing I/O cells and blocks, and cutting around the blocks, the power stripes need to be routed across the core area, and the remaining power nets need to be planed.

6.2.1 Initialising Power Planning The Plan Power command identifies groups of rows (called clusters) and channels for power planning.

• Select Route -> Plan Power… The Plan Power (PP) toolbox opens, and a yellow dotted line show the general topology of the power routes that are planned. Note: All power planning must be completed before the PP toolbox is closed. Once the PP toolbox is closed it cannot be opened again if there exist power and ground wires for rings and stripes. I.e. if more power wires are needed later, it is necessary to delete any pre-existing power and ground wires.

6.2.2 Adding Rings To add rings do the following.

• On the PP toolbox select Add Rings… • Fill out the form according to Figure 9

Figure 9: The PP Add Rings form.

• Click OK in the PP Add Ring Form (do not close the PP toolbox) A ring around the blocks and one ring around the core, where the yellow dotted lines were, are created.


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6.2.3 Adding Stripes To add stripes do the following.

• On the PP toolbox select Add Str ipes… • Fill out the form according to Figure 10

Figure 10: The PP Add Stripes form.

• Click OK in the PP Add Stripes Form • Click Close in the PP toolbox

6.2.4 Saving the Floorplan Database The floorplan database now contains completed floorplanning and power planning.

• Select File -> Save As… • Enter design name f l oor pl an • Select Keep Editing Current Design and click OK


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7 Placement

7.1 Placement With QPlace

7.1.1 Placing Standard Cells in a Timing Critical Design At this point the floorplan contains rows for all the standard cells. The next step is to place the standard cells in the rows. Space is reserved for the Clock Tree Generation (CTGen) around all core components connected to nets using a clock.

• View the floorplan as instructed at the end of section 6.1.1 • Select Place -> Cells… • Fill out the form according to Figure 11

Figure 11: The Place Cells form.

• Click Options • Set Extra Sites for Clock Buffers to 0.6 (this reserves 0.6 sites around every

clocked core component for CTGen) • Click OK in the Place Cells Options form • Click OK in the Place Cells form to place the standard cells (takes very long

time, an excellent time get a cup of coffee) Note: The results from QPlace can be found in the file se. j nl . By comparing key numbers (VMAX, HMAX and total wire length) from different runs on the same design, the best design can be found.


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7.1.2 Saving the Placement The design database now contains completed timing driven placement.

• Select File -> Save As… • Enter design name pl aced • Select Keep Editing Current Design and click OK


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8 Clock Tree

8.1 Clock Tree Generation (CTGen) CTGen is an optional feature in Silicon Ensemble, which is used to generate buffered clock trees. CTGen constructs an optimised clock tree and minimises skew and clock tree min/max insertion delay.

8.1.1 Looking at the Existing Clock Tree The design already contains a (un-optimised) clock tree.

• View the floorplan as instructed at the end of section 6.1.1 • Select Edit -> Find… • Set the Type droplist to Net • Set the Name field to n3371 (the name of the clock net from the Verilog

netlist file) • Select Show List • Set Background Dimmer to ~40 • Click Find • Select n3371 in the list (the only item in the list) • Click Select to highlight the existing clock net • Click Deselect All and Dehilight All when done viewing • Click Cancel to close the Find form • Click Fit to restore the colours

8.1.2 Running CTGen • Select Place -> Clock Tree Generate (CTGen)… • Fill out the form according to Figure 12

Figure 12: The CTGen form.

• Click Edit to open the CTGen Constraint form • Fill out the form according to Figure 13


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Figure 13: The CTGen Constraint form.

• Click OK to create the constraint file • Click OK in the CTGen form (this takes some time).

Once the CTGen run has completed the CTGen Results form is displayed. In this tutorial warnings can be ignored. A number of reports can be directly accessed from the form.

• Click Violations to see if there are any violations in the design • Press the keys [ ESC] [ : ] [ q] [ ! ] [ ENTER] to close the vi window

If all constraints were met, the result can either be discarded or loaded into the database.

• Click Load Results in the CTGen Results form

8.1.3 Looking at the Newly Created Clock Tree The new clock tree is now created and loaded into the design.

• View the floorplan as instructed at the end of section 6.1.1 • Select Edit -> Find… • Set the Type droplist to Net • Set the Name field to n3371* • Select Show List • Set Background Dimmer to ~40 • Click Find • Select all items from the list • Click Select to highlight the clock tree


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• Click Deselect All and Dehilight All when done viewing • Click Cancel to close the Find form • Click Fit to restore the colours

8.1.4 Saving the CTGen Database The design database now contains completed clock tree generation.

• Select File -> Save As… • Enter design name ct gen • Select Keep Editing Current Design and click OK


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9 Routing

9.1 Special, Clock and Signal Routing

9.1.1 Core Filler Cells The Alcatel 0.35µm process requires that Core Filler cells must be placed between the core cells. This is done before the routing is started.

• View the floorplan as instructed at the end of section 6.1.1 • Enter execut e Scr i pt s / cor e_f i l l er . mac; at the command window

9.1.2 Special Routing The first step during the special routing is to connect the stripes and blocks to the power rings in the design.

• Select Route -> Connect Ring… • Fill out the form according to Figure 14

Figure 14: The Connect Ring form.

• Click OK • Zoom in and have a look at the stripes and blocks that have been connected to

the power rings.


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Next step is to connect power pins for the standard cells within rows to the power rings.

• Select Route -> Route Power -> Follow Pins… • Fill out the form according to Figure 15

Figure 15: The Sroute Follow Pins form.

• Click OK • Zoom in and have a look at the power for the standard cells that have been

connected to the power rings. Note: X-shaped markers indicate violations. For this tutorial we can ignore them. Finally, the power rings will be connected to the power pads.

• Enter execute zoom1; to zoom in around the VDDI pad • Select Edit -> Wire -> Add… • Refer to Figure 16 to add the wires • Click at position ’1’ • Click at position ’2’ to add part of the wire • In the Add Wire Form set Layers to metal5 • Click at position ’3’ to add the left wire • In the Add Wire Form set Layers to metal5 : metal4 • Click at position ’4’ • Click at position ’5’ to add part of the wire • In the Add Wire Form set Layers to metal5 • Click at position ’6’ to add the right wire • Click OK in the Add Wire Form to finally connect the vdd! ring


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VDDI PAD

gnd!

vdd!

Ring Wires Wires tobe added

vdd! pin

1

2

3

4

5

6

Figure 16: Connecting the vdd! net to the vddi pad.

• Enter execute zoom2; to zoom in around the VSSI pad • Select Edit -> Wire -> Add… • Refer to Figure 17 to add the wires • Click at position ’1’ • In the Add Wire Form set Layers to metal5 • Click at position ’2’ to add the left wire • Click at position ’3’ • Click at position ’4’ to add the right wire • Click OK in the Add Wire Form to finally connect the gnd! ring

VSSI PAD

gnd!

vdd!

Ring WiresWires tobe added

gnd! pin

1

2 4

3

Figure 17: Connecting the gnd! net to the vssi pad.


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9.1.3 Clock Routing The clock routing is used to route the clock nets in the design.

• Select Route -> Clock Route… • Fill out the form according to Figure 18

Figure 18: The ClockRoute form.

• Click OK

9.1.4 Signal Routing Silicon Ensemble includes the WRouter utility. The WRouter does global and detailed routing, automatic search and repair, and optimisation.

• Select Route -> WRoute… • Select Timing Dr iven Routing • Click Options • Select Optimize Wire Length in the WRoute Option form • Click OK in the WRoute Option form • Click OK in the WRoute form (somewhat time-consuming)

Note: Running several iterations of WRoute will optimise the wire length and number of vias used. The results from WRoute can be found in the log file.

9.1.5 Saving the Routed Database The design database now contains final routing.

• Select File -> Save As… • Enter design name r out ed • Select Keep Editing Current Design and click OK


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10 Generating a GDSII File Generate the GDSII file (tape-out) by following these steps:

• Select File -> Export -> GDS I I… • Fill out the form according to Figure 19

Figure 19: The Export GDSII form.

• Click OK • Check the log file for any warnings or errors.

11 Cleaning Up the Environment To avoid using unnecessary space on the server, please delete files that you do not need any longer. E.g. all but the last database (routed.* ) can probably be deleted from the l ab1/ l ayout / dbs/ folder.

12 Submission To pass this lab, you just need to (besides doing the lab of course) send an e-mail no later than the submission date to [email protected] or [email protected] with

• Subject: SMD106 submission lab1 • Body: Your name(s)

The results will be posted on the course homepage.

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