INPUT VECTOR DEPENDENT LEAKAGE CURRENT OF VLSI STANDARD CELLS IN 45NM TECHNOLOGY

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HERITAGE INSTITUTE OF TECHNOLOGY Department of

Electronics and Communication Engineering

This is to certify that the project thesis titled INPUT VECTOR DEPENDENT LEAKAGE CURRENT OF VLSI STANDARD CELLS

IN 45NM TECHNOLOGY Has been currently undertaken by

Argha Rakshit (Roll no-12600311030) Avirup Dutta Gupta (Roll no-12600311042)

Ipsita Basu (Roll no-12600311062) Md. Maroof Khan

(Roll no-12600311084) Prathhana Roy

(Roll no-12600311105)

In partial fulfilment for the award of the degree in Bachelor of Technology

In Electronics and Communication Engineering West Bengal University of Technology, 2015

Under the supervision of

--------------------------------

Prof. Krishanu Datta Project Guide & Associate Professor

Department of Electronics and Communication Engineering Heritage Institute of Technology, Kolkata

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Heritage Institute of Technology Affiliated to

West Bengal University of Technology

Certificate of Approval*

The foregoing project report is hereby approved as a creditable study of an engineering subject carried out and presented in a manner satisfactory to warrant its acceptance as a prerequisite to the degree for which it has been submitted. It is understood that by this approval the undersigned dont necessarily endorse or approve any statement made opinion expressed or conclusion drawn therein but approve the project report only for the purpose for which it is submitted.

Signature of the Examiners:

1.

2.

3.

*Only in the case the project report is approved

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Abstract

With rapid scaling of CMOS technology, sub threshold and gate leakage mechanisms have become dominant. With feature size scaling beyond 50nm, gate leakage has become comparable to sub threshold leakage. In such a scenario, gate leakage currents can no longer be ignored in NMOS devices that are switched OFF. In todays technology reducing stand by power consumption is one of the key design goals for portable devices. In this study input vector dependency on standby leakage current of VLSI standard cells has been explored for a deep submicron technology (45 nm process node). It is observed that gate leakage current for NMOS devices is not negligible with respect to the subthreshold leakage current which dominates stand by current in VLSI standard cells. Maximizing stacking effect is the key to achieve min leakage of VLSI standard cells.

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CHAPTER[1]:INTRODUCTION

There are three major sources of power dissipation in digital CMOS circuits which are summarized in the following equation: Pavg=Pswitching+ PShort-circuit +PLeakage = 0->1CL.V

2dd.fclk+Isc.Vdd+Ileakage.Vdd

The first term represents the switching component of power, i.e. the Dynamic Power Dissipation, where CL is the load capacitance , fCLK is the clock frequency and 0 is the node transition activity factor (the average number of times the node makes a power consuming transition in one clock period).The second term ,i.e. Short-Circuit Power Dissipation is due to the direct path short circuit current ,ISC, which arises when both the NMOS and PMOS transistors are simultaneously active , conducting current directly from supply to ground .Finally, Static (Leakage) Power Dissipation ,where the leakage current, Ileakage, which can arise from substrate injection and subthreshold effects, is primarily determined by fabrication technology considerations. In todays technology Leakage power is dominating most of the chip has more than 50% leakage power.

[1.1] SOURCES OF LEAKAGE POWER:

There are four main sources of leakage current in a CMOS transistor (see Figure 1):

1. Sub-threshold (weak inversion) leakage (ISUB),

2. Gate direct-tunnelling leakage (IG) ,

3. Gate induced drain leakage (IGIDL), and

4. Reverse-biased junction leakage current (IREV).

Around 70-80% of leakage current is ISUB, 20-30% of leakage current is IGate (IG+IGIDL) and rest is IREV.

Figure 1: Leakage current components in an NMOS transistor.

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[1.1.1]SUBTHRESHOLD LEAKAGE

The subthreshold leakage is the drain-source current of a transistor operating in the weak inversion region. Unlike the strong inversion region in which the drift current dominates, the subthreshold conduction is due to the diffusion current of the minority carriers in the channel for a MOS device. For instance, in the case of an inverter with a low input voltage, the NMOS is turned OFF and the output voltage is high. In this case, although VGS is 0V, there is still a current flowing in the channel of the OFF NMOS transistor due to the VDD potential of the VDS. The magnitude of the subthreshold current is a function of the temperature, supply voltage, device size, and the process parameters out of which the threshold voltage (VTH) plays a dominant role. In current CMOS technologies, the subthreshold leakage current, ISUB, is much larger than the other leakage current components. This is mainly because of the relatively low VTH in modern CMOS devices. ISUB is calculated by using the following formula:

ISUB = (W/L).vTH2CSTH.e((vGS - vT + vDS)/ vTH ).( 1 - e( -vDS/vTH ) ).(1) where W and L denote the transistor width and length of the MOS, denotes the carrier mobility, VTH=kT/q is the thermal voltage at temperature T,CSTH=CDEP+CIT,denotes the summation of the depletion region capacitance and the interface trap capacitance both per unit area of the MOS gate , and is the drain-induced barrier lowering (DIBL) coefficient [2].

is the slope shape factor and is calculated as:

= 1 + (CSTH/COX ).(2) where COX denotes the gate input capacitance per unit area of the MOS gate. When a long channel transistor with VDS larger than a few VTH is in the OFF state (VGS=0), we have:

ISUB = (W/L).vth2Csth..10 (-VT/S).(3) where S denotes the subthreshold swing parameter, which is defined as the inverse of the slope of the log10(IDS) versus VGS characteristic and is equal to nth.ln(10). S is equal to the subthreshold voltage decrease required to increase ISUB by a factor of ten.

It is highly desirable to have a subthreshold swing as small as possible since this is the parameter that determines the amount of voltage swing necessary to switch a MOSFET from OFF to ON state (typical values of S for bulk CMOS devices are 70-110 mV/decade; the theoretical lower bound is 60 mV/decade corresponding to n=1.) This is especially important for modern MOSFETs with supply voltages reaching sub-one volt region. To minimize S, the thinnest possible gate oxide (since it increases Cox) and the lowest possible doping concentration in the channel (since it decreases CDEP) must be used. Higher temperature results in larger S value, and hence, an increase in the OFF leakage current.

In long channel devices, the influence of source and drain on the channel depletion layer is negligible. However, as channel lengths are reduced, overlapping source and drain depletion regions cause the depletion region under the inversion layer to increase. The wider depletion region is accompanied by a larger surface potential, which attracts more electrons to the channel. Therefore, a smaller amount of charge on the gate is needed to reach the onset of strong inversion and the threshold voltage decreases. This effect is worsened when there is a larger bias on the drain since the depletion region becomes even wider. More precisely,

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when a high drain voltage is applied to a short-channel device, it lowers the barrier for electrons between the source and the channel, resulting in further decrease of the threshold voltage. The source then injects carriers into the channel surface (independent of gate voltage), causing an increase in IOFF. This phenomenon, which can be thought of as a lowering of VTH as VDS increases, is the DIBL effect. There is yet another phenomenon known as the VTH Roll-off whereby the VT of a MOSFET decreases as the channel length is reduced. In such a case, the subthreshold swing parameter degrades and the impact of drain bias on VTH increases. Finally, there is the well-known Body Effect ,which causes an increase in VTH as the body of the transistor is reverse-biased (i.e., VSB of an NMOS transistor is increased).

Clearly, decreasing the threshold voltage increases the leakage current exponentially. In fact decreasing the threshold voltage by 100mV increases the leakage current by a factor of 10. Decreasing the length of transistors increases the leakage current as well. Therefore, in a chip, transistors that have smaller threshold voltage and/or length due to process variation contribute more to the overall leakage.

Figure 2: ISUB (VGS=0) trend as a function of temperature. Courtesy of Vivek De, Intel.

The subthreshold leakage current increases with temperature. Figure 2 shows the leakage current for several technologies for different temperatures. As one can see, IOFF grows in each generation. Furthermore, in a given technology, the leakage current increases with the temperature. Ioff has a temperature sensitivity of 8-12 x/100oC.

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Figure 3: Power consumption of a die as a function of temperature. Courtesy of Vivek De, Intel. Figure 3 shows the power consumption of a 15mm die fabricated in a 0.1 m technology with a supply voltage of 0.7V. Although the leakage power is only 6% of the total power consumption at 30C, it becomes 56% of the total power at 110C. This clearly shows the necessity of using leakage power reduction techniques in current designs. Putting it all together, Let IOFF denote the leakage of an OFF transistor (VGS=0V for an NMOS device).From the above discussion, we know thatIOFF=IREV+IGIDL+ISUB...(4) Clearly, IREV and IGIDL are maximized when VDB = VDD. Similarly, for short-channel devices, ISUB increases with VDB because of the DIBL effect. Note the IG is not a component of the OFF current, since the transistor gate must be at a high potential with respect to the source and substrate for this current to flow. Among the three components of IOFF, ISUB is clearly the dominant component. So the remainder of this paper focuses on ISUB. More precisely, in the next two sections, methods are presented for decreasing the subthreshold leakage currents in circuits that are in STANDBY or ACTIVE state. STACK EFFECT:

To limit the energy and power increase in future CMOS technology generations, the supply voltage (VDD) will have to continually scale [9]. The amount of energy reduction depends on the magnitude of VDDscaling[10]. Along with VDDscaling, the threshold voltage (Vt) of MOS devices will have to scale to sustain the traditional 30% gate delay reduction. These VDDand Vt scaling requirements pose several technology and circuit design challenges [11]. One such challenge is the rapid increase in sub-threshold leakage power due to Vtscaling. Should the present scaling trend continue it is expected that the sub-threshold leakage power will become a considerable constituent of the total dissipated power[12]. In such a system it becomes crucial to identify techniques to reduce this leakage power component. It has been shown previously that the stacking of two off devices has significantly reduced sub threshold leakage compared to a single off device[13]. This concept of stack effect is illustrated in Figure 4.

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Figure 4: Leakage Current Difference between a Single OFF Device and a Stack of Two OFF Devices. As Illustrated by the energy Band Diagram, the Barrier Height is modulated to be higher for the Two-Stack due to Smaller Drain-to Source Voltage Resulting in Reduced Leakage.

Stack effect factor is defined as the ratio of the leakage current in one off device to the leakage current in a stack of two off devices. One solution to the problem of ever-increasing leakage is to force a non-stack device to a stack of two devices without affecting the input load. By ensuring iso-input load, the previous gates delay and the switching power will remain unchanged. Logic gates after stack forcing will reduce leakage power, but incur a delay penalty.

[1.1.2].GATE DIRECT TUNNELLING LEAKAGE

The gate leakage flows from the gate thru the leaky oxide insulation to the substrate. In oxide layers thicker than 34 nm, this kind of current results from the Fowler-Nordheim tunnelling of electrons into the conduction band of the oxide layer under a high applied electric field across the oxide layer. For lower oxide thicknesses (which are typically found in 0.15m and lower technology nodes), however, direct tunnelling through the silicon oxide layer is the leading effect. Mechanisms for direct tunnelling include electron tunnelling in the conduction band (ECB), electron tunnelling in the valence band (EVB), and hole tunnelling in the valence band (HVB), among which ECB is the dominant one. The magnitude of the gate direct tunnelling current increases exponentially with the gate oxide thickness Tox and supply voltage VDD. In fact, for relatively thin oxide thicknesses (in the order of 2-3 nm), at a VGS of 1V, every 0.2nm reduction in Tox causes a tenfold increase in IG [3]. Gate leakage increases with temperature at only about 2x/100oC. Note that the gate leakage for a PMOS device is typically one order of magnitude smaller than that of an NMOS device with identical Tox and VDD when using SiO2 as the gate dielectric. As transistor length and supply voltage are scaled down, gate oxide thickness must also be reduced to maintain effective gate control over the channel region. Unfortunately this results in an exponential increase in the gate leakage due to direct tunnelling of electrons through the gate oxide [4]. An effective approach to

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overcome the gate leakage currents while maintaining excellent gate control is to replace the currently-used silicon dioxide gate insulator with high-K dielectric material such as TiO2 and Ta2O5. Use of the high-k dielectric will allow a less aggressive gate dielectric thickness reduction while maintaining the required gate overdrive at low supply voltages [5]. According to the 2003 International Technology Roadmap for Semiconductors (ITRS-03) [6], high-K gate dielectric is required to control the direct tunnelling current for low standby power devices in process technology nodes below 90 nm. High-K gate dielectrics are expected to be introduced in 2006.

[1.1.3]GATE-INDUCED DRAIN LEAKAGE

The gate induced drain leakage (GIDL) is caused by high field effect in the drain junction of MOS transistors. For an NMOS transistor with grounded gate and drain potential at VDD, significant band bending in the drain allows electron-hole pair generation through avalanche multiplication and band-to-band tunnelling. A deep depletion condition is created since the holes are rapidly swept out to the substrate. At the same time, electrons are collected by the drain, resulting in GIDL current. This leakage mechanism is made worse by high drain to body voltage and high drain to gate voltage. Transistor scaling has led to increasingly steep halo implants, where the substrate doping at the junction interfaces is increased, while the channel doping is low. This is done mainly to control punch-through and drain-induced barrier lowering while having a low impact on the carrier mobility in the channel. The resulting steep doping profile at the drain edge increases band to band tunnelling currents there, particularly as VDB is increased. Thinner oxide and higher supply voltage increase GIDL current. As an example, with a VDG=3V and Tox of 4nm, there is roughly a 10 fold increase in the GIDL current when VDB is increased from 0.8V to 2.2V.

[1.1.4].JUNCTION LEAKAGE The junction leakage occurs from the source or drain to the substrate through the reverse biased diodes when a transistor is OFF. A reverse-biased pn junction leakage has two main components: one is minority carrier diffusion/drift near the edge of the depletion region; the other is due to electron-hole pair generation in the depletion region of the reverse-biased junction [7]. For instance, in the case of an inverter with low input voltage, the NMOS is OFF, the PMOS is ON, and the output voltage is high. Subsequently, the drain-to-substrate voltage of the OFF NMOS transistor is equal to the supply voltage. This results in a leakage current from the drain to the substrate through the reverse-biased diode. The magnitude of the diodes leakage current depends on the area of the drain diffusion and the leakage current density, which is in turn determined by the doping concentration. If both n and p regions are heavily doped, band-to-band tunnelling (BTBT) dominates the pn junction leakage [8]. Junction leakage has a rather high temperature dependency i.e., as much as 50 100 x/100 oC, but it is generally inconsequential except in circuits designed to operate at high temperatures (> 150oC.) Junction reverse-bias leakage components from both the source-drain diodes and the well diodes are generally negligible with respect to the other three leakage components.

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[1.2] DIGITAL GATE TIMING DEFINITION:

Switching Speed - limited by time taken to charge and discharge, the capacitor CL.

Rise Time, TR: waveform to rise from 10% to 90% of its steady state value

Fall Time TF: 90% to 10% of steady state value

Delay Time, TD: time difference between input transition (50%) and 50% output level

The below expression denotes average delay where pLH defines the Response Time of the gate for a Low to High Output Transition and pHL refers to Low to High Transition. The P of a gate defines how quickly it responds to a change at its output.

P=( pLH+ pHL)/2..........(5)

Figure 5: Depiction Of Delay In The Response Time Of The Gate In Accordance With The Input Signal.

Figure 6: CMOS Inverter with a Capacitative Load, CL , to Examine the Average Delay.

Figure 6, shows the familiar CMOS inverter with a capacity load C(input of next gates, output of this gate and routing). Of interest is the voltage waveform Vout(t) when the input is driven by a step waveform, Vin(t) as shown in figure

Figure 8 shows the trajectory of the n0V to VDD. Initially, the end-device is cuX1 on the characteristic curve. Application of a step voltage (Vthe operating point to X2. From there onwards the trajectory moves on the Vtowards point X3 at the origin. Thus it is evident that the fall time consists of two intervals:

1. TF1=period during which the capacitor voltage, V

2. TF2=period during which the capacitor voltage, V

Figure 7: VOUT(t) when the Input Is Driven By A Step Waveform, VWith further calculations it is found out that the expression for fall time is given by

TF = kn .CL/VDD .Bn...........(6)

From this expression we can see that the delay is directly prachieve high speed circuits one has to minimize the load capacitance seen by a gate. Secondly it is inversely proportion to the supply voltage i.e. as the supply voltage is raised the delay time is reduced. Finaldelay is proportional to the n of the driving transistor so increasing the width of a transistor decreases the delay.

Thus the fall time is faster than the rise time primarily due to different carrier mobility associated with the p and n devices thus if we want TF=TR

Figure 8: Trajectory o

shows the familiar CMOS inverter with a capacity load CL that represents the load capacitance (input of next gates, output of this gate and routing). Of interest is the voltage waveform Vout(t) when the

iven by a step waveform, Vin(t) as shown in figure 7.

shows the trajectory of the n-transistor operating point as the input voltage, Vin(t), changes from device is cut-off and the load capacitor is charged to V

X1 on the characteristic curve. Application of a step voltage (VGS = VDD) at the input of the inverter changes the operating point to X2. From there onwards the trajectory moves on the VGS= V

origin. Thus it is evident that the fall time consists of two intervals:

=period during which the capacitor voltage, VOUT, drops from 0.9VDD to (VDD=period during which the capacitor voltage, VOUT, drops from (VDDVTN) to 0.1V

(t) when the Input Is Driven By A Step Waveform, VWith further calculations it is found out that the expression for fall time is given by

From this expression we can see that the delay is directly proportional to the load capacitance. Thus to achieve high speed circuits one has to minimize the load capacitance seen by a gate. Secondly it is inversely proportion to the supply voltage i.e. as the supply voltage is raised the delay time is reduced. Final

n of the driving transistor so increasing the width of a transistor decreases the

Thus the fall time is faster than the rise time primarily due to different carrier mobility associated with the p TF=TR so, width of the pmos must be greater than that of nmos.

Figure 8: Trajectory of N-Transistor Operating Point

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that represents the load capacitance (input of next gates, output of this gate and routing). Of interest is the voltage waveform Vout(t) when the

transistor operating point as the input voltage, Vin(t), changes from off and the load capacitor is charged to VDD. This illustrated by

) at the input of the inverter changes = VDD characteristic curve

origin. Thus it is evident that the fall time consists of two intervals:

DDVTN)

) to 0.1VDD.

(t) when the Input Is Driven By A Step Waveform, VIN(t) With further calculations it is found out that the expression for fall time is given by

oportional to the load capacitance. Thus to achieve high speed circuits one has to minimize the load capacitance seen by a gate. Secondly it is inversely proportion to the supply voltage i.e. as the supply voltage is raised the delay time is reduced. Finally, the

n of the driving transistor so increasing the width of a transistor decreases the

Thus the fall time is faster than the rise time primarily due to different carrier mobility associated with the p mos must be greater than that of nmos.

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[1.3] PVT (Process Voltage Temperature) Variations: As technology scales down to the deep sub-micron regime, the effects of semiconductor process variations are an increasingly significant and critical factor in the design of high performance CMOS circuits. Furthermore, as the process steps involved in the manufacture an IC becomes more complex as the overall circuit performance is now more sensitive to the underlying statistical process variations. Hence a precise knowledge of the effects of process variations is emerging as an integral part of the design methodology. This variation negatively impacts on circuit performance, and generates design specifications which are harder to meet, resulting in functional and parametric yield loss. Moreover, with technology scaling, these problems are becoming increasingly critical due to the tighter design requirements.

In semiconductor manufacturing, a process corner is an example of a design-of-experiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes the design is considered to have inadequate design margin.

In order to verify the robustness of an integrated circuit design, semiconductor manufacturers will fabricate corner lots, which are groups of wafers that have had process parameters adjusted according to these extremes, and will then test the devices made from these special wafers at varying increments of environmental conditions, such as voltage, clock frequency, and temperature, applied in combination (two or sometimes all three together) in a process. Corner-lot analysis is most effective in digital electronics because of the direct effect of process variations on the speed of transistor switching during transitions from one logic state to another.

One naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P channel (PMOS) corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobility that is higher and lower than normal, respectively. For example, a corner designated as FS denotes fast NFETs and slow PFETs.

There are therefore five possible corners: typical-typical (TT) (not really a corner of an n vs. p mobility graph, but called a corner, anyway), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). The first three corners (TT, FF, SS) are called even corners, because both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit. The resulting devices can function at slower or faster clock frequencies, and are often binned as such. The last two corners (FS, SF) are called "skewed" corners, and are cause for concern. This is because one type of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge.

Leakage current is a major drawback in nanoscale CMOS. Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits.

In nanometreCMOS circuits, the main leakage components are the subthreshold, gate-tunneling and reverse-biased junction band-to-band-tunnelling (BTBT) leakage currents. As transistor geometries decrease, it is necessary to reduce the supply voltage to avoid electrical breakdown and obtain the required performance.

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However, to retain or improve performance, it is necessary to reduce the threshold voltage (Vth) as well, which results in an exponential increase of subthreshold leakage. To control short-channel effect and increase the transistor driving strength in deep-submicron (DSM) circuits, gate-oxide thickness also becomes thinner as technology scales down.

The aggressive scaling in the gate oxide results in a tunnelling current through the oxide, which is a strong exponential function of the oxide thickness and the voltage magnitude across the oxide. In scaled devices, the higher substrate doping density and the application of halo profiles cause significantly large reverse-biased junction BTBT leakage currents through the drain- and source-substrate junctions. We have used two different process corners model. Firstly, Nominal Model, in this model the corner type is TT i.e. Typical Typical, the Voltage is 1.0V and the operating Temperature is 27 C. The other model is FF i.e. Fast Fast corner based. For this variational model the Voltage is 1.1V. It is used for three different operating Temperatures, which are 0 C, 27 C and 110 C.

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CHAPTER [2] :SIMULATION Technology used: PTM 45nm Model File.

Tools used: Tanner Tool

[2.1].SIZING OF STANDARD CELLS: Another important factor for our study is proper sizing of PMOS and NMOS such that the equivalent resistance of the p network and the n network is always same .

The expression for RON = L/(KW(Vgs- Vt Vds)) ........(6) when the MOS is in Linear Region.

Where W is the width of the MOS.

When NMOSes are connected in series then to get resistance of p network and n network to be same (R) that is equivalent to an inverter, resistance of each MOS should be R/n where R is the required equivalent resistance. Now as resistance is inversely proportional to width, so the width of the MOS es in series has to be increased n*times.But when NMOS es are connected in parallel we consider the discharging time topology that is the lesser the value of resistance the faster an RC network would discharge. So each of the parallel networks should have least resistance that is resistance equal to the equivalent inverter resistance that is R. So, each of the MOS in parallel will have same width.

[2.2] Fanout-4

This inverter circuit is then used as a block for ease of simulation.

Figure 7: Fanout-4 Inverter Circuit

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0

5

10

15

20

25

30

35

40

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Delay vs. Wp/Wn

Rise Delay Fall Delay

Data for 45 nm Nominal Model:

Wp Wn Wp/Wn Output Rise Output Fall Rise Delay Fall Delay Average Delay

1.67 3.33 0.501502 11.79 30.52 36.35 11.79 24.07

2.5 2.5 1 48.9188 28.5188 25.299 14.8419 20.07045

3 2 1.5 42.874 30.43 22.543 16.5935 19.56825

3.33 1.67 1.994012 40.692 33.092 21.675 18.225 19.95

3.57 1.43 2.496503 40.0456 36.12 21.439 19.905 20.672

3.73 1.27 2.937008 40.1486 38.942 21.5062 21.4087 21.45745

3.75 1.25 3 40.1972 39.3532 21.527 21.626 21.5765

3.89 1.11 3.504505 40.7889 42.7147 21.768 23.3884 22.5782

4 1 4 41.618 46.109 22.078 25.1 23.589

Plot for Rise & Fall Delay against ratio Wp/Wn for 45 nm Nominal Model

It is observed that Rise Delay and Fall Delay is equal for Wp/Wnas 3:1 for 45nm nominal which forms the basis of our further simulations study.

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[2.3] LOGICAL EFFORT The method of logical effort is founded on a simple model of the delay through a single MOS logic gate. The model describes delays caused by the capacitive load that the logic gate drives and by the topology of the logic gate. Clearly, as the load increases, the delay increases, but delay also depends on the logic function of the gate. Inverters, the simplest logic gates, drive loads best and are often used as amplifiers to drive large capacitances. Logic gates that compute other functions require more transistors, some of which are connected in series, making them poorer than inverters at driving current. Thus a NAND gate has more delay than an inverter with similar transistor sizes that drives the same load. The method of logical effort quantifies these effects to simplify delay analysis for individual logic gates and multistage logic networks.

The logical effort of a logic gate tells how much worse it is at producing output current than is an inverter, given that each of its inputs may present only the same input capacitance as the inverter. Reduced output current means slower operation, and thus the logical effort number for a logic gate tells how much more slowly it will drive a load than would an inverter. Equivalently, logical effort is how much more input capacitance a gate must present in order to deliver the same output current as an inverter. It is measured as a ratio of capacitance of an input pin for a particular gate to that for an inverter.It is dependent on the width of each transistor.

Some of the standard cells with sizing is given below:

Figure 8: Schematic diagram of 3 input NOR

This is Three Input NOR circuit. All the NMOS in the Pull-Down network are in parallel to each other, so width of individual NMOS does not change, as already mentioned. In the Pull-Up network, all the PMOS are in series, so individual resistance of PMOS will get divided by 3 and since width is inversely proportional to the resistance, the width of the PMOS should increases 3 fold, that is PMOS have 9mwidth and NMOS have 1 m width.

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Logical effort of pin with voltage source 2 is 2.5, with voltage source 3 is 2.5 , with voltage source 4 is 2.5 since they have same width.

Figure 9: Schematic Diagram of OAI (A+B).C) In the Pull-Down network, (A+B) and C are in series so equivalent width of (A+B) and C should be 2m. And as A and B are in parallel so each should have width 2m.

For the Pull-Up network, (A+B) are in parallel with C. So, (A+B) and C should have width 3m. And as A and B are in series so each has width increased 2 times as two are in series. Hence, Width of PMOS_A and PMOS_B is 6m. Width of PMOS_C is 3m

Logical Effort for Pin A and Pin B is 2, whereas, the Logical Effort for Pin C is 1.25 .

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Figure 10: Schematic Diagram of AOI (AB+C) For the given AOI circuit,

In the Pull-Down network, A and B are in series with C in parallel with them. So, A, B and C must have same width as they are the part of a parallel network. So their widths are 1m each of A, B and C.But individually A and B are in series so width increases 2 folds. Hence, Width of NMOS_A and NMOS_B is 2m. Width of NMOS_C is 1m

In the Pull-Up network A and B are in parallel with each other and is in series with C. Similarly A and B have a width of 6 micron such that the equivalent width is 3micron.

Logical Effort for Pin A and Pin B is 2, whereas, the Logical Effort for Pin C is 1.75

In similar way we can find the logical effort for other Standard cells, which are as follows,

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Table for Logical Effort of Various Circuits:

Cell Input Pin Logical Effort

2 Input NOR A 1.25

B 1.25

3 Input NOR

A 2.5

B 2.5

C 2.5

2 Input NAND A 1.25

B 1.25

3Input NAND

A 1.5

B 1.5

C 1.5

AOI

A 2

B 2

C 1.75

OAI

A 2

B 2

C 1.25

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[2.4] PROCESS CORNER FOR MAXIMUM LEAKAGE:

[2.4.1] Inverter Circuit:

Figure 11: Schematic Diagram of Inverter

Process Voltage (in V)

Temperature (C)

Input Vector

Total Leakage Current ILEAKAGE(nA) Remarks

TT 1.0 27 0 90.39

-

1 149.4

FF 1.1 0 0 640.5 Maximum

Leakage 1 1302.0

FF 1.1 27 0 600.1

-

1 1212.0

FF 1.1 110 0 556.3

-

1 1067.0

From the above data, it is observed that for the PVT variation, according to Nominal Model (TT 27 C), the Leakage current is Minimum, and for FF 0C, it is the worst condition as Leakage current is Maximum.

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[2.4.2] NAND Circuit:

Figure 12: Schematic Diagram of2 Input NAND Gate


Temperature (C)

Input Vector Total Leakage Current

ILEAKAGE(in nA) Remarks

A B

TT

1.0

27

0 0 11.82

-

0 1 181.3

1 0 57.79

1 1 291.8

FF

1.1

0

0 0 26.58

Maximum Leakage

0 1 1279

1 0 290.3

1 1 3416

FF

1.1

27

0 0 2689

-

0 1 1200

1 0 281.4

1 1 3079

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From the above data it is observed that for the PVT variation, according to Nominal Model (TT 27 C), the Leakage current is Minimum and for FF 0 C, it is the worst condition as Leakage current is Maximum.

[2.4.3]NOR Circuit

Figure 13: Schematic Diagram of2 Input NOR Gate

From the above data it is observed that for the PVT variation, according to Nominal Model (TT 27 C), the Leakage current is Minimum and for FF 0 C, it is the worst condition as Leakage current is Maximum.

Hence from the above three circuits we can conclude that, for Minimum Leakage the Nominal Model is suitable. So for the all the circuits further to be used in this project, the model file that will be used is the Nominal Model where the Process Corner is TT (Typical Typical), Voltage VDD is 1.0 V and operating Temperature is 27 C.


Temperature (C)

Input Vector Total Leakage Current

ILEAKAGE(nA) Remarks

A B

TT

1.0

27

0 0 1738

-

0 1 112

1 0 1051.2

1 1 4.0

FF

1.1

0

0 0 3564

Maximum Leakage

0 1 502

1 0 39.8

1 1 10.56

Y= A+B

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[2.5] LEAKAGE ANALYSIS FOR VARIOUS INPUT VECTOR OF SIZED VLSI STANDARD CELLS

[2.5.1] INVERTER

Figure 14: Circuit Diagram for Inverter

Figure 15: Schematic diagram of inverter

1

5

2

3

4

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Ammeter Index Type

Leakage current(nA)

Input Vector

0 1

1 Gate current of PMOS_1 N N

2 Source current of PMOS_1 90.38 149.4

3 Substrate current of PMOS_1 N N

4 Drain current of PMOS_1 & NMOS_1 90.18 149.5

5 Gate current of NMOS_1 -3.6 15

6 Substrate current of NMOS_1 N N

7 Source current of NMOS_1 86.58 165.5

8 Total Leakage 90.39 149.4

N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.

Using KCL:

Input Vector

Drain Current

(nA)

Source Current

(nA)

Gate Current

(nA)

Substrate Current

(nA) PMOS_1

0 90.18 90.38 N N

NMOS_1 90.18 86.58 -3.6 N

PMOS_1 1

149.5 149.4 N N

NMOS_1 149.5 165.5 15 N


Analysis:

In order to maintain the ratio Wp:Wn= 3:1, the equivalent resistance of the Pull-Up Network and Pull-Down Network must remain the same. To achieve this, the width of PMOS is 3 m and the width of NMOS is 1m.

It is observed that the substrate leakage is negligible for both NMOS and PMOS and the gate leakage is negligible for PMOS. So body effect is not playing any crucial role here. So for our further study we are neglecting substrate leakage.

Another interesting conclusion is that the gate current when the NMOS is on is greater than the gate current when the NMOS is off. The first current is called the tunnelling current and the second current of the NMOS which is off is due to gate induced drain leakage. The ratio that we obtained is 4.16 for inverter which is the basic circuit in our study. Very similar ratios are obtained for other standard cells, which has been discussed later.

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[2.5.2] 2 INPUT NAND

Figure 16: Circuit Diagram for 2 Input NAND Gate

Figure 17: Schematic diagram of 2 input NAND

4 4

9 4

2 4

11 4

3 4

1 4

10 4

5 4

12 4

6 4

7 4

8 4

4

1

2

3

5

6

7

8

9

10

11

11

12

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Ammeter Index Type

Leakage current(nA)

Input vector

0 0 0 1 1 0 1 1

1 Gate current of PMOS_1 N N N N

2 Source current of PMOS_1 5.907 N N 149.4

3 Drain current of PMOS_1 5.7 181.1 N 149.5

4 Total Leakage 11.81 181.3 57.78 298.8

5 Drain current of NMOS_1 11.4 181.1 57.58 299

6 Source current of NMOS_1 &Drain

current of NMOS_2 4.164 173.9 57.62 311

7 Gate current of NMOS_2 N -31.45 1.452 -30

8 Source current of NMOS_2 4.161 205.9 56.24 363.1

9 Source current of PMOS_2 5.907 N 57.78 149.4

10 Gate current of PMOS_2 N N N N

11 Drain current of PMOS_2 5.7 N 57.58 149.5

12 Gate current of NMOS_1 -7 -7 N 32.66


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Using KCL

Input vector Drain Current (nA) Source

Current (nA)

Gate Current (nA)

PMOS_1

0 0

5.7 5.907 N

PMOS_2 5.7 5.907 N

NMOS_1 11.4 4.164 -7

NMOS_2 4.164 4.161 N

PMOS_1

0 1

181.1 181.3 N

PMOS_2 N N N

NMOS_1 181.1 173.9 -7

NMOS_2 173.9 205.9 -31.45

PMOS_1

1 0

N N N

PMOS_2 57.58 57.78 N

NMOS_1 57.58 57.62 N

NMOS_2 57.62 56.24 1.452

PMOS_1

1 1

149.5 149.4 N

PMOS_2 149.5 149.4 N

NMOS_1 299 311 12.66

NMOS_2 311 342.1 -30


Analysis:

In order to maintain the ratio Wp:Wn= 3:1, the equivalent resistance of the Pull-Up Network and Pull-Down Network must remain the same. To achieve this, the width of PMOS is 3 m and the width of NMOS is 2 m.

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FACTORS AFFECTING LEAKAGE IN 2-INPUT NAND GATE:

A B Total Leakage Current (nA) Factor Affecting Leakage Current

1. 0 0 11.81 best case Stack Effect

2. 0 1 181.3 -

3. 1 0 57.78 -

4. 1 1 298.8 worst case PMOS devices leaking in parallel

From the data, it is observed that the fundamental Network Theory i.e. Kirchhoffs Law has been obeyed at every node, here, we are considering NMOS and PMOS as nodes.

Due to the stacking effect, leakage through a logic gate depends on the applied input vector. To evaluate the effect of input vector selection in controlling leakage, the pull-down network of the two input NAND gate (a two-transistor stack) is considered. With both gates at logic 0, the intermediate node voltage is positive (Vm), resulting in a negative value of Vgs1. This reduces the sub threshold current in M1. With all other input vectors, Vgs of NMOS_1and NMOS_2 are either positive or zero. Thus, 00 gives the minimum sub threshold current flowing through a stack of two transistors. It has been shown that sub threshold current flowing through a stack of transistor decreases with an increase in the number of the off transistors.

Whereas, maximum leakage current is obtained when the input vector is 11. In this condition, both the NMOS are ON but both the PMOS are OFF. As the PMOS are in Parallel, both the devices will leak and the sum of it results in a higher Leakage current than that of rest cases.

Logical effort at input A&B is 1.25.

[2.5.3] 3 INPUT NAND

Figure 18

Figure 19

Figure 18: Circuit Diagram for 3 Input NAND Gate

Figure 19: Schematic diagram of 3 input NAND

= (A.B.C.)

Page 30 of 51

= (A.B.C.)

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Ammeter Index

Type

Leakage Current(nA)

Input Vector

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

1 Total Leakage Current 14.41 17.55 11.33 272.1 9.03 86.7 74.9 448.1

2 Drain Current of PMOS_1 4.2 8.77 5.6 272.1 N N N 149.4

3 Drain Current of PMOS_2 4.8 8.77 N N 4.5 86.7 N 149.4

4 Drain Current of PMOS_3 4.8 N 5.6 N 4.5 N 74.8 149.4

5 Source Current of PMOS_1 4.49 8.5 5.4 271.9 N N N 149.4

6 Source Current of PMOS_2 4.49 8.5 N N 4.3 86.4 N 149.4

7 Source Current of PMOS_3 4.49 N 5.4 N 4.3 N 74.89 149.4

8 Gate Current of PMOS_3 N N N N N 0 N N

9 Gate Current of NMOS_1 -10 -10 -10 -10 N N 88.5 50

10 Drain Current of NMOS_1 13.78 17.1 10.9 271.9 8.3 86.4 N 448

11 Source Current of NMOS_1 & Drain

Current of NMOS_2 2.91 6.2 N 261 8.6 86.5 88.75 498.6

12 Gate Current of NMOS_2 N N 12 50 -2.8 -2 N 48

13 Source Current of NMOS_2 & Drain

Current of NMOS_3 2.903 6.2 11 309.2 5.6 84.5 89.56 544

14 Gate Current of NMOS_3 N 50 N 50 N 50 -16 48

15 Source Current of NMOS_3 2.903 54.4 10.9 357.3 5.6 132 73.24 592.9


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USING KCL:

Input Vector Drain Current(nA) Gate Current

(nA) Source

Current(nA)

PMOS_1

0 0 0

4.49 N 4.2

PMOS_2 4.49 N 4.8

PMOS_3 4.49 N 4.8

NMOS_1 13.78 -10 2.91

NMOS_2 2.91 N 2.903

NMOS_3 2.903 N 2.903

PMOS_1

0 0 1

8.5 N 8.77

PMOS_2 8.5 N 8.77

PMOS_3 N N N

NMOS_1 17.1 -10 6.2

NMOS_2 6.2 N 6.2

NMOS_3 6.2 50 54.4

PMOS_1

0 1 0

5.4 N 5.6

PMOS_2 N N N

PMOS_3 5.4 N 5.6

NMOS_1 10.9 -10 N

NMOS_2 N 12 11

NMOS_3 11 N 10.9

PMOS_1

0 1 1

271.9 N 272.1

PMOS_2 N N N

PMOS_3 N N N

NMOS_1 271.9 -10 261

NMOS_2 261 50 309.2

NMOS_3 309.2 50 357.3


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Input Vector Drain Current (nA) Gate Current

(nA) Source

Current (nA)

PMOS_1

1 0 0

N N N

PMOS_2 4.5 N 4.3

PMOS_3 4.5 N 4.3

NMOS_1 8.3 N 8.6

NMOS_2 8.6 -2.8 5.6

NMOS_3 5.6 N 5.6

PMOS_1

1 0 1

N N N

PMOS_2 86.7 N 86.4

PMOS_3 N N N

NMOS_1 86.4 N 86.5

NMOS_2 86.5 -2 84.5

NMOS_3 84.5 50 132

PMOS_1

1 1 0

N N N

PMOS_2 N N N

PMOS_3 74.8 N 74.8

NMOS_1 N 88.5 88.75

NMOS_2 88.75 N 89.56

NMOS_3 89.56 -16 73.24

PMOS_1

1 1 1

149.4 N 149.4

PMOS_2 149.4 N 149.4

PMOS_3 149.4 N 149.4

NMOS_1 448 50 498.6

NMOS_2 498.6 48 544

NMOS_3 544 48 592.9


Analysis:

In order to maintain the ratio Wp:Wn= 3:1, the equivalent resistance of the Pull-Up Network and Pull-Down Network must remain the same. To achieve this, the width of PMOS is 3 m and the width of NMOS is 3 m.

In our study, we have examined the interdependence between ISUBand IGATE. However IGATEin PMOS transistors and reverse IGATEin OFF transistors was considered negligible. This fact does not hold true for 45nm and 32nm technologies.

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IGATE leakage in the OFF NMOS transistor is comparable to that in the ON NMOS transistor. However, IGATE in PMOS transistors is relatively less than in NMOS transistors and can be safely ignored. Here Substrate Leakage is also ignored.

FACTORS AFFECTING LEAKAGE IN 3-INPUT NAND GATE

A B C Leakage Current (in nA) Factor Affecting Leakage Current

0 0 0 14.41 -

0 0 1 17.55

0 1 0 11.33 -

0 1 1 272.1 -

1 0 0 9.03 best case No IGATEDrawn; Stack Effect

1 0 1 86.7

No Stack Effect; ISUBTDominates 1 1 0 74.9

1 1 1 448.1 worst case

From the data, it is observed that the fundamental Network Theory i.e. Kirchhoffs Law has been obeyed at every node, here, we are considering NMOS and PMOS as nodes.

Leakage Current is found to be minimum for vector 100 because No IGATE is drawn; Stack effect. In this combination, NMOS_1 is ON so it doesnt any gate current from supply voltage. Rests of the two NMOS are OFF and are in series, hence due to Stacking effect lows ISUB flows.

Another Category of input vector is IGATE drawn; Stack Effect. In this combination, NMOS_1 is switched OFF and therefore draws IGATE from power supply. Because there are two OFF NMOS in this combination, low ISUB flows due to stack effect.

In case of vector 010, IGATE replaces ISUB. In such cases where there is a non-conducting transistor above and below a conducting transistor, IGATE replaces ISUB. A positive potential is developed between the NMOS_1 and NMOS_2 due to ISUB flowing through NMOS_1.Thevoltage developed is sufficiently small for NMOS_2 to exhibit IGATE from its gate to drain. IGATE further increases the voltage at the node. This increase in voltage reduces ISUB through NMOS_1 and also reduces IGATE. But the dependence of ISUB on VGS is stronger than the dependence of IGATE onVGD. Thus, IGATE displaces ISUB and remains as the only leakage component in the stack.

The Last category is No Stack Effect; ISUB Dominates, as stack effect is not possible in this case Isub leads to be the dominating factor in leakage. For 111, it is the Worst case as three PMOS are in parallel, hence ISUB from all the PMOS collectively makes it the maximum leakage combination.

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It is observed that for 3ip nand gate max leakage occurs when 3pmos es are in series that is for 111 combination and theoretically min leakage should occur for 000 combination. But this is not the case .We have taken readings of vgs and vds for all 3 nmoses . The nmos with vgs most negative is the limiter of current in the entire circuit for a particular input combination. It is found out that the theoretical and practical values of ratios of channel currents after subtracting the gate leakage current is almost same. The theoretical value is found from the equation of sub threshold current.

100 000

Vds(v) Vgs(v) Vds(v) Vgs(v)

Nmos 1 .225 .225 .984 -.156

Nmos 2 .77 -.105 .129 -.027

Nmos 3 .105 0 .027 0

From the table it is observed for 100 combination Nmos2 is the limiter. After subtracting gate leakage current, channel current for 100 combination is (9.03-2.8)nA= 6.23 nA.

For 000 combination channel current is 14.41nA. So practically ratio of channel current for 100 to 000 is .432.

Isub=I0e((vgs-vth)/n.vt)e(-vds/vt) Putting the values from the above table and taking n to be 2 ,vth=.22v,vt(thermal voltage) =25 mV

we get Isub(100)/Isub(000)= 0.013/0.0298= 0.436

Logical effort at input A, B & C is 1.5

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[2.5.4] 2 input NOR

Figure 20: Circuit Diagram for 2 Input NOR Gate

Y= A+B

Figure 21: Schematic diagram of 2 Input NOR Gate

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AmmeterIndex

Type Leakage current(nA)

Input Vector

0 0 0 1 1 0 1 1

1 Total Leakage Current

181.2 299.3 77.11 3.103

2 Drain Current of PMOS_1 &Source Current of PMOS_2

180.7 298.9 77.16 3.104

3 Drain Current of PMOS_2 180.3 299.1 77.16 3.313

4 Drain Current of NMOS_1 90.17 N 77.16 1.656

5 Drain Current of NMOS_2 90.17 299.1 N 1.656

6 Gate Current of NMOS_1 -3.5 N 16.34 15.95

7 Gate Current of NMOS_2 -3.5 15.95 N 15.95

8 Source Current of NMOS_1 86.57 N 93.11 17.61

9 Source Current of NMOS_2 86.57 315 N 17.61

N=NEGLIGIBLE AMOUNT OF CURRENT

Input Vector Drain Current (nA) Source Current

(nA) Gate Current

(nA) PMOS_1

0 0

180.7 181.2 N

PMOS_2 180.3 180.7 N

NMOS_1 90.17 86.57 -3.5

NMOS_2 90.17 86.97 -3.5

PMOS_1

0 1

298.9 299.3 N

PMOS_2 299.1 298.9 N

NMOS_1 N N N

NMOS_2 299.1 315 15.95

PMOS_1

1 0

77.16 77.11 N

PMOS_2 77.16 77.16 N

NMOS_1 77.16 93.11 16.34

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Analysis:

In order to keep the effective resistance of the p-MOS and n-MOS equal, the width of the p-MOS and n-MOS are fixed at 6u and 1u, respectively, thereby maintaining ratio of Wp :Wn at 3:1.

In both the studies we observe that the fundamental law of network theory i.e. Kirchhoffs Current Law has been obeyed at every node (considering, each mos to be a node).

We also observe that maximum leakage current is obtained when both the sources are set to 0V. This is because both the n-MOS are off simultaneously, and so their individual leakage currents are added up.

Minimum leakage current is obtained when both the sources are set to 1V.This is because of the stack effect, resulting in decrease of the leakage current as the p-MOS are in series

Logical effort at input A & B is 7/4.

NMOS_2 N N N

PMOS_1

1 1

3.104 3.103 N

PMOS_2 3.313 3.104 N

NMOS_1 1.656 17.61 15.95

NMOS_2 1.656 17.61 15.95

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[2.5.5]3 input NOR

Figure 22: Circuit Diagram for 3 Input NOR Gate

A

B

B

A

C

C

Y= (A+B+C)

Figure 23: Schematic diagram of 3 Input NOR Gate

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Ammeter index

Type

Leakage Current (nA)

Input Vector

000 001 010 011 100 101 110 111

1 Total leakage current

272.3 449 116.3 5.281 94.81 4.704 4.098 1.868

2

Drain current of PMOS_1 &

Source current of PMOS_2

271.7 448.4 115.7 4.658 94.87 4.705 4.099 1.868

3

Drain current of PMOS_2 &

Source current of PMOS_3

271.7 447.8 115.8 4.658 94.87 4.36 4.233 1.869

4 Drain current of PMOS_3 270.5 448.1 115.8 4.971 94.87 4.674 4.234 2.183

5 Drain current of NMOS_1 90.16 N N N 94.86 2.337 2.117 N

6 Drain current of NMOS_2 90.16 N 115.8 2.486 N N 2.117 N

7 Drain current of NMOS_3 90.16 448.1 N 2.486 N 2.337 N N

8 Source current of NMOS_1 86.56 N N N 110.8 18.29 18.07 16.68

9 Source current of NMOS_2 86.56 N 131.7 18.43 N N 18.07 16.68

10 Source current of NMOS_3 86.56 464 N 18.43 N 18.29 N 16.68

11 Gate current of

NMOS_1 -3.516 N N N 16.3 16.3 16.3 16.3

12 Gate current of NMOS_2 -3.516 N 16.3 16.3 N -N 16.3 16.3

13 Gate current of NMOS_3 -3.516 16.3 N 16.3 N 16.3 N 16.3


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Using KCL

Input Vector Source Current

(nA)

Drain Current

(nA)

Gate Current

(nA)

PMOS_1

000

272.3 271.7 N

PMOS_2 271.7 271.7 N

PMOS_3 271.7 270.5 N

NMOS_1 86.56 90.16 -3.516

NMOS_2 86.56 90.16 -3.516

NMOS_3 86.56 90.16 -3.516

PMOS_1

001

449 448.4 N

PMOS_2 448.4 447.8 N

PMOS_3 447.8 448.1 N

NMOS_1 N N N

NMOS_2 N N N

NMOS_3 464 448.1 16.3

PMOS_1

010

116.3 115.7 N

PMOS_2 115.7 115.8 N

PMOS_3 115.8 115.8 N

NMOS_1 N N N

NMOS_2 131.7 115.8 16.3

NMOS_3 N N N

PMOS_1

011

5.281 4.658 N

PMOS_2 4.658 4.658 N

PMOS_3 4.658 4.971 N

NMOS_1 N N N

NMOS_2 18.43 2.486 16.3

NMOS_3 18.43 2.486 16.3

PMOS_1

100

94.81 94.87 N

PMOS_2 94.87 94.87 N

PMOS_3 94.87 94.87 N

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NMOS_1 110.8 94.86 16.3

NMOS_2 N N N

NMOS_3 N N N

PMOS_1

101

4.704 4.705 N

PMOS_2 4.705 4.36 N

PMOS_3 4.36 4.674 N

NMOS_1 18.29 2.337 16.3

NMOS_2 N N N

NMOS_3 18.29 2.337 16.3

PMOS_1

110

4.098 4.099 N

PMOS_2 4.099 4.233 N

PMOS_3 4.233 4.234 N

NMOS_1 18.07 2.117 16.3

NMOS_2 18.07 N 16.3

NMOS_3 N 2.117 N

PMOS_1

111

1.868 1.868 N

PMOS_2 1.868 1.869 N

PMOS_3 1.869 2.183 N

NMOS_1 16.68 N 16.3

NMOS_2 16.68 N 16.3

NMOS_3 16.68 N 16.3


Analysis: In order to keep the effective resistance of the p-MOS and n-MOS equal, the width of the p-MOS and n-MOS are fixed at 9u and 1u, respectively, thereby maintaining ratio of Wp :Wn at 3:1.

We observe that the fundamental law of network theory i.e. Kirchhoffs Current Law has been obeyed at every node(considering, each mos to be a node).

Minimum leakage current is obtained when both the sources are set to 1V.This is because of the stack effect, resulting in decrease of the leakage current as the p-MOS are in series.

Maximum leakage current is observed in the case of 0 0 1.

Logical effort at input A, B & C is 2.5

[2.5.6] AOI (A.B+C)

Figure 24

Figure 25

Figure 24: Circuit diagram of AOI (AB+C)

Figure 25: Schematic diagram of AOI (AB+C)

Page 43 of 51

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Leakage current(nA)

Input Vector

Ammeter Index Type 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

1 Total Leakage 102.8 299.9 272.1 299.3 148.6 299.3 141.6 5.657

2 Source current of PMOS_1 51.41 150 272.1 299.3 N N 70.82 2.829

3 Source Current of PMOS_2 51.41 150 N N 148.6 299.3 70.82 2.829

4 Source Current of PMOS_3 102 299.1 271.7 298.9 148.2 298.9 141.8 5.658

5 Drain Current of PMOS_1 51 149.5 271.7 298.9 N N 70.88 2.829

6 Drain Current of PMOS_2 51 149.5 N N 148.2 298.9 70.88 2.829

7 Drain Current of PMOS_3 101.6 101.6 271.3 299.1 147.7 299.1 141.8 5.867

8 Drain Current of NMOS_1 11.4 N 181.1 N 57.58 -32.04 141.8 -9.091

9 Source current of

NMOS_1 & Drain Current of NMOS_2

4.164 N 173.9 N 57.62 N 173.8 22.97

10 Gate current of NMOS_1 -7.23 N -7.228 N N 30 32.06 32.06

11 Gate current of NMOS_2 N N 33.85 33.85 -1.374 N 32.06 32.06

12 Source current of NMOS_2 4.16 N 205.9 32.07 56.24 N 205.9 55.03

13 Drain Current of NMOS_3 90.18 299.3 90.16 299.1 90.17 331.1 N 14.96

14 Source current of NMOS_3 86.58 315.3 86.58 315 86.57 347 N 30.91

15 Gate current of NMOS_3 -3.6 15.95 -3.39 15.95 -3.59 15.95 N 15.95


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Using KCL

Input Vector Drain Current (nA) Source Current

(nA) Gate Current

(nA) PMOS_1

0 0 0

51 51.41 N

PMOS_2 51 51.41 N

PMOS_3 101.6 102 N

NMOS_1 11.4 4.164 -7.23

NMOS_2 4.164 4.161 N

NMOS_3 90.18 86.58 -3.6

PMOS_1

0 0 1

149.5 150 N

PMOS_2 149.5 150 N

PMOS_3 299.3 299.1 N

NMOS_1 N N N

NMOS_2 N N N

NMOS_3 299.3 315.3 15.95

PMOS_1

0 1 0

271.7 272.1 N

PMOS_2 N N N

PMOS_3 271.3 271.7 N

NMOS_1 181.1 173.9 -7.228

NMOS_2 173.9 205.9 33.85

NMOS_3 90.16 86.56 -3.39

PMOS_1

0 1 1

298.9 299.3 N

PMOS_2 N N N

PMOS_3 299.1 298.9 N

NMOS_1 N N N

NMOS_2 N 32.07 33.85

NMOS_3 299.1 315 15.95

PMOS_1

N N N

PMOS_2 148.2 148.6 N

PMOS_3 147.7 148.2 N

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NMOS_1 1 0 0

57.58 57.62 N

NMOS_2 57.62 56.24 -1.374

NMOS_3 90.17 86.57 -3.59

PMOS_1

1 0 1

N N N

PMOS_2 298.9 299.3 N

PMOS_3 299.1 298.9 N

NMOS_1 -32.04 N 30

NMOS_2 N N N

NMOS_3 331.1 347 15.95

PMOS_1

1 1 0

70.88 70.82 N

PMOS_2 70.88 70.82 N

PMOS_3 141.8 141.8 N

NMOS_1 141.8 173.8 32.06

NMOS_2 173.8 205.9 32.06

NMOS_3 N N N

PMOS_1

1 1 1

2.829 2.829 N

PMOS_2 2.829 2.829 N

PMOS_3 5.867 5.658 N

NMOS_1 -9.091 22.97 32.06

NMOS_2 22.97 55.03 32.06

NMOS_3 14.96 30.91 15.95


Analysis: In order to maintain the ratio Wp:Wn= 3:1, the equivalent resistance of the Pull-Up Network and Pull-Down Network must remain the same. To achieve this, the width of all three PMOSES are 6 m and the width of NMOS_1 & NMOS_2 are 2 m and for NMOS_3 it is 1 m.

We observe that the fundamental law of network theory i.e. Kirchhoffs Current Law has been obeyed at every node(considering, each mos to be a node).

Maximum leakage current is observed in the case of 0 0 1, because AB and C in nmos are in parallel so no stacking effect.

Minimum is observed in 111 where the leaking pmos are in series with pronounced stacking effect.

Logical effort at input A and B is 2, whereas at input C it is 7/4.

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[2.5.7 ]OAI (A+B).C

Figure 26: Schematic diagram of OAI (A+B)C

Figure 26

Ammeter index Type

0 0 01 Total leakage

current 20.01

2 Source current of Pmos_1 10.17

3 Drain current of

pmos_1 and source current of Pmos_3

9.75

4 Drain current of pmos_3 9.33

5 Source current of pmos_2 9.84

6 Drain current of pmos_2 9.63

7 Drain current of Nmos_1 9.48

8 Source current of Nmos_1 2.25

9 source current of Nmos_2 2.25


11 Gate current of nmos_2 7.04

12 Gate current of nmos_1 7.05

13 Gate current of nmos_3 N


15 source current of Nmos_3 4.5

Figure 26: Schematic diagram of OAI (A+B)C Leakage

current(nA) Input Vector

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 20.01 362.7 66.67 448.6 66.67

10.17 362.7 N 299.2 N

9.75 362.7 N 299.2 N

9.33 361.9 N 299.2 N

9.84 N 66.25 149.4 66.25

9.63 N 66.25 149.4 66.66

9.48 181 7.232 N 58.81

2.25 173.7 -1.37 N 58.85

2.25 173.7 58.85 480.5 -1.37

9.48 181 58.85 480.5 7.232

7.04 -7.04 N N -7.9

7.05 -7.05 -8.3 N N

N 32.91 N 32.6 N

4.5 347.5 57.48 480.5 57.48

4.5 379.5 56.11 512.6 56.11 N=NEGLIGIBLE AMOUNT OF CURRENT

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1 0 1 1 1 0 1 1 1 226.5 61.89 152.5

77.1 N 3.103

77.1 N 3.103

77.16 N 3.313

258.7 61.89 149.4

258.7 61.68 149.4

226.7 30.84 76.43

258.7 30.87 108.5

N 30.87 108.5

N 30.87 76.43

-1.74 N 34.62

32.91 N 32.91

32.91 -1.4 34.62

258.7 61.74 217

290.8 60.1 249 N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.

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Using KCL:

Input vector Source Current (nA) Drain current

(nA) Gate current

(nA) PMOS_1

000

10.17 9.75 N

PMOS_2 9.84 9.63 N

PMOS_3 9.75 9.33 N

NMOS_1 2.25 9.48 -7.05

NMOS_2 2.25 9.48 -7.04

NMOS_3 4.5 4.5 N

PMOS_1

011

299.2 299.2 N

PMOS_2 149.4 149.4 N

PMOS_3 299.2 299.2 N

NMOS_1 N N N

NMOS_2 480.5 480.5 N

NMOS_3 512.6 480.5 32.6

PMOS_1

100

N

N

N

PMOS_2 66.25 66.66 N

PMOS_3 N N N

NMOS_1 58.85 58.81 N

NMOS_2 -1.37 7.232 -7.9

NMOS_3

56.11 57.48 N

PMOS_1

101

77.1 77.1 N

PMOS_2 258.7 258.7 N

PMOS_3 77.1 77.6 N

NMOS_1 258.7 226.7 32.91

NMOS_2 N N -1.74

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NMOS_3

290.8 258.7 32.91

PMOS_1

110

N N N

PMOS_2 61.89 61.68 N

PMOS_3 N N N

NMOS_1 30.87 30.84 N

NMOS_2 30.87 30.87 N

NMOS_3

60.1 61.7 -1.4

PMOS_1

111

3.103 3.103 N

PMOS_2 149.4 149.4 N

PMOS_3 3.103 3.313 N

NMOS_1 108.5 76.43 32.91

NMOS_2 108.5 76.43 34.62

NMOS_3

249 217 34.62


Analysis:

Pmos 1 and pmos 3 are in series with pmos 2 in parallel so in the parallel combination width of each is 3microm. Again two pmoses in series has each 6microm width to get equivalent resistance of the p network and the n network same.

Maximum leakage is taking place for 011 combination, with pmos 1 is leaking and is not in stack. So logically this gives the max leakage. Again for 000 combination nmos are leaking and also in stack, so logically this combination gives min leakage

Logical effort at input A and B is 2 and for input C it is 1.25.

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CHAPTER [3]: CONCLUSION

In todays technology reducing stand by power consumption is one of the key design goals for portable devices. In this study we have observed input vector dependency on standby leakage current of VLSI standard cells has been explored for a deep submicron technology(45 nm process node). It is observed also that gate leakage current for NMOS devices is not negligible with respect to the subthreshold leakage current which dominates stand by current in VLSI standard cells. Maximizing stacking effect is the key to achieve min leakage of VLSI standard cells.

REFERENCES:

Minimizing Power Consumption In Digital CMOS circuits ANANTHA P.CHANDRAKASAN and ROBERT W.BRODERSEN, FELLOW, IEEE

CMOS Power Consumption and Cpd Calculation - SCAA035B June 1997 Lectures by Prof. A. N. Chandorkar, IIT-B K.Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, Leakage Current Mechanisms and Leakage

Reduction chniques in Deep-Submicrometer CMOS Circuits, Proceedings of the IEEE, Feb,2003, pp. 305-327

V. De, and S. Borkar, Technology and design challenges for low power and high performance, International Symposium on Low Power Electronics and Design, 1999, pp. 163-168

Y. Taur, and T.H. Ning, Fundamentals of Modern VLSI Devices. New York: Cambridge Univ. Press, 1998.

INPUT VECTOR DEPENDENT LEAKAGE CURRENT OF VLSI STANDARD CELLS IN 45NM TECHNOLOGY

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