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InAlN/GaN high electron mobility transistors on Sifor RF applications

Xing, Weichuan

2018

Xing, W. (2018). InAlN/GaN high electron mobility transistors on Si for RF applications.Doctoral thesis, Nanyang Technological University, Singapore.

https://hdl.handle.net/10356/88831

https://doi.org/10.32657/10220/45971

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InAlN/GaN High Electron Mobility Transistors on Si

for RF Applications

XING WEICHUAN

School of Electrical & Electronic Engineering

2018

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InAlN/GaN High Electron Mobility Transistors on Si

for RF Applications

XING WEICHUAN

School of Electrical & Electronic Engineering

A thesis submitted to the Nanyang Technological University

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy

2018

Statement of Originality

I hereby certify that the work embodied in this thesis is the result of original

research and has not been submitted for a higher degree to any other university or

institution.

--------------------------------- -------------------------------

Date Xing Weichuan

i

Acknowledgements

It is of my great honor to join the GaN HEMT group in Nanyang Technological

University and work closely with so many outstanding researchers in the past few years.

This experience will surely be a precious treasure of my life. Before presenting this thesis,

I would like to express my most sincere appreciations to all the individuals who have

helped me during my Ph.D. tenure.

First and foremost, I am deeply indebted to my supervisor, Professor Ng Geok Ing.

Owing to his foresight, knowledge, experience and rigorous attitude towards research

works, I learned how to think and performance independently as a researcher. It is a great

fortune to be his student and the experience with him will definitely be an impressive and

valuable memory for my whole career.

Next, I would like to present my genuine thankfulness to my co-supervisor Professor

Tomas Palácios for his consistent support and encouragement throughout my PhD study

and research.

I want to present my sincere appreciation to Dr. Liu Zhihong, who taught me

fundamentals and many skills in semiconductor characterization and fabrication process.

His excellent mentorship with rich knowledge and experience has facilitated my research

significantly. In addition, he is always patient in guiding me with a lot of face-to-face

discussions. The experience with Dr. Liu will certainly be great helpful to my future

career.

ii

Special thanks to Dr. Subramaniam Arulkumaran, Dr. Liu Chongyang, Dr. Qiu

Haodong and Kumud Ranjan. Dr. Arulkumaran and Dr. Liu have provided me a lot of

help on the fabrication and characterization process and the fruitful technical discussions.

Dr. Qiu helped me a lot on the Electron Beam Lithography training and recipes

development. Kumud Ranjan has offered his guidance and support on device

characterization.

I am grateful to all my colleagues in GaN HEMT group in Nanyang Technological

University for their fruitful discussions and collaborations with me. They are Dr. Li Yang,

Dr. Ye Gang, Zhang Zecen, Matthew Whiteside and Sandupatla Abhinay.

I appreciate the contribution of all the lab staffs, Muhd Fauzi Bin Abudullah and Seet

Lye Ping in the Characterization Lab, Mohamad Shamsul Bin Mohamad, Mak Foo Wah,

Chuang Kwok Fai, Yang Xiaohong, Ngo Ling Ling, Chong Gang Yih, Irene Chia Ai Lay

etc. in the Nanyang Nano-Fabrication Center for their efforts on maintaining the

equipment which facilitated my device fabrication.

Of course, I will not forget to thank all of my friends and colleagues: Dr. Wang Cong,

Bao Shuyu, Dr. Wei Mengyao, Lin Yiding, Danny Ren, Dr. Wang Bing, Dr. Cheng

Yuanbing, Dr. Wang Xinghui, Dr. Sun Leimeng, Dr. Hu Xiaonan, Dr. Meng Bo, etc., for

their kind support and invaluable friendship.

Finally, my sincere gratitude goes to my parents and my wife who have always

supported me with love. This thesis is dedicated to them.

iii

Abstract

Conventional AlGaN/GaN High Electron Mobility Transistors (HEMTs) have been

proven to be a strong competitor in both high voltage and high frequency applications

resulting from the intrinsic material properties of GaN such as large bandgap, high

electron mobility, high electron saturation velocity and high thermal conductivity. In the

past decades, GaN HEMTs have emerged as one of the hottest research topics and

intensively studied. The performance of conventional AlGaN/GaN HEMTs have been

improved significantly and continuously in the past decades, such as high output power,

high operation frequency and low noise figure. Recently, a novel heterostructure with a

thin layer of InAlN on top of GaN have been demonstrated to further improve the high

frequency performance of GaN HEMTs. Benefiting from the unique properties of

InAlN/GaN hetrostructure such as very thin top barrier thickness, high electron density

and lattice match, the high frequency performance of GaN HEMTs have been pushed to

the next level. On the other hand, there are still some critical challenges limiting the

applications of GaN HEMTs.

On key issue is that most of the high frequency results, especially those above 200

GHz, were reported from devices grown on SiC substrates. SiC has the advantages of

small lattice mismatch to GaN eplilayers, very high resistivity and thermal conductivity.

Thus, GaN HEMTs grown on SiC can achieve higher RF performance than those grown

on Si. However, GaN HEMT on SiC is not cost-effective and is only available in smaller

sizes ( 6 inch) which make it less attractive to be adopted commercially.

iv

To reduce the cost of GaN HEMTs, Si substrates have attracted increasing interest in

recent years, not only in power electronics applications but also in RF applications.

Significant efforts have been made on improving the epitaxial quality of GaN on Si

substrates as well as the device fabrication technology. As a result, the performance of

RF GaN HEMTs on Si has improved significantly. However, the high frequency

performance of GaN HEMTs on Si still lags behind their counterparts on SiC. The best

reported AlGaN/GaN HEMT on Si only exhibited a fT of 176 GHz with for a gate length

of 80 nm.

Another drawback is the poor linearity performance of deeply scaled GaN HEMTs.

Linearity is an important parameter for GaN HEMTs to be applied as amplifiers in

modern communication system. GaN HEMT is expected to maintain high operation

frequency at high gate bias to support its application for large signal RF operation.

However, poor linearity characteristics have been observed in the conventional GaN

HEMTs. It is manifested by a non-flat transconductance (gm) and fT, fmax versus gate bias

(or drain current). After reaching its maximum point, gm or fT, fmax decrease drastically

with the increasing gate bias. Linearity of GaN transistors ultimately limits the power

density and efficiency of these devices in many applications, as the operating point of the

device typically needs to be backed-off to meet the linearity specifications. In fact, as the

operating frequency increases into the mm-wave range by shrinking the gate length, the

linearity is expected to degrade even further.

This thesis mainly focuses on these two issues. Novel approaches are employed to

resolve them and much improved device performance were obtained. The major

contributions of the thesis are listed as below.

v

(1) The factors that limit the devices’ high frequency performance are investigated. A

thin InAlN top barrier is applied instead of conventional AlGaN top barrier in

order to minimize the impact of decreased gate length-to-barrier thickness ratio

and thereby degradation of the gate modulation efficiency. Sub-100 nm gate was

developed using electron beam lithography (EBL) technology to minimize gate

induced intrinsic delay. Parasitic charging delay was minimized benefiting from

the short source-to-drain distance down to 300 nm and low contact resistance Rc

of 0.2 Ω.mm. Maximum fT of 250 GHz was obtained in a 40-nm gate device,

which is the highest among any other GaN HEMTs demonstrated on Si substrate

previously. Surface passivation effects on DC and RF performance were also

investigated.

(2) The mechanism of the poor linearity performance of the gm and fT at high gate

bias was investigated. A novel planar-nanostrip GaN HEMTs structure using ion

implantation technology was developed to improve the linearity performance and

maintain fT at a high level without introducing too much gate parasitic capacitance.

The fabrication process was described in details including As ion implantation for

isolation application, nanostrip-channel formation using different approaches.

Moreover, the planar-nanostrip device also showed much improved maximum

drain current Idmax up to 2.6 A/mm, which is close to the theoretical limit. Also,

device geometries including gate length, line-to-space ratio of the nanostrip-

channel and gate-to-source distance have been studied. These results do not only

identify the origin of the non-linear performance in GaN HEMTs, but also

vi

illustrate the direction of design improvement of RF GaN HEMTs for high

linearity application.

(3) A Planar nanostrip-channel Al2O3/InAlN/GaN MISHEMTs on Si was

demonstrated. A thin layer of oxide between the metal gate and the thin InAlN

barrier and form a metal-insulator-semiconductor (MIS) gate in the Planar

nanostrip-channel GaN HEMT, gate leakage current was reduced and thus

increase the gate voltage swing and drain current swing. The results show that the

Planar nanostrip-channel Al2O3/InAlN/GaN MISHEMTs is able to work at up to

Vg = +4 V and the linearity performance was further improved. Two-tone

intermodulation characterizations are discussed for conventional HEMT, Planar

nanostrip-channel HEMT and MISHEMT. The lower IM3-to-carrier ratio (–

C/IM3) and larger third order intercept OIP3 values of the Planar nanostrip-

channel MISHEMT clearly indicate that the linearity of GaN HEMT was

improved by the planar nanostrip-channel structure as well as the insertion of 6-

nm Al2O3 gate insulator.

vii

Table of Contents

Acknowledgements .............................................................................................................. i

Abstract .............................................................................................................................. iii

Table of Contents .............................................................................................................. vii

List of Figures .................................................................................................................... xi

List of Tables ................................................................................................................. xviii

Chapter 1 Introduction ........................................................................................................ 1

1.1. Overview of GaN based high-electron-mobility transistors (HEMTs) for RF

application ....................................................................................................................... 1

1.2. Issues in GaN HEMTs for RF applications .......................................................... 5

1.2.1. Lack of High Frequency GaN HEMTs on Si substrate .................................... 6

1.2.2. Poor Linearity performance of deeply scaled GaN HEMTs at high gate bias . 8

1.3. Project goal and thesis outline .............................................................................. 9

References ..................................................................................................................... 11

Chapter 2 Fundamentals of GaN HEMTs ......................................................................... 24

2.1. Physics and device design in conventional AlGaN/GaN HEMTs ..................... 24

2.2. Key fabrication process for conventional GaN HEMTs .................................... 29

2.2.1. Mesa Isolation................................................................................................. 30

2.2.2. Ohmic Contact Formation .............................................................................. 31

2.2.3. Gate Formation ............................................................................................... 33

viii

2.2.4. Surface Passivation ......................................................................................... 37

2.3. DC characteristics for GaN HEMTs .................................................................. 37

2.4. RF characteristics for GaN HEMTs ................................................................... 39

Reference ...................................................................................................................... 43

Chapter 3: InAlN/GaN HEMTs on Si with high operation frequency ............................. 45

3.1. Introduction ........................................................................................................ 45

3.2. Limiting factors in GaN HEMTs for high frequency operation......................... 47

3.2.1. Delay analysis model of GaN HEMTs ........................................................... 47

3.2.2. Intrinsic limits in GaN HEMTs ...................................................................... 49

3.2.3. Extrinsic limits in GaN HEMTs ..................................................................... 51

3.2.3.1. Parasitic charging delay .............................................................................. 52

3.2.3.2. Extrinsic delay ............................................................................................ 55

3.3. Device scaling .................................................................................................... 56

3.3.1. Electron beam lithography technology ........................................................... 58

3.3.2. Deeply scaled gate and sub-micron channel................................................... 69

3.4. Thin InAlN top barrier GaN HEMTs on Si........................................................ 75

3.4.1. Advantages in InAlN as top barrier ................................................................ 75

3.4.2. Challenges for high performance GaN HEMTs on Si .................................... 78

3.5. Device fabrication .............................................................................................. 80

3.6. Device characterizations .................................................................................... 81

ix

3.6.1. DC and RF characterizations .......................................................................... 81

3.6.2. Delay analysis and future optimization .......................................................... 86

3.7. Passivation effects on deeply scaled InAnN/GaN HEMTs ................................ 90

3.7.1. Al2O3 deposited by atomic layer deposition (ALD) as passivation layer. ...... 91

3.7.2. Passivation effect on device characteristics .................................................... 92

3.8. Conclusion .......................................................................................................... 98

References ..................................................................................................................... 99

Chapter 4 Planar Nanostrip-Channel InAlN/GaN HEMTs on Si with Improved gm and fT

Linearity .......................................................................................................................... 110

4.1. Introduction ...................................................................................................... 110

4.2. Non-linear gm and fT in GaN HEMTs at high gate bias ................................... 111

4.2.1. Origins of the non-linear performance ......................................................... 112

4.2.2. Current status of high linearity GaN HEMTs ............................................... 115

4.2.2.1. Self-aligned GaN HEMTs......................................................................... 115

4.2.2.2. Fin-like nanowire GaN HEMTs................................................................ 116

4.3. Planar nanostrip-channel InAlN/GaN HEMTs ................................................ 118

4.3.1. Importance of gate fringing capacitance ...................................................... 119

4.3.2. Novel device fabrication techniques............................................................. 120

4.3.2.1. As+ implantation for isolation ................................................................... 120

4.3.2.2. Nanostrip-channel formation .................................................................... 122

x

4.3.2.2.1. HSQ-PMMA self-aligned approach ...................................................... 122

4.3.2.2.2. SiO2-PMMA approach .......................................................................... 129

4.3.3. Device characterizations ............................................................................... 134

4.4. Geometry effect on InAlN/GaN HEMTs ......................................................... 141

4.5. Conclusion ........................................................................................................ 146

References ................................................................................................................... 147

Chapter 5 Planar nanostrip-channel Al2O3/InAlN/GaN MISHEMTs on Si ................... 151

5.1. Introduction ...................................................................................................... 151

5.2. Al2O3 as gate dielectric .................................................................................... 152

5.3. Device fabrication ............................................................................................ 154

5.4. Device characterization and analysis ............................................................... 157

5.5. Conclusion ........................................................................................................ 164

References ................................................................................................................... 164

Chapter 6 Conclusions and recommendations for future work ...................................... 168

6.1. Conclusions ...................................................................................................... 168

6.2. Key contributions of this work ......................................................................... 171

6.3. Recommendations for future work ................................................................... 173

List of Publications ......................................................................................................... 175

xi

List of Figures

Fig. 1.1 Device breakdown voltage versus current gain cutoff frequency (fT) of GaN and

other semiconductor materials…………………………………………………………….3

Fig. 1.2 Comparison of the cut-off frequencies (fT) of GaN HEMTs on Si [41], [43], [46],

[58]-[60] and GaN HEMTs on SiC [57], [61]-[65]……………………………………….8

Fig. 2.1 Crystal structure and polarization field in (a) Ga-face and (b) N-face GaN [1]...25

Fig. 2.2 (a) The schematic of the cross section and (b) energy band diagram of a typical

GaN HEMT………………………………………………………………………………26

Fig. 2.3 Key fabrication processes for conventional AlGaN/GaN HEMTs……………..30

Fig. 2.4 Rs versus annealing temperature………………………………………………...32

Fig. 2.5 Process flow for Bi-layer T-shaped gate formation…………………………….34

Fig. 2.6 SEM images of typical (a) MMA-PMMA resist stack after exposure and (b)

cross section of fabricated T-shaped gate…………………………………………….….35

Fig. 2.7 V-shaped gate by overdose of gate head………………………………………..36

Fig. 2.8 Top view SEM image of the fabricated AlGaN/GaN HEMT with T-shaped

gate………………………………………………………………………………………36

Fig. 2.9 (a) output and (b) transfer characteristics of fabricated conventional AlGaN/GaN

HEMT……………………………………………………………………………………38

Fig. 2.10 System setup for small signal RF measurement……………………………….39

xii

Figure 2-11 (a) device under test, (b) open structure, and (c) short structure……………41

Fig. 2.12 RF characteristics of AlGaN/GaN HEMT with gate length of 250 nm……….42

Fig. 3.1 Reported fT values of AlGaN/GaN HEMTs versus gate length in literatures…..45

Fig. 3.2 Schematic diagram and its small signal equivalent circuit of a GaN HEMT…..49

Fig. 3.3 Delay components of devices with different gate length [21]…………………..52

Fig. 3.4 Small signal equivalent circuits of (a) intrinsic device and (b) device with Rs, Rd

and finite output resistance………………………………………………………………53

Fig. 3.5 Source and drain resistance in a GaN HEMT…………………………………...57

Fig. 3.6 Schematic of an electron-optical column in EBL system and functions of the

main components………………………………………………………………………...59

Fig. 3.7 Alignment marker detection…………………………………………………….60

Fig. 3.8 EBL alignment marker formation……………………………………………….62

Fig. 3.9 Cross section of a Si sample after spin-coated with PMMA at 1200 rpm for 70

seconds and baked at 180 oC for 120 seconds…………………………………………...64

Fig. 3.10 Electron trajectories as function acceleration voltage [28]……………………66

Fig. 3.11 Different dosages assigned for bulk and small features……………………….66

Fig. 3.12 Position of sample in writing chamber [27]…………………………………...67

Fig. 3.13 PMMA after developing……………………………………………………….69

xiii

Fig. 3.14 16 nm isolated line on PMMA with thickness of 370 nm……………………..70

Fig. 3.15 Process flow for gate formation………………………………………………..72

Fig. 3.16 Process flow for channel formation……………………………….…..……….73

Fig. 3.17 SEM image of a short channel (a) before and (b) after annealing……………..74

Fig. 3.18 Energy gap and lattice constant for different III-Nitride alloy materials [40]....77

Fig. 3.19 Simulated 2DEG density as function of barrier thickness for In0.17Al0.83N and

Al0.3Ga0.7N [43]…………………………………………………………………………..78

Fig. 3.20 Schematic diagram and TEM image (gate region) of a 40-nm gate InAlN/GaN

on Si……………………………………………………………………………………...80

Fig. 3.21 (a) output and (b) transfer characteristics of an InAlN/GaN HEMT on Si with a

40-nm gate……………………………………………………………………………….83

Fig. 3.22 Gate leakage current characteristic of an InAlN/GaN HEMT on Si with a 40-nm

gate……………………………………………………………………………………….83

Fig. 3.23 DIBL of InAlN/GaN HEMTs with different gate length……………………...84

Fig. 3.24 (a) de-embeded RF small signal at Vd= 6 V and Vg = - 3.5 V and (b) de-

embedded fT and fmax as a function of Vg of 40-nm gate device………………………….85

Fig. 3.25 (a) comparison of the cut-off frequencies (fT) of GaN HEMTs on Si in this

work with other reported GaN HEMTs on Si [13], [15], [18], [58-60] and GaN HEMTs

on SiC [21-23], [43-47] and (b) shows the Lg dependence of fT• Lg product…………….85

xiv

Fig. 3.26 (a) τT as a function of Wg/Id for the device with 40 nm gate and (b) τT – τp as a

function of Lg…………………………………………………………………………….87

Fig. 3.27 Extracted delay components for the devices with different gate length in this

work……………………………………………………………………………………...89

Fig. 3.28 (a) output and (b) transfer characteristics of a 40-nm gate device before and

after 10 nm Al2O3 passivation……………………………………………………………93

Fig. 3.29 Pulsed-IV measurement for the 40-nm gate device (a) before and (b) after

passivation………………………………………………………………….…………….94

Fig. 3.30 Comparison of maximum fTs before and after passivation……………………95

Fig. 3.31 (a) veff extraction and (b) the extracted delay components after passivation…..97

Fig. 4.1 (a) 𝑔𝑚 and (b) 𝑓𝑇 decrease significantly with the increasing drain current...….112

Fig. 4.2 (a) Cross-section of the conventional GaN HEMT under saturation, (b)

simulation of longitudinal electric field and resistance increase in the source access

region [1] and (c) electric field dependence of electron velocity for different model

[1]……………………………………………………………………………………….114

Fig. 4.3 Device structure of a self-aligned GaN HEMT [15]…………………………..116

Fig. 4.4 Output and transfer characteristics of the Self-aligned GaN HEMT [15]……..117

Fig. 4.5 Device structure of etched nanowire channel GaN HEMT [2]………………..117

xv

Fig. 4.6 Transfer and output characteristic of the reported nanowire channel GaN HEMTs

[2]……………………………………………………………………………………….118

Fig. 4.7 (a) fringing capacitance between gate and 2DEG, (b) fringing capacitance

between gate and additional access region and (c) degraded fT performance [2]………119

Fig. 4.8 Simulated gate capacitance versus gate voltage of the conventional, planar

nanostrip-channel and fin -like nanowire-channel GaN HEMTs. Inset: cross-section of

the gate stack in (a) conventional HEMT (b) fin-like nanowire HEMT and (c) planar

nanostrip HEMT………………………………………………………………………..120

Fig. 4.9 Process flow of HSQ-PMMA self-aligned approach………………………….125

Fig. 4.10 SEM image of HSQ nanostrips………………………………………………126

Fig. 4.11 SEM images of (a) PMMA gate pattern on HSQ nanostrip and (b) fabricated

gate with a comb-like shape…………………………………………………………….127

Fig. 4.12 (a), (b) SEM images of PMMA patterns after ion implantation and (c)

schematic of the cross section of PMMA stack before and after ion implantation…….130

Fig. 4.13 Fabrication flow of the (a) conventional (b) fin -like nanowire and (c) planar

nanostrip GaN HEMTs…………………………………………………………………132

Fig. 4.14 SEM images of (a) etched nanostrip-channel, (b) good alignment between gate

metal and nanostrips and (c) fabricated Planar nanostrip-channel device……………...134

Fig. 4.15 Isolation effect of dry etching and arsenic ion implantation…………………135

xvi

Fig. 4.16 DC characteristics of planar nanostrip, fin -like nanowire and conventional GaN

HEMTs………………………………………………………………………………….136

Fig. 4.17 The source resistance (Rs) of the conventional, fin-like nanowire channel and

planar nanostrip channel GaN HEMTs, Rs0 is the source resistance when Id= 0

mA/mm…………………………………………………………………………………138

Fig. 4.18 Gate leakages of conventional, fin-like nanowire and planar-nanostrip

HEMTs………………………………………………………………………………….139

Fig. 4.19 Subthreshold swing characteristics of conventional and Planar nanostrip-

channel device…………………………………………………………………………..140

Fig. 4.20 fT as a function of Vg after pad capacitance de-embedded of conventional, fin-

like nanowire and planar-nanostrip HEMTs……………………………………………141

Fig. 4.21 Variation of nanostrip width in the device layout……………………………142

Fig. 4.22 Transfer characteristics of the Planar nanostrip-channel device with different

nanostrip width………………………………………………………………………….143

Fig. 4.23 Coupling between additional gate and channel of device with different nanostrip

width……………………………………………………………………………………144

Fig. 4.24 (a) subthreshold characteristics and (b) DIBL of devices with different

Wnanostrip…………………………………………………………...…………………….144

Fig. 4.25 De-embedded fT for the devices with different Wnanostrip……………………..145

xvii

Fig. 4.26 gm as function of gate bias for the device with different gate-to-source

distance…………………………………………………………………………………146

Fig. 5.1 A typical band diagram of a GaN MISHEMT………………………………...153

Fig. 5.2 Schematic diagram of InAlN/GaN on Si………………………………………155

Fig. 5.3 Fabrication flow of the planar nanostrip GaN MISHEMTs…………………...158

Fig. 5.4 The gate leakage currents of planar-nanostrip channel HEMT and

MISHEMT………………………………………………………………………….…..159

Fig. 5.5 (a) output and (b) transfer characteristics of an InAlN/GaN HEMT with a 40-nm

gate……………………………………………………………………………………...160

Fig. 5.6 fT as a function of Vg after pad capacitance de-embedded……………………..161

Fig. 5.7 (a) ideal amplifier without non-linearity and (b) actual amplifier [25]………..163

Fig. 5.8 OIP3 extraction of a conventional GaN HEMT……………………………….163

Fig. 5.9 Intermodulation distortion (IMD) characteristics of conventional HEMT, Planar

nanostrip-channel HEMT and Planar nanostrip-channel MISHEMT………………….164

xviii

List of Tables

Table 1.1 Key intrinsic electronic properties of GaN and other semiconductor

materials…………………………………………………………………………………...2

Table 1.2 Properties of commonly used substrates for GaN growth……………………...6

Table 4.1 (a) measured current in the test structure under 5 V before and after ion

implantation with ion energy of 50 keV and dosage of 2x1015 cm-2 and (b) 40 KeV and

dosage of 3x1015 cm-2…………………………………………………………………..122

1

Chapter 1 Introduction

1.1. Overview of GaN based high-electron-mobility

transistors (HEMTs) for RF application

In the last few decades, GaN based semiconductor technology has witnessed

significant advancement. The unique properties of GaN based materials have stimulated

the applications in many fields such as optoelectronics [1-5] microelectromechanical

systems (MEMS) [6-11] and electronics [12-17]. Among all these applications,

AlGaN/GaN high electron mobility transistors (HEMTs) are especially attractive due to

their excellent capabilities in high power [12], high frequency [13, 14] and high

temperature operations [17].

Table 1.1 compare the key intrinsic electronic propertied of GaN to other major

semiconductor materials. It can be concluded that GaN has several major advantages over

Si, GaAs and InP. Benefiting from its wider band-gap (Eg), GaN has an up to ten time

higher critical electrical field (Ec) than Si, GaAs and InP. The high Ec of GaN leads to

much higher breakdown voltage of GaN HEMTs compared to other semiconductor

device thus making GaN very suitable for high voltage and high power applications. In

addition, the high breakdown voltage helps to improve the circuit robustness based on

GaN transistors. The outstanding electron mobility and saturation drift velocity together

with the high 2DEG concentration enable these devices to operate at very high

frequencies with high drain current, which is important for high power RF applications.

As a wide band-gap material, the intrinsic carrier generation rate ni is very much lower

2

than Si, GaAs or InP, which makes GaN based transistors able to operate at high voltage

and meanwhile keeping the leakage current at a low level [5]. Moreover, the high thermal

conductivity allows GaN based device to work at extreme environments.

Table 1.1 Key intrinsic electronic properties of GaN and other semiconductor materials

Material Si 4H-SiC GaN GaAs InP

Eg(eV) 1.1 3.26 3.4 1.4 1.34

Ec(MV/cm) 0.3 2.0 3.3 0.4 0.5

ni (/cm3) 1.5×1010 8.2×10-9 1.9×10-10 2.1×106 1.3×107

εr 11.8 10 9.0 12.8 10

μn(cm2∙V-1∙s-1) 1350 720 900 8500 5400

νsat(107 cm/s) 1.0 2.0 2.5 2.0 0.9

κ(W∙cm-1∙K-1) 1.5 4.5 1.3 0.5 0.68

Eg: band gap energy, Ec: breakdown electric field, εr: relative dielectric constant, ni:

intrinsic carrier generation rate, μn: electron mobility, νsat: saturated drift velocity of

electron, κ: thermal conductivity.

As shown in Table 1.1, many properties of SiC are similar to GaN. However, there are

some critical challenges such as difficulties in forming heterostructure and developing

fabrication techniques ultimately limit its applications. On the other hand, GaN is able to

form heterosructure with other GaN based material such as AlGaN and thus form a

HEMT structure. Moreover, benefiting from the existence of high density 2DEG (for

AlGaN/GaN hetrostructure, ni ~ 1× 1013

/cm3

; μn~ 1500 cm2∙V-1∙s-1) induced by the high

3

polarization effect near the heterojunction interface, the fabrication process of

AlGaN/GaN HEMTs is simple since there is no need of additional doping process.

Due to the advantages mentioned above, AlGaN/GaN HEMTs are commercially very

attractive in RF high power amplifications in 5G communication systems and imaging

applications, such as vehicle to vehicle communication, automobile radar in auto-driving

system, internet-of-things, HDTV (High Definition Tele-Vision), IoTs (Internet of

Things), and imaging systems etc.

As for RF power amplifiers, the most important parameters are maximum output power

and operating frequency. Since these two parameters are significantly affected by

breakdown voltage, mobility and electron saturation velocity as mentioned above,

AlGaN/GaN HEMT is an excellent candidate to be used as power amplifiers with the

potential to obtain outstanding performance as shown in Figure1.1 [18].

4

Fig.1.1 Device breakdown voltage versus current gain cutoff frequency (fT) of GaN and

other semiconductor materials [18]

The AlGaN/GaN HEMTs’ microwave characteristics were firstly reported in 1994 [7].

Since then, a lot of efforts have been made for the improvement of their performance,

particularly on the large-sginal power and small-signal frequency performance.

Two of the most important large-signal power figure-of-merits of AlGaN/GaN HEMTs

are the maximum output power (Pout) and power-added-efficiency (PAE). The first large-

signal RF characteristics for an AlGaN/GaN HEMT was reported in 1996 [19]. The

device had a gate length of 1µm. At 2 GHz, it showed a maximum Pout of 1.1 W/mm and

PAE of 18.6 %. Since then, both the high power performance and operation frequency of

AlGaN/GaN HEMTs have been improved dramatically. In 1997, Wu et al. demonstrated

a device with Pout of 3.3 W/mm and PAE of 18.2 % at 18 GHz [20]. In the same year,

Moon et al. reported a 0.15 µm-gate device with Pout of 6.6 W/mm and PAE of 35 % at

20 GHz [21]. Benefiting from the use of a field-plate technology [22], Chini et al. pushed

the devices’ Pout to 12 W/mm and PAE to 58 % at 4 GHz in 2004 [23]. In the same year,

Wu et al. improved Pout significantly to 41.4 W/mm with PAE of 60 % at 4 GHz [24]. In

2005, Palacios et al. reported a device with Pout of 10.5 W/mm and PAE of 33 % at 40

GHz [25]. In 2007, Wu et al. improved Pout to 13.7 W/mm and PAE to 40 % at 30 GHz

[26]. Moreover, many promising high power results of AlGaN/GaN HEMTs in high

frequency range have also been reported [27, 28].

For small-signal RF characterizations, by measuring the device S-parameters, one can

extract the maximum operation frequency of an AlGaN/GaN HEMT. Generally, the most

important figure-of-merits (FOMs) in the small-signal performance are current gain

5

cutoff frequency (fT) and power gain cutoff frequency (fmax). They are the most straight

forward parameters to evaluate the speed performance of a device. The first small-signal

microwave characteristics of AlGaN/GaN HEMT were reported by Khan et al. on a

device with 0.25 µm gate in 1994. The device showed a fT of 11 GHz and fmax of 35 GHz

[29]. Since then, both fT and fmax of AlGaN/GaN HEMTs have increased significantly.

The maximum fT and fmax have been increased to 36.1 GHz and 70.8 GHz, respectively

by Khan et al. in 1996 in a 0.25 µm-gate device [30]. Wu et al. reported a 0.2 µm-gate

device with fT of 50 GHz and fmax of 92 in 1997 [31]. In 2000, by shrinking the gate

length to 0.15 µm, Micovic et al. improved the fT to 110 GHz and fmax to 140 [32]. Kumar

et al. demonstrated a 0.12 μm-gate device with fT of 121 GHz and fmax of 162 GHz [33].

A 90 nm-gate device with fT of 163 GHz and fmax of 185 GHz was reported by Palacios et

al. in 2005 [34]. By applying an InGaN back barrier structure in a 100 nm-gate device in

2006, fmax of 230 GHz was achieved by Palacios et al. [35]. In the same year,

Higashiwaki et al. pushed the fT to 181 GHz by scaling the gate length down to 30 nm

[36]. A device with 60 nm gate AlGaN/GaN HEMT and a thinner top barrier was

demonstrated by Higashiwaki et al in 2008. fT of 190 GHz and fmax of 251 GHz were

obtained in this device [37]. Finally, in 2010, a new record performance was reported by

Chung et al.. The device in this work exhibited high fT of 225 GHz and fmax of 300 GHz,

respectively [38], [39].

1.2. Issues in GaN HEMTs for RF applications

As discussed in the last section, great improvements have been made on the

performance of GaN HEMTs for RF applications. However, despite all these significant

improvements, there are still some critical issues for GaN HEMTs. On key issue is that

6

the performance of GaN HEMTs reported on low-cost Si substrate still lags behind that

on SiC substrate. The other one is that the poor linearity performance of GaN HEMTs

especially for sub-100 nm gate limits its application at high gate bias condition.

1.2.1. Lack of High Frequency GaN HEMTs on Si

substrate

Resulting from the lack of large size bulk GaN substrate as well as the high cost and the

difficulties of synthesis, GaN based heterostructures are usually grown on non-native

substrates such as sapphire (Al2O3), SiC and Si (111). The properties of commonly used

substrates are listed in Table 1- 2.

Table 1.2 Properties of commonly used substrates for GaN growth

Material Al2O3 (100) 6H-SiC GaN (0001) Si (111)

a (Å) 4.758 3.081 3.189 3.846

a mismatch −33% 3.5% 0 −17%

α (10-6K-1) 7.3 4.5 5.6 2.6

α mismatch −23% 24% 0 116%

𝜿 (W/cm·K) 0.5 4.5 1.3 1.5

Max. D (mm) 200 150 50 300

Cost Medium Very high Extremely high Low

a: Lattice constant; α: Thermal expansion coefficient; κ : Thermal conductivity; D:

substrate diameter.

7

As shown in Table 1.2, SiC has the advantages of smaller lattice mismatch to GaN

eplilayers and has very high resistivity and thermal conductivity. Thus, GaN HEMTs

grown on SiC can achieve higher RF performance than those grown on Si. However,

GaN HEMT on SiC is not cost-effective and is only available in smaller sizes (≤ 6 inch)

which make it less attractive to be adopted commercially.

To reduce the cost of GaN HEMTs, Si substrates have attracted increasing interest in

recent years, not only in power electronics applications but also in RF applications.

Significant efforts have been made on improving the epitaxial quality of GaN on Si

substrates as well as the device fabrication technology. As a result, the performance of

conventional AlGaN/GaN HEMTs on Si has improved significantly [40]-[46]. However,

the high frequency performance of GaN HEMTs on Si still lags behind their counterparts

on SiC. Large lattice mismatch (17%, versus 3.6% between GaN and SiC) and thermal

expansion coefficient difference between GaN and Si (111) substrate lead to higher

density of dislocations in the epitaxial GaN materials [47, 48]. The low resistance Si

substrate, nitride/Si interface and GaN buffer also bring significant RF loss for the

devices [49]. Besides, novel barrier materials such as InAlN, AlN, InAlGaN and AlGaN

with high al concentration [36, 37, 50-56] with thin thickness have already been applied

on the devices fabricated on SiC substrate. Combined with deeply scaled gate length,

these devices showed dramatically improved maximum operation speed [57]. In contrast,

there is very limited study on deep sub 100-nm-gate GaN HEMTs on Si with novel thin

InAlN barrier layer. As a result, most of high frequency results, especially those above fT

of 200 GHz, were reported from devices grown on SiC substrates. The best reported GaN

HEMT on Si only exhibited a fT of 176 GHz with for a gate length of 80 nm [58]. As

8

0 50 100 150 200 2500

100

200

300

400

500

GaN HEMT on Si

GaN HEMT on SiC

f T

(G

Hz)

Lg (nm)

shown in Fig. 1.2, the fT values of GaN HEMTs on Si substrate reported in literatures are

much lower than that of on SiC.

Fig. 1.2 Comparison of the cut-off frequencies (fT) of GaN HEMTs on Si [41], [43], [46],

[58]-[60] and GaN HEMTs on SiC [57], [61]-[65]

1.2.2. Poor Linearity performance of deeply scaled

GaN HEMTs at high gate bias

Beside operation frequency and output power, linearity performance needs to be

particularly considered in the GaN HEMT devices. The next generation communication

systems will widely adopt the techniques of CA (carrier and MIMO (multiple input

multiple output), and these techniques will result in greater signal intermodulation and

communication channel interference. High linearity amplifiers and switches are needed in

these systems. However, the linearity of GaN transistors ultimately limits the power

density and efficiency of these devices in many applications, as the operating point of the

device typically needs to be backed-off to meet the linearity specifications. In fact, as the

9

operating frequency increases into the mm-wave range by shrinking the gate length, the

linearity is expected to degrade even further [66, 67]. Circuit designers are putting efforts

to add more functional sub-circuits such as DPD (Digital Pre-Distortion) to solve the

linearity issue. However, this will definitely increase the system complexity, chip size,

and design cost, and degrades the system robustness. Several theories have been brought

forward to explain the non-linearity in GaN HEMTs, such as alloy and interface

scattering [68], enhanced phonon scattering [69] and the increased access resistance at

high channel current [66, 70, 71]. Techniques like self-align GaN HEMT [72] and etched

nanowire channel HEMT [67] have been studied to suppress the nonlinear effect.

However, these techniques still have their own limitations. Low breakdown voltage has

been observed for the self-aligned HEMT due to the small gate-to-source and gate-to

drain access regions. The etched nanowire channel introduces too much parasitic

capacitance and therefore degrades the device performance. Further improvement on

linearity performance of GaN HEMTs is hence needed.

1.3. Project goal and thesis outline

This thesis mainly focuses on the two key issues in GaN HEMTs for RF application as

discussed in the last section. First, in order to obtain high operation frequency in GaN

HEMTs on Si substrate, delay components of the devices have been analyzed in detail.

The limitations of device speed have been clarified. Device fabrication technologies have

been developed for deeply scaled InAlN/GaN HEMTs on Si and pushed the devices’

operation frequency to higher level. Then, the origin of the poor linearity performance of

GaN HEMTs at high gate bias (or drain current) is studied. Novel technologies and

device design have been developed to obtain high linearity in GaN HEMTs.

10

In chapter 2, the fundamentals of conventional AlGaN/GaN HEMT technology are

briefly presented. The device physics including heterostructures formation and device

operation mechanism are described. Typical fabrication process of a conventional

AlGaN/GaN with T-shaped gate and its DC/RF characterizations are explained.

In chapter 3, the factors that limit the devices’ high frequency performance are

investigated. A thin InAlN top barrier is applied instead of conventional AlGaN top

barrier in order to minimize the impact of the decreased gate length-to-barrier thickness

ratio and thereby degradation of the gate modulation efficiency. Sub-100 nm gate was

developed using electron beam lithography (EBL) technology to minimize gate induced

intrinsic delay. Parasitic charging delay was minimized benefiting from the short source-

to-drain distance down to 300 nm and low contact resistance Rc of 0.2 Ω.mm. Maximum

fT of 250 GHz was obtained in a 40-nm gate device which is the highest value ever

reported for GaN HEMTs on Si substrate previously. Surface passivation effects on DC

and RF performance was also investigated.

In chapter 4, the mechanism of the poor linearity performance of the gm and fT at high

gate bias are clarified. A novel planar nanostrip-channel GaN HEMTs structure using ion

implantation technology is implemented to improve the linearity performance and

maintain a high fT by not introducing too much gate parasitic capacitance. The fabrication

process was described in details including Arsenic ion implantation for isolation

application, nanostrip-channel formation using different approaches. Moreover, the

planar nanostrip-channel device also showed much improved maximum drain current

Idmax up to 2.6 A/mm, which is close to the theoretical prediction. Also, studies on the

device geometries including gate length, line-to-space ratio of the nanostrip-channel and

11

gate-to-source distance are carried out. These results do not only identify the origin of the

non-linear performance in GaN HEMTs, but also provide the direction on how to

improve the design of RF GaN HEMTs for high linearity application.

In chapter 5, A Planar nanostrip-channel Al2O3/InAlN/GaN MISHEMTs on Si are

demonstrated. A thin layer of oxide was introduced between the metal gate and the thin

InAlN barrier to form a metal-insulator-semiconductor (MIS) gate in the Planar

nanostrip-channel GaN HEMT. As a result the gate leakage current was reduced which

in turn increase the gate voltage swing and drain current swings. The results show that the

Planar nanostrip-channel Al2O3/InAlN/GaN MISHEMTs are able to work at a positive

gate bias voltage up to 4 V and at the same time improves the linearity performance.

Two-tone intermodulation characterizations are discussed for conventional HEMT,

Planar nanostrip-channel HEMT and MISHEMT. The lower IM3-to-carrier ratio (–

C/IM3) and larger third order intercept OIP3 values of the Planar nanostrip-channel

MISHEMT clearly indicate that the linearity of GaN HEMT was improved by the planar

nanostrip-channel structure as well as the insertion of 6-nm Al2O3 gate insulator.

Finally, the main results of this thesis are summarized in chapter 6. In addition, the

recommendations for future improvement of GaN HEMTs for RF applications are also

presented.

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Chapter 2 Fundamentals of GaN HEMTs

In this chapter, the fundamentals of conventional AlGaN/GaN HEMT technology are

briefly introduced. The device physics including heterostructures formation and device

operation mechanism will be described. Typical fabrication process of a conventional

AlGaN/GaN with T-shaped gate and its DC/RF characterizations will be briefly

explained.

2.1. Physics and device design in conventional

AlGaN/GaN HEMTs

The most general GaN crystalline structure is wurtzite. In such a crystal unit cell,

Gallium (Ga) and Nitrogen (N) atoms are bounded ionically. Due to the electron affinity

difference between Ga and N atoms, the distribution of valence electrons in the bonding

is strongly asymmetric [1]. Unlike other semiconductors such as GaAs and InP with

zincblende crystal structure, the wurtzite structure in GaN is not symmetrical, and thus a

strong net polarization field is induced. Typically, based on the growth direction, there

are two types of GaN material namely Ga-face and N-face. The directions of the

polarization field in the two types of GaN are opposite as shown in Fig. 2.1 [1]. In this

work, Ga-face GaN material was used for all the devices. This polarization field is called

spontaneous polarization because it is an intrinsic property of GaN material and induced

by the crystalline structure and elemental composition.

25

(a) (b)

Fig. 2.1 Crystal structure and polarization field in (a) Ga-face and (b) N-face GaN [1].

In addition to the spontaneous polarization, another polarization namely piezoelectric

polarization exists in lattice mismatched GaN based heterostructures such as AlGaN and

AlN. This polarization component is induced by the strain between two different

materials. If the thickness of AlGaN or AlN barrier is below their critical thickness, the

strain cannot be eliminated and gives rise to piezoelectric polarization [2]. Together with

spontaneous polarization, these two polarization components determine the basic electric

properties of GaN based heterostructures and enable the possibility of a high electron

mobility transistor (HEMT).

Fig. 2.2 shows a typical structure of the AlGaN/GaN HEMT and its band diagram used

in this work. It consists of a undoped GaN cap layer, AlGaN top barrier layer, AlN spacer

layer, GaN channel/buffer layer and transition/seeding layer. Benefitting from the

26

bandgap difference between AlGaN barrier (larger bandgap) and GaN channel (smaller

bandgap) and high polarization field, a quasi-triangular potential well is formed several

nanometers under the interface of the heterostructure and a high density two dimensional

electron gas (2DEG) is confined in this well. The gate electrode controls the channel by

modulating the concentration of 2DEG through the gate voltage. The functions of each

layer in the GaN HEMT structure are listed as follow:

Fig. 2.2 (a) The schematic of the cross section and (b) energy band diagram of a typical

GaN HEMT

a. Undoped GaN cap layer

A thin layer of in-situ GaN is usually grown on top of the barrier layer. Generally, the

cap layer can be either n+ doped or undoped. The undoped GaN cap layer used in this

work has the advantage that the Schottky barrier height is large (> 1.0 𝑒𝑉) and thus the

gate metal can be directly deposited on the GaN cap layer. In this case, the device

fabrication process can be simplified and better device performance uniformity can also

be achieved.

27

b. AlGaN barrier layer

Barrier layer mainly plays two roles in GaN HEMT structure. One is to generate high

density electrons in the channel and the other is to isolate the gate electrode from the

channel. In order to have high electron concentration, barrier layer need to have a larger

bandgap than GaN channel. Conventionally, AlxGaN1-x is used for top barrier. Aluminum

concentration is expected to be higher in order to have a larger bandgap difference ∆Ec

compared with GaN and thus generates higher 2DEG concentration and prevents hot

electrons from injecting into the barrier. However, Aluminum concentration is usually

kept lower than 30%. This is because if the Al composition is too high, it will introduce

high strain between top barrier and channel due to enlarged lattice mismatch [3].

Furthermore, higher Al composition will potentially impact the long-term reliability as

reported in [4].

c. AlN spacer layer.

The high bandgap undoped spacer layer can be grown in between the barrier layer and

the channel layer to increase the 2DEG density by further increasing bandgap difference.

At the same time, the spacer layer can increase the electron mobility by reducing the

remote coulomb scattering of the electrons in the channel. A 10% increase in 2DEG

density and 50% in electron mobility was reported in [5].

d. Undoped GaN channel layer

As discussed above, a conductive channel is formed several nanometers under the

interface between the barrier and buffer layer. As the GaN buffer layer has a lower

bandgap compared with AlGaN barrier, a quasi-triangular potential well is formed

28

between the two types of materials. Due to the large spontaneous and piezoelectric

polarization difference between the AlGaN and GaN, a high density 2DEG is formed and

confined in the quasi-triangular potential well. As a result, there is no need of additional

doping process to generate electrons in the channel.

e. GaN buffer layer

Insulating buffer layer is necessary for GaN HEMTs to reduce the buffer leakage

current and the parasitic capacitance between electrodes and conductive buffer. Generally,

both un-doped and Fe or C doped GaN can be used for this purpose.

f. 1 µm GaN and transition/seeding layer

Typically, GaN epi layers are grown on a foreign substrate with different material

because it is still hard to achieve high quality GaN substrate with large wafer size. The

lattice mismatch between the substrate material and GaN is relatively large, for example,

the corresponding mismatch between GaN and SiC/sapphire/Si are 3.6%/ 13.8% /17%

respectively. The purpose of the transition/seeding layer is to accommodate the strain and

TEC mismatch between substrate and GaN buffer [6]. Thus, the design and growth of this

layer is very important to realizing high quality GaN epi layers.

g. Substrate

Generally, there are three types of substrate materials for GaN growth which are SiC,

Sapphire and Si. The properties of these materials have been discussed in the first chapter

of this thesis. In this work, all the devices are fabricated using GaN-on-Si for low-cost

purpose.

29

2.2. Key fabrication process for conventional GaN

HEMTs

The fabrication process of conventional AlGaN/GaN HEMT can be roughly divided

into four steps, which are: mesa isolation, ohmic contact formation, gate formation and

surface passivation. Fig. 2.3 shows the process flow.

Mesa isolation by Cl2/BCl3

plasma dry etching.

Ohmic contact formation by

Ti/Al/Ni/Au metallization and

high temperature annealing.

Gate formation by EBL and

Ni/Au metallization.

Si3N4 passivation.

30

Fig. 2.3 Key fabrication processes for conventional AlGaN/GaN HEMTs

2.2.1. Mesa Isolation

The fabrication of the device starts from device isolation. This step is to prevent short

circuit or current leakage between adjacent devices. The device performance is highly

dependent on the quality of mesa isolation. If the leakage current is high, the device will

not be able to pinch-off. For effective mesa isolation, the leakage current should be less

than 10−6 A/mm at operation biases.

Usually, this isolation can be achieved by wet etching and dry etching. Since wet

etching is difficult to use for etching in GaN based material, dry etching processes like

Reactive-Ion-Etching (RIE) or Inductive-coupled-Plasma (ICP) are more commonly used.

The mesa pattern is realized by photolithography and followed by Cl2/BCl3 plasma dry

etch.

The mesa isolation process starts by cleaning the wafer with acetone and IPA by

ultrasonic. The wafer was first coated with a 1.4 μm AZ5214 photoresist using a spin

coater at 4000 rpm for 30 secs. Soft bake of the wafer at 105 ⁰C for 2 minutes was

adopted to evaporate the solvent in the photoresist. The sample was then patterned using

UV-light (320nm) exposure and developed in CD 26 developer for 30 secs. 𝑂2 plasma

treatment was used to remove the residue of photoresist. The dry etching was carried out

with Cl2/BCl3 of 20/40 sccm at RF power of 100w for 100 s to remove the top 100-

120nm GaN and AlGaN layers. The measured leakage current for a 10 µm gap is

typically lower than 10−7A/mm at 20 V, which indicates that the mesa isolation and the

buffer quality is acceptable.

31

2.2.2. Ohmic Contact Formation

To achieve high drain current density and high maximum operation frequency, low

source and drain contact resistance are necessary. The contact resistance is influenced by

many factors such as wafer structure, growth quality, process technique, metal deposited

and annealing temperature etc. To form a low resistance ohmic contact, the metal to be

deposited needs to fulfill several characteristics such as low work function and resistivity

and highly thermal conductive. Ti/Al/Ni/Au multilayer metal stack is commonly used as

the metal scheme to form the ohmic contact. A high temperature (typically 800 ⁰C)

annealing is required after the metal deposition. During the annealing, Ti and Al will

react with the N atoms of the under layer semiconductor materials including GaN and

AlGaN barrier and form TiAlN [7]. Thus, lots of N vacancies were generated in the

barrier and these vacancies are working as n-dopants, which pull down the conduction

band of the nitrides and help to form the ohmic contact. Au is used to prevent Ti/Al from

being oxidized and improve both the electrical and thermal conductivity. Ni is inserted as

a blocking layer between Ti/Al and Au to prevent the inter-diffusion of Ti/ Al and Au.

For the ohmic contact formation, the wafer was treated with 𝐻2𝑆𝑂4/𝐻2𝑂2 3:1 (Piranha)

to remove the surface contaminant. The ohmic contact patterns were defined using the

image reversal process of AZ5214. After coating with 1.4μm photoresist, the wafer was

soft baked at 105⁰C for 2 minutes and followed by the first exposure with contact mask

aligner. Then hard bake was carried out at 120⁰C for 2 minutes followed by flood

exposure without any mask. CD26 developer was used for development. This image

reversal photolithography process is able to give minimum 1μm linewidth with good

undercut, which is useful for the metal lift-off process. After 𝑂2 plasma descum, a BOE

32

(buffered oxide etchant) treatment was applied to the wafer to remove the native oxide.

This is important to form low resistance ohmic contact because the native oxide can form

a barrier between the deposited metal and the AlGaN barrier, thus deteriorate the ohmic

contact between the Ti/Al/Ni/Au alloys and the semiconductor material. A four-layer

Ti/Al/Ni/Au 20/120/40/50 nm was deposited using an electron beam evaporator system.

Lift-off was used to remove the unwanted metal. The post metallization annealing is

needed to form the ohmic contact. The ohmic contact resistance (Rc) can be measured

with the Transmission Line Model (TLM) method. The optimization of the annealing

temperature was carried out in this work. Fig. 2.4 shows that the lowest contact resistance

can be achieved at 775⁰C. For the wafer in this work, the contact resistance 𝑅𝑐 =

0.32~0.36 Ω-mm has been measured.

Fig. 2.4 Rs versus annealing temperature

After the ohmic contact formation, a two layer Ti/Au 50/300 nm was deposited for

interconnect and pads.

33

2.2.3. Gate Formation

Good Schottky gate formation is one of the keys to realize high device performance.

To minimize the gate leakage current, the gate metal should have a high work function

and with a high Schottky barrier height. Ni/Au double layer is usually used to form the

metal gate. Au deposited on top of Ni is used to reduce the gate metal resistance.

The speed of the device is directly dependent on the gate length (Lg) as the time that

the electron travels across the channel is proportional to Lg. Thus, a short gate length (Lg)

is crucial to achieve high operation speed in GaN HEMT. However, the gate resistance

(Rs) increases proportional to the Lg for a rectangular gate. High Rs will degrade large

signal performance of GaN HEMTs. To solve this problem, a T-shaped gate (also known

as mushroom-shaped) with a short gate foot length and larger gate head length can be

applied to increase the cross section area of the gate and thus can achieve short gate

length as well as low gate resistance. In this chapter, a T-shaped gate was formed with

Bi-layer MMA-PMMA process using an Electron Beam Lithography (EBL) system (EBL

system will be discussed in details in chapter 3). The gate formation process flow is listed

in Fig. 2.5.

After mesa isolation and ohmic

contact formation.

34

Fig. 2.5 Process flow for Bi-layer T-shaped gate formation

Electron beam exposure

Gate metallization and lift-off

To spin coat PMMA

To spin coat MMA

35

Fig. 2.6 SEM images of typical (a) MMA-PMMA resist stack after exposure and (b)

cross section of fabricated T-shaped gate

For the gate formation process, the wafer was first spin coated with bi-layer PMMA

(poly methyl methacrylate) and MMA (methyl methacrylate) resist stack. Vistech 5200

EBL system was used to write the gate pattern directly on the resist stack. The sensitivity

to electron beam of MMA on top is higher than that of PMMA underneath. So, the

dosage use for gate head writing is lower than that for gate foot. During gate head writing,

by carefully control the dosage, the PMMA layer will not be exposed. After the writing

of gate head, a higher dosage was used for gate foot writing. After electron beam

exposure, a Methyl Iso-Butyl Ketone (MIBK): Isopropanol (IPA) =1:3 solution at room

temperature was used to develop the sample for 90 secs. A T-shaped resist stack was

formed as shown in Fig. 2.6 (a). After gate metallization and lift-off, T-shaped gate was

fabricated as shown in Fig 2.6 (b). It is worth noting that the dosage for gate head writing

is crucial to obtain an accurate profile for the T-shaped gate. For example, if the dosage

used for gate head writing is too high, the PMMA underneath will also be exposed and

36

thus change the gate foot profile. Fig. 2.7 presents an example for the over dose of gate

head.

Fig. 2.7 V-shaped gate by overdose of gate head

Fig.2.8 represents the top view SEM image of the fabricated conventional AlGaN/GaN

HEMT with a T-shaped gate. In this device, the gate foot length Lg was 250 nm while the

gate head length was 700 nm. 50/300 nm Ni/Au metal stack was used for the gate metal.

The source-to-gate distance Lgs was 750 nm and the drain-to-gate distance was 3 µm. The

channel width of the device was 50 µm x 2.

GATE SOURCE SOURCE

DRAIN

37

Fig. 2.8 Top view SEM image of the fabricated AlGaN/GaN HEMT with T-shaped gate

2.2.4. Surface Passivation

As the final step, a layer of dielectric material is deposited on top of the device as

passivation layer to reduce the surface states. Usually, on the surface of source and drain

access regions, there are a large number of surface states which can degrade both the DC

and RF performance of GaN HEMTs. These surface states may come from the damage

induced during processing, or the dangling bonds of the atoms on the surface of

semiconductor material, or even surface contaminations.