In this last lecture of the course, I will be looking at how adder circuits … 15... ·...

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Transcript of In this last lecture of the course, I will be looking at how adder circuits … 15... ·...

Page 1: In this last lecture of the course, I will be looking at how adder circuits … 15... · 2017-11-28 · 4 To build a 4 -bit adder from 1-bit full adders, we can connect four of these

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Page 2: In this last lecture of the course, I will be looking at how adder circuits … 15... · 2017-11-28 · 4 To build a 4 -bit adder from 1-bit full adders, we can connect four of these

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Inthislastlectureofthecourse,Iwillbelookingathowaddercircuitswork.Inparticular,IwillbeexaminingtheimplementationofaddersontheCycloneVFPGAs.Furthermore,sinceCycloneValsocontainalargenumberofmultipliersinsideDSPblocks,Iwillbriefexplainhowthesecouldbeinstantiated.

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Thebuildingblockforann-bitadderisaone-bitfulladder.ThisisessentiallyacomponentthataddsTHREEone-bitvaluestogether:PQandCI.Itproducestwooutputs:SumS,andCarryC.

Notethatallthreeinputsaresymmetrical– theycanbeswappedwithoutanychangeintheoutputs.

Further,ifyouinvertallinputs,theoutputsarealsoallinverted.Thisisknownas“self-dual”.

TheBooleanequationforCandSareshownhere.Thisissomethingthathasbeencoveredfromthefirstyear.

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Tobuilda4-bitadderfrom1-bitfulladders,wecanconnectfouroftheseseriallyasshownhere.Itisimportanttoappreciatethatthis4-bitadderworksforbothsignedandunsignedinput,providedthatsignednumbersareusing2’scomplementrepresentation.Inotherwords,ifyouinterpretinputasunsigned4-bitnumbers,thentheadderproducesunsigned5-bitoutput(includingthecarryoutsignal).

Ifyouinterprettheinputas2’scomplementsignednumbers,thentheoutputiscorrectasa4-bitSIGNEDoutput.(Inthiscase,youcannotuseC3asthe5thbit).

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Ifyouaddtwo4-bitnumberstogether,theinputsareunsigned,thentheoutputwillbeintherangeof0to30.However,ifyouwanttousetheadderforsignednumberaddition,theinputrangeis-8to+7,thereforetheoutputrangeis-16to+14.Inbothcases,wewouldneed5-bitaddertoavoidanyoverflow.

Fortheunsignedcase,youcouldusethecarryoutasthe5th outputbit.Fornow,letususeonlythesumoutput,andweneeda5-bitadder.

Forsignedaddition,wecannotusethecarryoutasthe5th bit.WeMUSTusea5-bitadder.So,weneedexpandtheinputnumbersfrom4-btito5-bit.WhatdowedowiththeMSB?

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Forunsignednumbers,examplinga4-bitnumbertoan8-bitnumbersimplyrequiresadding4extra‘0’ totheMSBpartofthenumber.

Forsignednumbers,weneedtoextendtotheleftfoursignbitsinordertopreservethesignedofthenumberandmaintainthecorrectvalue.Thisisknownas“signextension”.

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Toshrinkabinarynumbertosmallernumberofbits,itiseasyforunsignednumbers– simplydeleteallleading‘0’sforMSB.Thevalueoftheunsignednumberwillnotchange.

Forsignednumbers,iftheMSBis0,youcandeleteall‘0’ fromMSBdownexceptthelast‘0’.IftheMSBis‘1’,youcandeleteall‘1’sfromMSBdownexceptthelast‘1’.Inthatway,youpreservethecorrectsignofthenumber.

YoucanalsoshrinkthenumberofbitsbyremovingunwantedLSBsthroughtruncation.Alternativelyyoucanperformrounding.

Truncationiseasy– toreducean8-bitnumberto4-bit,justremovetheleastsignificant4-bit.

Roundingisharder,andtherearevariousmethodofroundingthatcanbeused.Thesimplestmethodinthecaseof8-bitroundedto4-bitsistoadd8’b00001000tothenumber,thantruncatethebottom4-bit.Basically,youaddhalfoftheLSBofthefinalnumbertotheoriginalnumberbeforechoppingoffthelowerbits.Thisisthesameashowweroundwithdecimalnumbers.

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Inordertoavoidoverflowwhenaddingtwo4-bitnumberstogether,weneedtousea5-bitadder.Forunsignedadd,wezeroextendtheinputsto5-bitandthenusea5-bitaddertoproduceS4:0asshwonhere.

Ofcourse,wecouldhaveusedthe4-bitadderandusethecarryoutC3asS4.

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Tobuilda4-bitsignedadderWITHOUToverflow,weneedtofirstextendtheinputto5bitswithsignextensionsashownhere.Thenusea5-bitaddercircuittoproducea5-bitsignedresult.

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Letusconsiderthepropagationdelaythrougha4-bitadder.TheworstcasepathisfromP0orQ0input,thenpassthroughthecarrychaintotheMSBsumoutput.

AssumingthegatedelaytoCis2andtoSis3,thentheworstcasedelayis9.

ThisiscalledaripplecarryadderbecausethecarrysignalhastopropagateallthewayfromtheLSBstagetotheMSBstage.

Anexamplescenariofortheworstcasepropagationdelayisshownhere.IfinitiallyP=4’b0000andQ=4’b1111,theS=5’b10000.

NowifPchangesto4’b0001,thenthis‘1’ intheLSBispropagatedallthewaytoS4.Theworst-casepathisexercised.

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WehavealreadydiscussedtheinsidestructureoftheFPGAinLecture2.Hereisareminder.TheAlteraCycloneVFPGAhasamoreadvancedprogrammablelogicelementthanthesimple4-inputLUTthatwehaveconsidereduptonow.ThecallthisaAdaptiveLogicModuleorALM.

AnALMcantakeupto8Booleaninputsignalsandproducesfouroutputswithorwithoutaregister.Additionally,eachALMalsocanperformthefunctionofa2-bitbinaryfulladder.Thisiswhatinterestusmostforthislecture.

AsauseroftheCycloneVFPGA,youdon’tactuallyneedtoworrytoomuchaboutexactlyhowtheALMisconfiguredtoimplementyourdesign.TheCADsoftwarewilltakecareofthemappingbetweenyourdesignandthephysicalimplementationusingtheALMs.Itishoweverusefultoknowthatasthetechnologyevolves,moreandmorecomplicatedprogrammablelogicelementsarebeingdevelopedbythemanufacturersinordertoimprovetheareautilizationoftheFPGAs.

TheCycloneVontheDE1-SOCboardhas32,000ALMs,whichcouldbeestimatedtobeequivalentto85K+theoldstyleLEs.Puttingthisincontext,

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youcouldputontothisonechip2,00032-bitbinaryaddercircuits!

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GiventhattheFPGAhasspecialaddermode,youshouldneverspecifyyouradderasindividualfulladdercircuitsconnectedtogether.ThesynthesissystemWILLNOTbeabletoexploitthededicatedaddermodeconfigurationshowninthepreviousslide.Insteadusethe‘+’ operatorinVerilogasshownhere.Itissimplerandwillproduceaveryfastadder.

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HowfastareadderswithinatypicalFPGA?Hereisann-bitaddercircuitsandwichedbetweenregisters.TheplotisbasedonaCycloneIIIFPGA.(Idon’thavethedataforCycloneV.)

Wecanusethetiminganalyzertoestimatehowfastwecanclockthiscircuitwithouterrorasthenumberofbitsnisincreasedfrom1to64.Theequationoftheredfittedline.Thisshowsthateachadderbitaddsaround57psdelay.Inaddition,thereisa1.8nsdelayfromclocktoQ+registersetuptime.IexpectthetimingfortheCycloneVdevicestobefaster.

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OlderFPGA(s.g.CycloneIII)hasembeddedmultiplierstomakeimplementationofdigitalsignalprocessingalgorithmsmoreefficientontheFPGA.CycloneVhasDSPsupportfarsuperiortojustsimpleconfigurablemultipliers.TheDSPblocksontheCycloneVcanbeusedforacombinationofdifferentfunctions.Itcandomultiplicationofdifferentprecisionandalsotoperformmultiply-accumulatefunction.Accumulatorisanadderwhoseoutputisusedasoneofthetwoinputsoftheadderonthenextclockcycle.Thereforeanaccumulatorusuallyonlyhasoneinput,whosevalueget“accumulated” cycle-by-cycle.TheDSPblockalsohasinternalstoragetostoreaconstantvalue.Typicallythisisafiltercoefficientforimplementingafinite-impulseresponse(FIR)filter.DetailofhowtouseDSPblocktoimplementonetap(oronestage)ofaFIRfilterisbeyondthescopeofthiscourse.ThoseinterestedcanreadCycloneVDevicesHandbook,Vol.1,p.3-17.

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Forthislecture,weconcentrateontheconfigurablemultipliersintheDSPblock.EachDSPblockcanbeconfiguredasthree9x9multipliers.Thisisparticularlyusefulforreal-timevideoprocessingsinceeachpixelvaluesareoftenrepresentedasan8-bitunsignedvalue(or3x8bitunsignednumberifweareusingcolour).Alternatively,eachblockcanprovideTWO18x18bit,orone27x27bitmultiplier(s).Ofcourseifyouneedlowernumberofbits(say14x14),youcanalwayseitherzero-extend,orsign-extendtheoperandstofitandusethe18x18multiplier.Eachmultipliercanalsobeconfiguredtooperatewiththeadderortheaccumulatorattheoutput.ItisimportanttounderstandthatwhenyoumultiplytwoNxMbitsunsignednumberstogether,yougetaproductwhichisN+Mbits.Thesamealsoappliesifyoumultiplyonesignedandoneunsignednumbertogether.Youcantrythisyourselffortwofour-bitnumbers!However,ifyoumultiplytwosigned2’scomplementnumberstogether,yougetaproductthatisonlyN+M-1bits.Thetoptwo-bitsarealwaysthesameandtheybothprovidethesignoftheproductvalue(i.e.yougettwoidenticalsignbitsintheproduct).Againtrythisyourselfwithtwo4-bitsignedmultiplication.

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IfyouconfigureaDSPblocktobeTHREE9x9multipliers,thetwoinputoperandsaxandayarebit-cascadetoforma27bitinputvaluestotheDSPblockasshownabove.Similar,thethreeproductsareprovidedasthree18-bitRESULTvalueasa54-bitvalue.

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ToinstantiatemultipliersinaCycloneV,wecanusetheIPCatalogtoolunderQuartus.MultiplierisshownunderLibrary>BasicFunctions>Arithmeticcategory.YoushouldchooseLPM_MULT.Adialogueformwillpopup.Youcanthencreatethetypeofmultiplieryouneedforyourdesign.Shownaboveisa10bitx14bitmultiplierusedinex15inPart3ofVERI.The10-bitinputisthefrequencyvaluespecifiedbytheswitchesortheADC,andthe14-bitisthemultiplyingconstant14’d10000.


L23 – Adder Architectures. Adders Carry Lookahead adder Carry select adder (staged) Carry Multiplexed Adder Ref: text Unit 15 9/2/2012 – ECE 3561.

L23 – Adder Architectures. Adders Carry Lookahead adder Carry select adder (staged) Carry Multiplexed Adder Ref: text Unit 15 9/2/2012 – ECE 3561.

Designing of Look Ahead Carry Adder by using VHDL...Sixteen 4-bit adders such as the 4-bit carry look-ahead circuit of Fig. 1 can be connected in this way to form the 64-bit adder

Designing of Look Ahead Carry Adder by using VHDL...Sixteen 4-bit adders such as the 4-bit carry look-ahead circuit of Fig. 1 can be connected in this way to form the 64-bit adder

Block Level Design. Outline Block-Level Design 4-bit Parallel Adder BCD-to-Excess-3 Code Converter 16-bit Parallel Adder 4-bit Parallel Adder.

Block Level Design. Outline Block-Level Design 4-bit Parallel Adder BCD-to-Excess-3 Code Converter 16-bit Parallel Adder 4-bit Parallel Adder.

Full-Adder The Binary Adder - Imperial College London 9 - adders... · Full-Adder E4.20 Digital IC ... Minimize Critical Path by Reducing Inverting Stages ... The Mirror Adder •The

Full-Adder The Binary Adder - Imperial College London 9 - adders... · Full-Adder E4.20 Digital IC ... Minimize Critical Path by Reducing Inverting Stages ... The Mirror Adder •The

Chapter 4. n -bit adder Cascade n full adder (FA) blocks to form a n-bit adder. Carries propagate or ripple through this cascade, n-bit ripple carry adder.

Chapter 4. n -bit adder Cascade n full adder (FA) blocks to form a n-bit adder. Carries propagate or ripple through this cascade, n-bit ripple carry adder.

16 Bit Digital Adders - Concordia Universityasim/COEN_6501/Lecture_Notes/Lecture_2... · bits is called a half adder ... Carry Select Adder Design Linear Carry Select and Non_Linear

16 Bit Digital Adders - Concordia Universityasim/COEN_6501/Lecture_Notes/Lecture_2... · bits is called a half adder ... Carry Select Adder Design Linear Carry Select and Non_Linear

Lecture 7: Adders - ecevn.files.wordpress.com · Adder stage 2 Wiring Adder stage 3 Bit slice 0 Bit slice 2 Bit slice 1 Bit slice 63 Sum Select Shifter Multiplexers Loopback Bus From

Lecture 7: Adders - ecevn.files.wordpress.com · Adder stage 2 Wiring Adder stage 3 Bit slice 0 Bit slice 2 Bit slice 1 Bit slice 63 Sum Select Shifter Multiplexers Loopback Bus From

A Comparative Study of Adders · Figure 30: Layout of a 32-bit Brent Kung Adder 19 . vii Figure 31: Schematic of a 64 bit Brent-Kung Adder 19 Figure 32: Layout of a 64-bit Brent Kung

A Comparative Study of Adders · Figure 30: Layout of a 32-bit Brent Kung Adder 19 . vii Figure 31: Schematic of a 64 bit Brent-Kung Adder 19 Figure 32: Layout of a 64-bit Brent Kung

Incorporation of Reduced Full Adder and Half Adder into ...file.scirp.org/pdf/CS_2016072216085240.pdf · It has 15-full adders and 17-half adders. As the ripple carry adder is used

Incorporation of Reduced Full Adder and Half Adder into ...file.scirp.org/pdf/CS_2016072216085240.pdf · It has 15-full adders and 17-half adders. As the ripple carry adder is used

Topics Adders Half Adder Full Adder Subtracter Half Subtracter Full Subtracter Comparators Multiplexer-Demultiplexer (MUX-DEMUX) Encoder- Decoder.

Topics Adders Half Adder Full Adder Subtracter Half Subtracter Full Subtracter Comparators Multiplexer-Demultiplexer (MUX-DEMUX) Encoder- Decoder.

An Efficient Filter Design for Active Noise Control System comparison between four 16 bit parallel prefix adders- Koggestone adder, Brent Kung adder, Sparse Koggestone adder and Spanning

An Efficient Filter Design for Active Noise Control System comparison between four 16 bit parallel prefix adders- Koggestone adder, Brent Kung adder, Sparse Koggestone adder and Spanning

Design of Hybrid Adder-Subtractor (HAS) using Reversible ... · Fig 6:Schematic of full adder circuit By connecting n such one-bit QCA full adders, n-bit CLA adder can be obtained,

Design of Hybrid Adder-Subtractor (HAS) using Reversible ... · Fig 6:Schematic of full adder circuit By connecting n such one-bit QCA full adders, n-bit CLA adder can be obtained,

Adders and Multiplication - University of New MexicoZbaker/Ece238/Slides/13.PdfFunctional Block: Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from

Adders and Multiplication - University of New MexicoZbaker/Ece238/Slides/13.PdfFunctional Block: Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from

VHDL Tut 4 - XilinX (Bit Adders)

VHDL Tut 4 - XilinX (Bit Adders)

Binary Adders: Half Adders and Full Adders - Edward · PDF fileSlide 1 of 20 slides September 4, 2010 Binary Adders: Half Adders and Full ... The half adder takes two single bit binary

Binary Adders: Half Adders and Full Adders - Edward · PDF fileSlide 1 of 20 slides September 4, 2010 Binary Adders: Half Adders and Full ... The half adder takes two single bit binary

ECE 301 – Digital Electronics Single-bit Adder Circuits and Multi-bit Adder Circuits (Lecture #10)

ECE 301 – Digital Electronics Single-bit Adder Circuits and Multi-bit Adder Circuits (Lecture #10)

Carry Lookahead Adders Ivor Pageivor/ce6305/m4p.pdf · Carry Lookahead Adders 3 inthisfashion. Forak bitaddertherewillbe log4 k levels. Figure2shows a 32-bit adder using 3 levels

Carry Lookahead Adders Ivor Pageivor/ce6305/m4p.pdf · Carry Lookahead Adders 3 inthisfashion. Forak bitaddertherewillbe log4 k levels. Figure2shows a 32-bit adder using 3 levels

Adders Half-adder Adds two bits Produces a sum and carry Problem: Cannot use it to build larger inputs Full-adder Adds three 1-bit values Like half-adder,

Adders Half-adder Adds two bits Produces a sum and carry Problem: Cannot use it to build larger inputs Full-adder Adds three 1-bit values Like half-adder,

9/6/2011 A 4-bit adder - · PDF fileA 4-bit adder • Four full adders together ... – It adds 3 numbers and produces partial ... Consider Adding: S = A + B + C + D + + + + + + +

9/6/2011 A 4-bit adder - · PDF fileA 4-bit adder • Four full adders together ... – It adds 3 numbers and produces partial ... Consider Adding: S = A + B + C + D + + + + + + +

1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)