Implementation of QPSK modulation and demodulation of FPGA

Jin ZHUa, Dandan Yanb

Engineering and Technical College of Chengdu University of Technology, Leshan, 614000, China

a1949450@qq.com; b935215199@qq.com

Keywords: QPSK; FPGA ; modulation and demodulation

Abstract. This paper studies the realization method of QPSK modulation and demodulation circuit

based on FPGA.And the simulation results are given under the environment of MAX+PLUSII .In

this paper, the scheme uses phase selection method, compared with the modulation and

demodulation method commonly used, design more simple, more suitable for FPGA

implementation, the reliability of the system is higher.Through the analysis of the simulation

waveform shows, the very good realization of the QPSK modulation and demodulation function.

Introduction

Since the nineteen eighties medium, four absolute phase shift phase shift keying (QPSK)

technology with its interference ability, good error performance, high use ratio of frequency

spectrum, widely used in the field of digital microwave communication system, digital video

broadcasting, digital broadcasting system, broadband access, mobile communication and cable TV

system.In the domestic and foreign application is very extensive.For example: in the satellite digital

television transmission, QPSK tuner is widely used in optimal selection of the comprehensive

consideration of various factors, the satellite power transmission efficiency and anti-jamming and

antenna size of the satellite digital television transmission.The content of this paper is to use FPGA

to realize the design of a QPSK modem, and the realization of simulation in QUARTUSII

environment.

The principle of QPSK

The QPSK signal is 00, 01, 10, 11, four kinds of state.Therefore, the binary sequence of input,

we must first packet, each two bits of a group.The QPSK signal is actually two orthogonal DSB

signal.First produced in two different phase of the carrier signal f1 and f2, the direct use of input

and double bit phase to select carriers, get the in-phase branch and quadrature branches, then the

two signals, you can get QPSK signal. Finally, the channel is transmitted to the receiving end.

QPSK is a multi-carrier modulation, so can use square Tour de France or Kostas de France

(COSTAS) isolated from the carrier from the modulation signal, demodulation.Modulation signal

by extraction of bit synchronization circuit is extracted from the carrier synchronization signal, and

to stop and then by the carrier synchronization signals to control the counter starts to count, the

modulation signal, finally a decision circuit to determine the modulation signal input is' 0 'or' 1 ', the

output is the baseband signal demodulation.QPSK signal is a synthesis of 2PSK signal of two

orthogonal, coherent demodulation method can be modeled on the 2PSK signal, A and B were

detected in two components by coherent carrier two orthogonal, and then restore the serial binary

digital signal demodulation of QPSK signal, can be completed.

Applied Mechanics and Materials Vols. 427-429 (2013) pp 880-883Online available since 2013/Sep/27 at www.scientific.net© (2013) Trans Tech Publications, Switzerlanddoi:10.4028/www.scientific.net/AMM.427-429.880

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Fig.1 Schematic diagram of QPSK signal demodulation Fig.2 QPSK modulation circuit

System design

Modulation Circuit Design.The QPSK signal is 00, 01, 10, 11, four kinds of state.Therefore, the

binary sequence of input, we must first packet, each two bits of a group.The order of input binary

information through the serial / parallel converter, transforms into a double sequence of bits rate in

half, then according to the combination, with four kinds of carrier phase characterization of them,

can choose one of four selectors to realize.Baseband signal through the serial / parallel converter

has 2 parallel signal, four choose a switch according to the data, select the carrier phase

corresponding to output, which is modulated signal.

Use the start signal to control the input data at the beginning and end of.Based on the CLK

frequency of 8, four phase, and complete the baseband signal and convert the serial.By the middle

of the xx register, enter a four bits per clock pulse, the STD logic vector XX one assignment,

implementation of serial-parallel conversion function.In the first pulse occurs when the intermediate

register value assigned to a 2 bit parallel yy register, the output waveform of the assignment of f

carrier phase.

Table 1.Modulation signal description Table 2 Demodulation signal description

Using VHDL language to program input modulation circuit, modulation circuit program is

compiled, parameter setting based on compile successfully on the timing simulation, the simulation

results are shown in Figure 4 and analyze the simulation results.

Fig. 3 QPSK modulation circuit simulation waveform

According to the simulation result:Start signal as control signal, the control input baseband signal

with or without, so the signal assignment for high level 1;Signal q as the counter output value, range

0-7;Use of signal assignment of f to achieve the desired phase waveform;The input baseband signal

into x“1001110001101101”; The program using the middle register xx to achieve signal and string

Applied Mechanics and Materials Vols. 427-429 881

conversion functions, so the yy signal output value should be "10", "01", "11", "00", "01", "10",

"11", "01".But as the intermediate registers, program the results of theoretical analysis, YY output

waveform should be "00", "10", "01", "11", "00", "01", "10", "11", "01".By the waveform can be

seen in figure, the waveform and the theoretical analysis was consistent with the yy;phase sequence

representation for:0,π,π/2,3π/2,0,π/2,π,3π/2 ,π/2，And the output waveform waveform y perfectly,

than the theoretical analysis of the input sequence waveform represents a 0 phase, so for the

modulation signal, it should be from ninth clock pulse signal to start receiving is modulated signal

integrityAt the output signal y in waveform waveform and yy waveform can be seen, the realization

of the phase shift keying function.The four phase waveform represents a pair of bit.After the test

waveforms observed as shown in Figure 5 that when the modulation signal respectively in the "01",

"00", "10", "11", the corresponding phase transformation between the change, meet QPSK

expectation phase modulation waveform.

Fig.4 QPSK modulation circuit of phase diagram Fig.5 The demodulation circuit principle diagram

The Demodulation Circuit Design.When the modulation is low, the decoder 1 according to the

counter output value, the corresponding data into adder.The calculation results to the register adder,

decoder 2 according to the register data by decoding, output two bits parallel signal, the signal

through a parallel-serial conversion can be obtained by the baseband signal after demodulation, the

demodulation diagram as shown in fig.. Using the start signal modulation signal control input and

end.Using four phase waveform

Demodulation signal description as shown in the following table. A signal period is divided into

4 parts, a high equity values were 0, 0, 0, 0, low parity values were 1, 1, 2, 3.After the adder

computing can have different output to input data.With the same modulation principle, the use of

intermediate register save adder output, output one each of the four clock pulse, implementation and

string conversion functions.For example, "00" on the carrier said, in the first two two periods is

high, weight is 0 so to adder number "000", in the third period is low, the weight is 2 so to adder

number is "010", in the fourth period is low, the weight is 3, so the into the adder number is "011",

so the final results for the "000" and "000" + "010" + "011" =0+0+2+3=5. Other phase generated

carrier waveform and so on.Details are shown in Table 2

According to the above derivation can design a demodulation circuit shown in Figure 6 below:

The demodulation circuit program is compiled by the waveform analysis.

Fig. 6 The simulation result of QPSK demodulation circuit

882 Mechanical Engineering, Industrial Electronics and Information TechnologyApplications in Industry

Conclusion

QPSK consists of four different phases represent four kinds of different digital information, for a

sequence of binary digits input, first group, two bits for a group, then use the phase and quadrature

carrier phase to represent each of the bit, is to use four different phase to represent them.For the

QPSK design, the demodulation output binary sequence than the original input binary sequence five

bits of information, it should be from twenty-first clock pulse output waveform received is the

binary input sequence waveform accurately, it is the realization of the demodulation function of

QPSK.

Fig.7 The modulation and demodulation of QPSK debugging circuit module

The modulation and demodulation waveform can be seen, in the input signal to the output signal

waveform modulation and demodulation simulation waveforms of the agreement, the modulation

and demodulation process was used in the intermediate register, modulation procedures used

register the modulation signal that a bit "00",

elsif q=0 then q<=1;f(3)<='1';f(1)<='0';xx(1)<=x;yy<=xx;

Baseband signal demodulation program register makes the demodulated by the demodulation

input than sequence represented by the extra three bits of information "000",

elsif q=0 then q<=1;yy<=xx;y<=yyy(0);

elsif q=4 then q<=5;y<=yyy(1);

This makes the final demodulation results than the original input sequence more than five bits of

information "00000", it should be from twenty-first clock pulse output waveform received is the

binary input sequence waveform accurately.

Reference

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Mechanical Engineering, Industrial Electronics and Information Technology Applications in Industry 10.4028/www.scientific.net/AMM.427-429 Implementation of QPSK Modulation and Demodulation of FPGA 10.4028/www.scientific.net/AMM.427-429.880