1

IMPACT OF MECHANICAL STRESS ON SILICON AND GERMANIUM METAL-OXIDE-SEMICONDUCTOR DEVICES: CHANNEL MOBILITY, GATE TUNNELING CURRENTS,

THRESHOLD VOLTAGE, AND GATE STACK

By

YOUN SUNG CHOI

A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2008

2

© 2008 Youn Sung Choi

3

To my parents in Korea and family, Luke and Jin-Hwa

4

ACKNOWLEDGMENTS

First and foremost I would like to thank my advisor, Dr. Scott E. Thompson, for his

constant encouragement and expert guidance over the past four years. I have learned many

things, including how to solve critical problems from a simple model and logical thinking, from

him. I also would like to convey my special thanks to my co-advisor, Dr. Toshikazu Nishida. His

consistent advice and technical writing skill have been very valuable in the course of my

research. I also would like to express my gratitude to my committee members (Dr. Arnost

Neugroschel, Dr. Jing Guo, and Dr. Franky So) for their interest and suggestions on my research.

My colleagues in our lab have contributed significantly to my Ph.D. research work through

interactive discussions. I would like to thank Dr. Ji-song Lim for his priceless help to publish my

first publication, which has been a booster for my research works. Dr. Toshinori Numata, a

visiting scholar from Toshiba, also gave me a lot of insightful ideas and reviewed a couple of my

publications. Hyunwoo Park, Uma Aghoram, Min Chu and Andrew Koehler have been with me

during my Ph. D. study and given me valuable ideas. I also would like to thank previous group

members, Dr. Sagar Suthram and Dr. Guangyu Son, and current members, Dr. Yongke Son,

Tony Acosta, Ukjin Roh, Xiaodong Yang, Srivatsan Parthasarathy, Mehmet Baykan and others

for their helps.

I dedicate this dissertation to my parents and family. I especially thank my father, mother,

and younger brother in Korea for their endless support and love, which have made me what I am

now. I also owe my deepest thanks to my wife, Jin-Hwa Lee, who has stood by and encouraged

me, and my son, Luke Jun-Young Choi, who has grown up healthily.

5

TABLE OF CONTENTS page

ACKNOWLEDGMENTS ...............................................................................................................4

LIST OF TABLES...........................................................................................................................7

LIST OF FIGURES .........................................................................................................................8

ABSTRACT...................................................................................................................................11

CHAPTER

1 INTRODUCTION ..................................................................................................................13

Overview of Strained CMOS Technology .............................................................................13 How to Apply Strain to MOSFETs ........................................................................................15 Brief Description of Study......................................................................................................19

2 UNIAXIAL-STRESS-INDUCED CHANNEL MOBILITY ENHANCEMENT..................21

Physics ....................................................................................................................................21 Strain Enhanced Hole Mobility ..............................................................................................26

3 STRAIN EFFECTS ON GATE LEAKAGE CURRENTS OF GERMANIUM (Ge) MOS DEVICES......................................................................................................................32

N-Type Metal-Oxide-Semiconductor Field Effect Transistors ..............................................32 Ge Conduction Band Edge Shift and Splitting................................................................32 Theoretical Model ...........................................................................................................34 Experimental Set-Up and Results....................................................................................36 Extraction of Conduction Band Deformation Potentials.................................................40 Summary..........................................................................................................................42

P-Type Metal-Oxide-Semiconductor Field Effect Transistors...............................................43 Experimental Set-Up .......................................................................................................43 Stress Altered Hole Tunneling Currents of Ge and Si p-MOSFETs...............................44 Stress Altered Electron Tunneling Currents From Metal Gate .......................................51 Summary..........................................................................................................................55

4 IMPACT OF MECHANICAL STRESS ON DIRECT AND TRAP-ASSISTED GATE LEAKAGE CURRENTS IN P-TYPE MOS CAPACITORS ................................................56

Introduction.............................................................................................................................56 Experimental Set-Up ..............................................................................................................56 Results and Discussions..........................................................................................................57 Conclusions.............................................................................................................................59

6

5 STRAIN INDUCED CHANGES IN GATE LEAKAGE CURRENT AND DIELECTRIC CONSTANT OF NITRIDED HF-SILICATE DIELECTRIC SILICON MOS CAPACITORS..............................................................................................................62

Introduction.............................................................................................................................62 Experimental Procedures ........................................................................................................62 Results and Discussions..........................................................................................................63 Conclusions.............................................................................................................................67

6 IMPACT OF DIFFERENT GATE STACKS AND CHANNEL MATERIALS ON THRESHOLD VOLTAGE SHIFTS IN P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER MECHANICAL STRESS................................69

Introduction.............................................................................................................................69 Threshold Voltage Shift Models.............................................................................................69 Results And Discussion ..........................................................................................................71 Conclusion ..............................................................................................................................72

7 RELIABILITY OF NITRIDED HAFNIUM SILICATE GATE DIELECTRICS UNDER [110] UNIAXIAL MECHANICAL STRESS: TIME DEPENDENT DIELECTRIC BREAKDOWN..............................................................................................77

Introduction.............................................................................................................................77 Experimental Setup.................................................................................................................78 Experimental Results ..............................................................................................................79 Discussion...............................................................................................................................82 Conclusion ..............................................................................................................................86

8 SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK..................................88

Summary.................................................................................................................................88 Recommendations for Future work ........................................................................................89

LIST OF REFERENCES...............................................................................................................91

BIOGRAPHICAL SKETCH .......................................................................................................106

7

LIST OF TABLES

Table page 3-1. Dilation (Ξd) and shear (Ξu) deformation potentials extracted from gate tunneling

current of Ge MOS device under tensile stress along [100] and [110]..............................42

6-1. Deformation potential constants used in this study [17] and CEΔ and gEΔ of Si and Ge, calculated at 300 MPa of uniaxial tension and compression along [110] direction. ............................................................................................................................73

6-2. Model-predicted, with m=1.3, contributions of band edge shifts, DOS change, Δµ and ΔΦM terms. (ΔΦM is estimated from [102]) ................................................................74

7-1. Measured and estimated reliability issues of thick (> 7 nm) high k Si MOSFET as a function of uniaxial mechanical stress...............................................................................87

8

LIST OF FIGURES

Figure page 1-1. Process architecture for strained Si....................................................................................17

1-2. Uniaxial four point wafer bending jig: two pairs of cylindrical rods are used and a sample is inserted between the pairs. .................................................................................18

1-3. Uniaxial wafer bending jig. The displacement (d) is defined as d=di-df. .........................18

2-1. Hole constant energy band surfaces for the top band obtained from 6 band kp calculations for common types of 1GPa stresses..............................................................23

2-2. Summary of key valence band parameters for top and second band for bulk Si under 500MPa stress.. ..................................................................................................................25

2-3. Conduction valley energy level splitting under 500MPa of longitudinal uniaxial tensile stress: bulk and MOSFET inversion layer (1MV/cm). ........................................26

2-4. Valence energy band splitting calculated using 3 different models versus inversion charge density for longitudinal compression and biaxial tension stress. .........................28

2-5. Calculated and experimental data for longitudinal compressive and biaxial tensile stress enhanced mobility vs. stress (Biaxial stress= σX+σY)............................................31

3-1. Conduction-band constant energy ellipsoids are centered at the L point, and the major axis of eight half ellipsoids are along Λ or [111] direction.. ...................................33

3-2. Schematic band diagrams for direct electron tunneling from inversion layer in Ge MOS device. ......................................................................................................................34

3-3. The [100] tensile stress-altered gate tunneling current for Ge MOS device under different gate biases. ..........................................................................................................38

3-4. The [110] tensile stress-altered gate tunneling current of Ge MOS device under different gate biases. ..........................................................................................................39

3-5. The [110] tensile stress-altered electron gate tunneling current of Ge and Si devices at inversion charge of 1013/cm2, where 1.2 V and 0.6 V gate biases are applied for Si and Ge MOS devices, respectively[68] .............................................................................39

3-6. Schematic band diagrams for [110] tensile stress effects on electron gate tunneling in Si and Ge devices...............................................................................................................40

3-7. Change in slopes ( σσ dIId GG /)]0(/)([Δ ) versus gate voltage with 95% confidence error bars for tensile stress along [100]..............................................................................41

9

3-8. Change in slopes ( σσ dIId GG /)]0(/)([Δ ) versus gate voltage with 95% confidence error bars for tensile stress along [110]..............................................................................42

3-9. Carrier separation measurement of p-MOSFET and 4-point wafer bending. The gate tunneling current (IG) can be separated into electrons (IG,electron)and holes (IG,hole) tunneling from gate and substrate, respectively[75]. .........................................................44

3-10. Carrier separation measurement of a) Source/drain (IS/D) and substrate tunneling current (ISUB) as a function of gate voltage (VG) for Ge p-MOSFET. b) IS/D and ISUB as a function of VG for Si p-MOSFET...............................................................................47

3-11. Relative change in IS/D of Si and Ge p-MOSFET as a function of stress. Symbols and lines are measured data and modeling, respectively. .........................................................48

3-12. Schematic band diagram for the hole gate tunneling current in a p-MOSFET on a (100) wafer.........................................................................................................................48

3-13. Valence band edge splitting of Ge and Si under tensile stress along [110]. ......................49

3-14. Charge density versus applied stress for the top (E1), bottom (E2), and third sub-bands (E3) at an inversion charge density of 3.5x1013/cm2 for a) Ge and b) Si, respectively. .......................................................................................................................50

3-15. Relative change in ISUB of Ge p-MOSFET as a function of stress at gate bias of -2.8V....................................................................................................................................53

3-16. The VFB shift under uniaxial stress. ...................................................................................53

3-17. Work-function shifts of TaN, bulk Al and bulk Cu as a function of stress[87]. Work-functions of three different metal increase/decrease with compressive/tensile stress. Line is the linear fit of extracted data. ...............................................................................54

3-18. Relative changes in gate tunneling current of MOS capacitor with TaN gate as a function of stress. Symbols and lines are measured data and modeling, respectively.......54

4-1. Relative change of gate leakage currents in MOS devices before constant voltage stress (CVS) and after CVS as a function of applied mechanical stress along [110] direction. ............................................................................................................................60

4-2. Schematic band diagrams for direct and trap-assisted gate tunneling mechanisms. Key parameters for mechanical stress-altered electron gate tunneling currents before and after CVS are summarized in table. ............................................................................61

4-3. Schematic of SiO2/(100) Si interface structure including Pb0 and Pb1 centers, showing mechanical stress-induced changes in dangling bond angles (Ө) and interface trap activation energy (ΦT)........................................................................................................61

10

5-1. The C-V characteristics at 1MHz of the MOS device with Pt and Al gate on nitrided Hf-silicate film. The inset shows current density-voltage (J-V) measurements of both devices................................................................................................................................64

5-2. Poole-Frenkel (ln(J/E) vs E1/2) plot of Pt and Al gate on nitrided Hf-silicate film at 25 oC. Inset in figure shows a schematic band diagram for MOS capacitors with HfSiON dielectric and interlayer and metal gates (Pt and Al) under negative gate bias. ....................................................................................................................................64

5-3. Changes in gate leakage current of Si MOS capacitors with HfSiON dielectric as a function of applied stress. ..................................................................................................66

5-4. Changes in dielectric constant of HfSiON, HfSiOx and HfO2, measured from C-V and PF slope change...........................................................................................................67

6-1. Plots of uniaxial stressed Vth shifts of p-MOSFETs with different gate stacks (poly Si/SiO2 vs TiN/HfO2) and different channels (Ge vs Si). Symbols and lines are experimental data and calculated models, respectively. ....................................................75

6-2. Plots of Vth shifts of Ge and Si p-MOSFETs with the mobility correction as a function of stress. Symbols and lines are experimental data and calculated models, respectively. The inset shows the relative changes in mobility of Ge and Si p-MOSFETs with TiN/HfO2 gate stack as a function of stress.............................................76

7-1. Current-time curve for 7 nm HfSiON dielectric Si MOS device during CVS ..................78

7-2. The tBD distributions and area scaled tBD distributions for different size samples under VG = -5.2 V. .............................................................................................................80

7-3. Uniaxial tensile stress effect on tBD distributions and area scaled tBD distributions under VG = -5.2 V. .............................................................................................................81

7-4. Uniaxial compressive stress effect on tBD distributions and area scaled tBD distributions under VG = -7 V. ...........................................................................................81

7-5. The QBD distributions for samples with two different HfSiON dielectrics thickness (7 and 8 nm) under tensile mechanical stress.........................................................................82

7-6. Interface trap generation under mechanical stress .............................................................85

7-7. Schematic band diagram for key strain-related parameters for reliability issues. .............85

11

Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

IMPACT OF MECHANICAL STRESS ON SILICON AND GERMANIUM METAL-OXIDE-SEMICONDUCTOR DEVICES: CHANNEL MOBILITY, GATE TUNNELING CURRENTS,

THRESHOLD VOLTAGE, AND GATE STACK

By

Youn Sung Choi

December 2008

Chair: Scott E. Thompson Cochair: Toshikazu Nishida Major: Electrical and Computer Engineering

Our study explores the impact of uniaxial mechanical stress on metal-oxide-semiconductor

devices in terms of channel mobility, gate direct tunneling current, trap-assisted gate tunneling

current, threshold voltage, high-k gate dielectric, and metal gate using four point wafer bending

setup. Beyond 90 nm technology node, strained Si technology has been a mainstream in VLSI

manufacturing technology. Therefore, it is important to properly understand strain effects on

channel mobility and also other electrical parameters, such as gate leakage, gate stack, and

reliability of MOS devices.

Process-induced uniaxial stress has been compared with substrate-induced biaxial tensile

stress and its advantages on Si p-MOSFETs have been pointed out. The net band splitting from

strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial

tensile stress. This results in larger hole mobility enhancement under uniaxial compressive stress.

Impact of uniaxial mechanical stress on gate direct tunneling current in Si and Ge MOS

devices are investigated. Because of the different conduction edges of Si and Ge, opposing

uniaxial mechanical stress dependence has been observed in gate direct tunneling currents of Si

and Ge n-MOSFETs. Based on gate bias-dependent gate direct tunneling current under

12

mechanical stress, Ge conduction band deformation potentials have been extracted and agree

well with theoretical calculations. We also measure gate direct tunneling current of Si and Ge p-

MOSFETs under mechanical stress using carrier separation technique in order to investigate

strain effects on subband structure in p-type inversion layer of Si and Ge. Due to larger strain-

induced valence band edge splitting in Ge, the relative change in gate tunneling current in Ge is 3

times larger than that in Si under uniaxial tensile stress.

Strain effects on trap-assisted gate tunneling mechanism, including trap-assisted

tunneling and Poole-Frenkel emission, are also investigated from both SiO2 and nitrided hafnium

silicate (HfSiON) gate dielectric Si MOS capacitors. A decrease in electron and/or hole trap

activation energy results in an increase in trap-assisted gate tunneling current with both [110]

tensile and compressive stresses. The dielectric constant of HfSiON also increases with

mechanical stress, resulting from strain-induced N p band splitting, which reduces the band gap

of HfSiON.

13

CHAPTER 1 INTRODUCTION

1.1 Overview of Strained CMOS Technology

Strain effects on semiconductors such as silicon (Si) and germanium (Ge) have been

extensively studied to maintain historical performance improvement. Bardeen and Shockley

introduced a deformation potential theory, explaining that the electron- or hole-phonon

interaction causes a static displacement of the atoms, thus resulting in the conduction or valence

band energy shifts[1]. Herring et al. and Pikus et al. quantified the conduction and valence band

energy shift as a function of strain, respectively, based on deformation potential constants, which

are important parameters in strained CMOS technology[2, 3].

The origin of strained-Si to improve CMOS devices can be traced to thin Si layer grown

on relaxed SiGe substrates in 1980s[4, 5]. The thin Si layer takes the larger lattice constant of the

SiGe and creates biaxial tensile stress. Wafer-based substrate strain was experimentally and

theoretically studied by a large number of researchers for two decades[6]. In the 1990s, two other

strained-Si activities started based on process-induced strain. First, high-stress capping layers

deposited on MOSFETs were investigated as a technique to introduce stress into a channel.[7]

Second, Gannavaram et al [8] proposed SiGe in the source and drain area for higher boron

activation and reduced external resistance. It was this embedded SiGe literature that prompted

Intel [9] to evaluate the technology, which resulted in larger than expected device performance

enhancement, which, after considerable internal debate, was later attributed to uniaxial

compressive channel stress[10]. Still, neither biaxial nor uniaxial stress was immediately adopted

in CMOS logic technologies for several reasons. Biaxial stress suffers from defects and

performance loss at high vertical electric fields[11]. Process-induced stress requires different

stress types (tensile and compressive for n- and p-channel, respectively) to simultaneously

14

improve both n- and p-channel devices. However, inside Intel and in the industry, strain was

becoming recognized as offering the best potential to enhance performance in sub-100-nm

process technologies (significantly larger performance gain than high-κ gates, fully depleted

silicon-on-insulator (SOI), or multi-gate devices). The only debate was on the best path to take

(biaxial substrate versus uniaxial-process-induced stress)[12].

Careful analysis of the 1990’s biaxial and uniaxial strained-Si experimental data suggested

that the industry adopt process-induced uniaxial strain. The key observations are as follows. First,

uniaxial (versus biaxial) stress provides significantly larger hole mobility enhancement at both

low strain and high vertical electric field due to differences in the warping of the valence band

under strain[13]. Large mobility enhancement at low strain is important since yield loss via

dislocations occurs at high strain. Second, uniaxial (as compared to biaxial) stress enhanced

mobility provides larger drive current improvement for nanoscale short-channel devices. This

results since the uniaxial stress-enhanced electron and hole mobility arises mostly from reduced

conductivity effective mass (versus reduced scattering for biaxial stress), since uniaxial shear

stress provides significant valence and some conduction band warping. Lastly, process-induced

uniaxial stress causes approximately five times smaller n-channel threshold voltage shift. Since

any threshold voltage shift needs to be retargeted by adjusting channel doping (for industry

standard poly-Si gate devices on bulk or partially depleted SOI), the larger threshold voltage

shift for wafer substrate-induced biaxial tensile stress causes approximately half of the stress-

enhanced electron mobility to be lost[14]. Rarely is the stress-induced threshold voltage shift

taken into account in the biaxial tensile-stress mobility data.

On the other hand, Ge and strained Ge are currently being investigated as a potential

replacement to strained Si[15, 16]. To characterize strained Ge, accurate deformation potential

15

constants (Ξd and Ξu) are required to model the strain induced energy level shifts and splitting.

Recently, strain altered gate leakage current has been proposed as an accurate method to extract

conduction band deformation potential constants and has been applied to Si with the results

matching theoretical expectations[17, 18]. For Si p-MOSFETs, uniaxial tensile stress increases

while compressive stress decreases the gate tunneling current[19, 20]. An opposite dependence

exists in Si n-MOSFETs[18, 21]. These results can be understood from the strain-altered out-of-

plane effective mass, energy splitting, and carrier repopulation in Si inversion layer[20], which

can be used to understand impact of strain on gate tunneling currents of Ge n- & p-MOSFETs.

Since Ge MOSFETs are usually incorporated with high k dielectric and metal gate, strain

effects on metal/high-k dielectric gate stack, such as strain altered metal gate work function and

high-k dielectric constant, can change the electrical parameters, such as the threshold voltage,

gate leakage current, gate capacitance and so on.

Unlike SiO2 technology, high-k dielectric technology suffers from trap-related problems

(i.e. bulk and interface traps) which may result in a degradation of the benefit from strain

technology. Even in SiO2 devices, especially in nonvolatile memory (NVM) application, stress-

induced leakage current (SILC) has become a major concern for the reliability of the tunneling

dielectric, resulting from the generated interface trap due to the repeated high-field stress

(Fowler-Nordheim stress)[22, 23]. Therefore, it is important to understand impact of mechanical

stress on trap-assisted gate leakage and dielectric breakdown.

1.2 How to Apply Strain to MOSFETs

This section describes two techniques used in commercial 90 and 65 nm logic technologies

to introduce uniaxial stress into the Si channel. The techniques in production include high stress

16

tensile and compressive SiN capping layers and selective epitaxial SiGe deposited in

recessed/raised source and drains.

The cost to implement process stressors is low at less than approximately 2-3% due to the

comparatively few new process steps. Several process flows exist to introduce the epitaxial SiGe

into a MOSFET[24-26]. The first consists of the steps shown in Fig. 1-1(a). The source/drains

are etched creating a silicon recess. Next, SiGe (for p-channel) or SiC for n-channel is epitaxially

grown in the source and drain. First generation embedded SiGe used ~17% Ge to create

~500MPa of channel stress. Future generations bring the SiGe closer to the channel and will

likely increase the Ge concentration[25, 27]. Locating the SiGe closer to the channel will require

reduced midsection thermal cycles to prevent any boron or Ge out-diffusion from the SiGe into

the channel. To date a maximum of ~900MPa of stress has been created with embedded SiGe

and impressive current improvements from 60-90% have been demonstrated on short devices

(~35 nm)[25, 27].

Instead of embedded SiGe, dual stress liners (tensile and compressive capping layers) [28]

are also being widely adopted[29, 30]. The advantages of a dual stress liner flow over epitaxial

SiGe are reduced process complexity and integration issues. Recent progress in increasing stress

of SiN films to ~3.0GPa for compressive and ~2.0GPa tensile [31] increases the attractiveness of

this option. The capping films are introduced either as a sacrificial layer before source and drain

anneal [28, 31, 32] or as a permanent layer post salicide (Fig. 1-1(b)). With 2-3GPa stress in the

SiN, comparable performance to the first generation SiGe has been demonstrated. The process

flow consists of a uniform deposition of a high tensile SiN liner post silicidation over the entire

wafer followed by patterning and etching the film off p-channel transistors. Generally a thin etch

stop layer is used under the liner to prevent any damage to the silicide. With highly selective

17

etches, the etch stop layer can be < 50A which only slightly degrades the stress transfer into the

channel. Next, a highly compressive SiN layer is deposited and this film is patterned and etched

from n-channel regions.

Figure 1-1. Process architecture for strained Si (a) p-channel MOSFET process flow for the representative stacked gate transistor and TEM cross sectional view (source: Chipworks) and (b) dual stress liner with tensile and compressive silicon nitride capping layers.

In this work, instead of process-induced stress described above, four point wafer bending

technique has been used to apply strain to MOS devices. Figure 1-2 and 1-3 show the fixture to

simulate uniaxially strained MOSFETs as shown in figure 1-1.

18

Figure 1-2. Uniaxial four point wafer bending jig: two pairs of cylindrical rods are used and a sample is inserted between the pairs.

Figure 1-3. Uniaxial wafer bending jig. The displacement (d) is defined as d=di-df. (a) an unstressed sample (b) a stressed sample.

19

Such a bending structure has been well studied and a relation between the applied force and

stress under uniform stress is given by [33]

⎥⎦⎤

⎢⎣⎡ −

⋅⋅=⋅=

32

22 aLa

dtYY εσ (1-1)

Here, σ and ε are the stress and strain values at the center of the sample respectively, Y is

Young’s modulus of Si along the stress direction, 2

DLa −= , and the deflection d is the vertical

displacement between the upper and lower plates of the uniaxial jig when we apply stress. In Fig.

1.3, d is defined as d = di - df, and actually measured by the change in micrometer graduations.

The stress calibration of this setup has been done with both strain gauge and optical curvature

measurements.

1.3 Brief Description of Study

The main purpose of our study is to understand the strain effects on Si and Ge MOSFET

operations: channel mobility, gate tunneling currents (direct and trap-assisted tunneling

mechanisms), threshold voltage, high k dielectric constant, and reliability related to dielectric

breakdown.

The brief explanation of strain-induced mobility enhancement of Si MOSFETs is given

and the physics behind some strained-Si experimental data is explored.

The strain effects on direct gate tunneling currents of Si and Ge MOSFETs are compared

and explained. Based on experimental observations, qualitative analyses are made for both n-

and p- MOSFETs. Next, deformation potential constants of Ge conduction band edge are

extracted from the measured gate tunneling current under mechanical stress.

20

The impact of mechanical stress on gate leakage current based on trap-assisted conduction

mechanism for Si MOS capacitors is discussed using constant voltage stressing and compared

with strain-altered direct tunneling current.

Strain induced changes in gate leakage current and dielectric constant of nitirided Hf-

silicate dielectric (HfSiON) Si MOS capacitors are explored with qualitative explanations.

Strain-induced threshold voltage shift models of different channel materials (Si and Ge)

and gate stacks (Poly Si/SiO2 and TiN/HfO2) are discussed with theoretical modeling. Each

component of model is analyzed thoroughly in conjunction with its underlying physical

mechanism.

Impact of mechanical stress on time dependent dielectric breakdown of HfSiON is also

investigated using controlled external applied mechanical stress and its mechanism is

experimentally clarified.

21

CHAPTER 2 UNIAXIAL-STRESS-INDUCED CHANNEL MOBILITY ENHANCEMENT

2.1 Physics

When deciding on a strained-Si process flow, it is first necessary to comprehend the

potential magnitude for electron versus hole mobility enhancement and whether the mobility

enhancement results from reduced conductivity effective mass or scattering. Since the valence-

band dispersion relationship for semiconductors depends on nearest neighbor atomic spacing,

certain stress (in particular shear stress) warps the valence bands (although less so for conduction

band but some warping for shear stress)[34]. The warping of the valence band provides dramatic

changes to the constant-energy surfaces in k space and can lead to large hole mobility

enhancement via reduced conductivity mass in the channel direction. Mobility enhancement via

reduced mass (as opposed to reduced scattering) is a key in nanoscale MOSFETs and often not

appreciated. Only mobility enhancement from reduced mass (unlike reduced scattering) is

maintained at the very short 15–20-nm channel lengths (35-nm gate length) devices currently in

production[35, 36]. A strained-Si flow, which is scalable for multiple technology nodes, thus,

needs to focus on reducing the hole conductivity mass with the goal of improving the n/p ratio

from ∼ 2 to ∼ 1. Therefore, in this section, we will focus on strain-enhanced hole mobility from

reduced conductivity mass. As a starting point, it is helpful to visualize the effect of strain on the

valence-band constant-energy surfaces in k space for bulk Si. Fig. 2-1 shows the surfaces

obtained using six band k • p and band parameters in [37]. The strain-altered surfaces for the top

two bands are shown at 1 GPa for the common stresses of interest: longitudinal compression on

(001)[24, 25, 38, 39] and (110) hybrid wafer orientation [39] and biaxial tensile stress. [40] Note

from the constant-energy surfaces in Fig. 2-1, the heavy and light hole bands lose their meaning

and we label the bands (first, second, etc.) in this work. Some important differences in the band

22

structure under the various stresses at 500 MPa are summarized in Fig. 2-2 for the in-plane and

out-of-plane conductivity effective masses and density of states at the band edge. We will refer

to Fig. 2-2 in the next section during analysis of experimental data.

Before covering strain-altered hole mobility calculations, we will briefly cover a

qualitative model for strain-enhanced electron mobility since the concepts are similar for

electrons and holes. The important concepts to understand are strain-induced energy-level

splitting, inversion-layer quantum confinement energy-level shifts, average mass change due to

repopulation and band warping, two-dimensional (2-D) density of states, and interband scattering

changes due to band splitting. All of these will be discussed in the following sections. A simple

qualitative model is now presented to gain insight and to understand the more complex

mathematics used elsewhere [11] and later in this work.

The electron mobility in bulk strained-Si along <110> direction is determined by

occupation and scattering in the Δ2 and Δ4 valleys and can be expressed as

2 4

2 4 2 4* * /( )efft l

n nq n n

m mμ τ τΔ Δ

Δ Δ Δ Δ

⎛ ⎞= + +⎜ ⎟

⎝ ⎠ (2-1)

where q, n, τ , and m are the electron charge, concentration, relaxation time, and conductivity

mass in the MOSFET channel direction, respectively. Strain improves the mobility by increasing

the electron concentration in the Δ2 valley. The repopulation improves the average in-plane

conductivity mass (unstressed: mt = 0.19m0 versus ml = 0.98m0) and some further improvement is

possible for stresses that warp the conduction valleys and lower mt[34]. Reduced intervalley

scattering by the strain-induced splitting between Δ2 and Δ4 plays some role (enhances long

channel mobility) when the splitting becomes comparable or larger than the optical phonon

energy. In addition to a low in-plane mass, a high out-of-plane mass for the Δ2 valley electron is

23

equally important since carrier motion perpendicular to the SiO2 interface (taken as the z-

direction in this paper) is quantized. This quantization in addition to strain alters the position of

the energy levels. The quantization leads to bands becoming subbands since only discrete wave

vectors kz are allowed. Including quantization, the total inversion-layer electron energy is given

by discrete values of energy (En) added to the electron energy in the x- and y-directions (in the

plane of the MOSFET)[41].

Figure 2-1. Hole constant energy band surfaces for the top band obtained from 6 band kp calculations for common types of 1GPa stresses (a) unstressed, (b) biaxial tension, (c) longitudinal compression on (001) wafer, (d) longitudinal compression on (110) wafer. (Note significant differences in stress induced band warping altering the effective mass).

24

y

y

x

xn m

kmk

22

22 hh++Ε=Ε (2-2)

Each step in energy is called a subband with En the energy of the bottom of the subband.

As an example, self-consistent solution of Schrödinger and Poisson equation for 500 MPa of

uniaxial tensile stress and an inversion-layer vertical field of 1 MV/cm gives the energy levels, as

shown in Fig. 2-3. Since the subband separation is greater than kT, nearly all the electrons in

most cases occupy the bottom two subbands [ground state n = 0 typically called Eo (from Δ2) and

Eo_ (from Δ4)]. The ground state energy is significantly lower for the Δ2 valleys because of the

higher quantization mass (Δ2 : mz = 0.98m0 versus Δ4 : mz = 0.19m0) which leads to increased

splitting between the bottom two subbands and confinement and strain splitting being additive

(for the common biaxial and uniaxial tensile stress). Note, the strong confinement in an

MOSFET shifts the energy levels more than the moderate ∼ 500-MPa stress typically used in

present-day production logic technologies. Thus, a high out-of-plane mass in the bottom subband

(top subband for holes) is an important requirement for the strain altered band structure.

Lastly, in addition to a low in-plane and high out-of-plane effective mass, a high in-plane

mass perpendicular to the channel direction is also important. The density of states per unit area

for the quantized system is yxoyx dkdkmmm )/()2/(2 2π , which results in the density-of-states

mass approximated by yxD

DOS mmm =2 . Though strain does not significantly alter the electron

subband density of states, as discussed next, a high DDOSm2 will be shown to be important for

maintaining a hole concentration in the top subband.

25

Figure 2-2. Summary of key valence band parameters for top and second band for bulk Si under 500MPa stress. The conductivity and density of states effective mass is listed at Gamma point. Uniaxial compression is longitudinal along <110> channel direction. (Note significant differences for in-plane, out-of-plane and density of states masses).

Similar to strained enhanced electron mobility, hole mobility in an inversion layer can

qualitatively be described as resulting from occupation and scattering in the top two bands

)/( 2*110,2

22*

110,ndtop

nd

ndnd

top

toptopeff pp

mp

mp

q +⎟⎟⎠

⎞⎜⎜⎝

⎛+= ττμ . (2-3)

However, hole transport is more complicated since strain significantly warps the valence

band (as seen in Fig. 2-1) altering both the in and out-of-plane mass and DDOSm2 . Further, the mass

changes with stress and is not constant in k space. As follows from the previous discussion on

strain enhanced electron transport, an advantageous strain for holes needs to warp the valence

band to create both a low in-plane and high out-of-plane mass and if possible a large mass in the

plane of the MOSFET perpendicular to the channel direction (creates a large DDOSm2 ). Band

calculations and measurements to be discussed next show uniaxial stress warps the valence band

26

creating most of these features. The strain altered band structure is calculated using 6 band kp,

including quantum confinement via a self-consistent solution of Schrödinger and Poisson

equation[41, 42]. The mobility is calculated by a linearization of the Boltzman transport equation.

The numerics confirm that the simple qualitative model captures much of the essential physics

for understanding the physical mechanisms for mobility enhancement.

Figure 2-3. Conduction valley energy level splitting under 500MPa of longitudinal uniaxial tensile stress: bulk and MOSFET inversion layer (1MV/cm). Note, energy level splitting from inversion layer confinement is larger than strained.

2.2 Strain Enhanced Hole Mobility

In a MOSFET, the 2-D surface confinement in the inversion layer also shifts the valence

bands and the conduction valleys[11, 43]. Whether the confinement-induced shift adds to or

reduces (cancels) the strain-induced splitting simply depends on the magnitude of the out-of-

plane masses (valence-band splitting is more complicated but this simple model captures the

essential physics). Bands or valleys with a “light” out of plane mass will shift more in energy

27

relative to bands with a “heavy” mass (similar to the increasing ground state energy of a quantum

well as the particle mass decreases). Hence, when the top most occupied band (or valley) has a

lower out-of plane mass compared to the next occupied band, the splitting is reduced or lost with

surface confinement. Fig. 2-4 pictorially shows the valence-band energy-level shift with

confinement for both uniaxial and biaxial stress. Etop represents the top band with large out-of-

plane mass for uniaxial stress and small for biaxial stress (relative to the second band with

masses given in Fig. 2-2). Hence, the top band will have a small shift in energy due to

confinement for uniaxial stress but large shift for biaxial stress. Esecond represents the second band.

As seen in Fig. 2-4, the stress-induced band splitting (Etop − Ebottom) increases for uniaxial stress

but decreases for biaxial tensile stress. Thus, although strain favors occupation of the top band

for both types of stresses, confinement favors occupation of the top band for uniaxial

compressive stress and the second band for biaxial tensile stress. The net band splitting from

strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial

tensile stress. The competing effects of strain and surface confinement on the band splitting is the

reason for the loss in mobility enhancement in biaxially strained-silicon p-MOSFETs at high

electric fields. The undesirable light out of-plane mass created by biaxial tensile stress occurs in

other material systems, such as Ge and III-V materials, and presents a fundamental problem in

using this type of strain in inversion layer MOSFETs (dominant device type due to superior

scaling properties).

To date, unlike biaxial stress [6], limited data exist for the maximum mobility possible for

uniaxial stress. We used a set of scattering parameters that fit the experimental data for hole

mobility enhancement under biaxial tensile stress[11]. The calculations include acoustic and

optical phonon and surface roughness scattering. This set of scattering parameters shows that the

28

dominant mechanism responsible for biaxial tensile-stress mobility enhancement (at large stress)

is reduced optical phonon scattering. Acoustic phonon scattering is only slightly altered due to

the changes in the density of states. Surface roughness scattering is slightly changed by stress but

uncertainty exists in the literature[11, 44, 45] and more work is needed especially for the (110)

substrate. The calculations for biaxial stress are consistent with the previous work [11], although

in this work, Schrödinger’s and Poisson’s equations are solved self-consistently. The model fit to

the biaxial tensile-stress experimental data is shown in Fig. 2-5.

Figure 2-4. Valence energy band splitting calculated using 3 different models versus inversion charge density for longitudinal compression and biaxial tension stress. Note all models show the net band splitting from strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress.

Using the same scattering parameters, mobility enhancement for uniaxial stress on (001)

and (110) wafers is calculated, as shown in Fig. 2-5, and compared to uniaxial stress data from

from three references[6, 24, 46]. The mobility calculations use the full sixband subband structure

29

and Kubo–Greenwood linearization of the Boltzmann equation[16]. Where data exist (0 to ∼

600 MPa for uniaxial stress), the model shows good agreement. The maximum predicted Si

inversion-layer hole mobility enhancement is estimated to be ∼ 4 times higher for uniaxial stress

on (100) wafer and ∼ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a

(110) wafer. The larger maximum mobility enhancement on a (001) wafer results from the high

density of states in the top band, as discussed previously but scattering differences also play a

role. Scattering differences for various substrate orientations and stresses should be expected as

captured in analytical scattering expressions.

First for acoustic phonon in the two dimensional inversion layer, the scattering time acτ is

expressed as [11, 44, 45, 47]

)(1 223

22D

DOSl

BD

DOSmnac

ac

mu

TkmbD∝=

ρτ h (2-4)

where eVDac 1.3= [48] is the acoustic deformation potential constant of the valence band, DDOSm2

is the density-of-state effective mass, ρ is the density, and lu is the longitudinal sound velocity.

The constant ( ) ( )zzdzb nk

w mkmn

vv ψψ ⋅= ∫0 is the form factor which defines the transition from

initial state m to final state n, and mmb2

represents the effective well width for the m-th subband.

Since the acoustic phonon energy is very small compared to the subband splitting, the acoustic

phonon scattering mainly occurs via intraband scattering. Thus, stress-induced band splitting

only weakly affects the acoustic phonon scattering time[13, 49]. As seen from Eq. 2-4, an

increased density-of-states will decrease the acoustic phonon scattering time which is

proportional to DDOSm2 . For uniaxial stress on a (100) wafer with a high density of states in the top

30

band, this slight negative effect on mobility (at least for uniaxial stress on (001) wafer) is offset

by the high hole density in the top band having a light conductivity mass in the channel direction.

Also, a large out-of-plane mass increases the acoustic phonon scattering time (decreases

scattering rate) since it decreases the effective well width (important for the high initial mobility

on (110) wafer).

Second, the optical phonon scattering time opτ is [13, 45, 47, 49]

( )( ) ( ) ( )

( ) ]1

11

11

[2

12

0

22

εε

εε

ρωτ fEkf

Nf

EkfN

Dbm Bp

Bq

opmnD

DOS

op −Δ−Θ−−

×++−

Δ−Θ+−×=

h (2-5)

where EΔ is the band splitting energy, cmeVDop /105.10 8×= [50] is the optical deformation

potential constant of the valence band, ( )εf is Fermi-Dirac distribution function at energy ε ,

K735=Θ is the Debye temperature and meVk B 630 ==Θ ωh is the optical phonon energy[47],

and ( )[ ] ( )[ ] 110 1/exp1/exp −− −Θ=−= TTkN Bq ωh is the number of phonons from Bose-Einstein

statistics. Hole intervalley scattering is not significantly reduced for stress < 1GPa since the

band splitting is less than the optical phonon energy (60meV). Band splitting greater than

60meV (stress > 1GPa) is necessary to appreciably suppress intervalley phonon scattering. Also,

the correlation between the topmost two subbands, mnb under uniaxial stress is smaller due to the

higher band splitting (strain and confinement being additive) and, therefore, the scattering rate is

less than that for biaxially stressed devices. Furthermore with the high out-of-plane mass

causing larger subband splitting, the interband optical phonon scattering rate is less on (110) vs.

(001) devices.

Third, the surface roughness scattering relaxation time srτ [11, 45] can be expressed as

( ) ( )( ) θθπτ

πdqS

mEq DDOSeff

sr∫ −=

2

03

222

cos12

1h

(2-6)

31

where effE is the transverse effective electric field in the inversion layer and ( )( )322

22

2/1 LqLqS

+

Δ=

π

is the power spectrum of the roughness at the interface. L is the correlation length ( nmL 6.2= )

and is the average step height ( nm4.0=Δ ). Differences in srτ for various stresses and substrates

result from changes in the density-of-states and location of the inversion layer charge from the

SiO2 interface. There is also a fair amount of uncertainly in surface roughness scattering

particularly on a (110) wafer since the commonly used universal mobility vs. effective oxide

field effE applies only to the (100) substrate[51, 52]. However, one can conclude since the

effective well width depends heavily on the out-of-plane effective mass for each subband, the top

subband for a (110) devices having a very large out-of-plane effective mass (see Fig. 2-2), will

lead to carriers significantly closer to the interface and greater surface roughness scattering.

Figure 2-5. Calculated and experimental data for longitudinal compressive and biaxial tensile stress enhanced mobility vs. stress (Biaxial stress= σX+σY). Note, the maximum predicted Si inversion layer hole mobility enhancement is estimated to be ~4 times higher for uniaxial stress on (100) wafer and ~2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a (110) wafer.

32

CHAPTER 3 STRAIN EFFECTS ON GATE LEAKAGE CURRENTS OF GERMANIUM (Ge) MOS

DEVICES

3.1 N-Type Metal-Oxide-Semiconductor Field Effect Transistors

3.1.1 Ge Conduction Band Edge Shift and Splitting

Strain-induced energy shift and splitting alters the gate tunneling current. The Ge

conduction band minima are located at the equivalent gamma (L) points[53]. Fig. 3-1 shows the

conduction band constant energy ellipsoids around the L point. Since the centers of the

diagonally opposite half ellipsoids are one wave vector apart, the 8 half ellipsoids can be

combined into four equivalent full ellipsoids( ]111[],111[],111[],111[ ).[54] Due to the major

axis along the Λ or [111] direction, uniaxial stress along [100] shifts but does not split the 4

ellipsoids, while splitting occurs for stress along [110], as shown in Fig. 3-2(b) and (c)[55]. Fig.

3-2(a) shows a schematic drawing of the direct tunneling process from the Λ sub-bands (EΛ) in

the inversion layer for uniaxial tensile stress. The strain-induced shift of the conduction band

edge is given by [2, 56]

)())(()(∧∧

⋅⋅Ξ+Ξ=Δ kkTrE ijuijdiC εεσ (3-1)

where dΞ and uΞ are the dilation and shear deformation potential constants of the conduction

band, respectively, and i denotes the various valleys. Tr(εij) is the trace of the strain tensor

( ijε )[57, 58] and ∧

k andσ are a unit vector in reciprocal space and applied stress, respectively. In

Fig. 3-2(b), stress along [100] causes a hydrostatic conduction band edge shift ( HydroEΔ )

resulting in an altered HfO2/Ge conduction band offset. The hydrostatic strain-induced

conduction band edge shift can be expressed in terms of the deformation potentials [53] and is

given by

33

)()31()()( ijudij

HydroHydro TrTrE εεσ Ξ+Ξ=Ξ=Δ (3-2)

where HydroΞ is the hydrostatic deformation potential constant. Unlike stress along [100], stress

along [110] leads to band splitting between the (110) plane and )101( plane ellipsoids. The band

splitting of each conduction band edge is given by [55]

><Λ Ξ+=Δ 11044)110( 61)( σσ u

Shear SE (3-3)

><Λ Ξ−=Δ 11044)101( 61)( σσ u

Shear SE (3-4)

where σ<110> is the uniaxial stress along [110] direction (positive for tensile stress) and S44 is the

elastic compliance constant. A schematic drawing of the [110] stress effect on EΛ is shown in

Fig. 3-2(c).

Figure 3-1. Conduction-band constant energy ellipsoids are centered at the L point, and the major axis of eight half ellipsoids are along Λ or [111] direction. Out-of-plane effective mass and Eeff are defined along [001] direction.[54, 59] Note half of ellipsoids belong to (110) plane while the rest of ellipsoids belong to )101( plane.

34

Figure 3-2. Schematic band diagrams for direct electron tunneling from inversion layer in Ge MOS device. (a) Conduction band offset between HfO2 and Ge is from reference.[59] (b) Stress along [100] raises Λ energy level resulting from hydrostatic strain-induced energy level shift (∆EHydro). (c) Stress along [110] causes shear strain-induced energy level splitting ( ShearEΛΔ ) between (110) plane Λ valley [ )110(Λ ] and )101(Λ . )110(Λ energy level is raised while )101(Λ energy level is lowered. Note ∆EHydro is additive for ShearE )110(ΛΔ .

3.1.2 Theoretical Model

From the change in the stress altered tunneling current, the Ge deformation potential can

be extracted[18]. The electron direct tunneling current density (IG) can be expressed in terms of

the electron charge density ( in ) and lifetime ( iτ ) of each energy sub-band in the quantization

layer, which are functions of stress,

∑=i i

iG

nqI)()()(

στσσ (3-5)

35

where the subscript i denotes each sub-band belonging to the Λ valley of Ge. Above the

threshold voltage, most electrons occupy each ground state for the )110(Λ and )101(−

Λ valleys.

The relative change of gate tunneling current due to the applied stress can be expressed as [18,

60]

)0()(

)0()0(

)()0(

)0()(

)0()0()(

)110(

)110(

)101(

)101(

)110(

)110(

Λ

Λ

Λ

Λ

Λ

Λ Δ−

Δ−

Δ≅

Δ

−

−

τστ

τ

στσσ CBnn

AII

G

G (3-6)

where )0(/)0()0(/)0(

)0(/)0(1)0(

)110()101(

)110()101(

)110()101(

ΛΛ

ΛΛ

ΛΛ

−−

−

+

+−=

ττ

ττ

nnA

)0(/)0()0(/)0(

)0(/)0()0(

)110()101(

)110()101(

)110()101(

ΛΛ

ΛΛ

ΛΛ

−−

−

+=

ττnn

nnB

)0(/)0()0(/)0(

)0(/)0()0(

)101()110(

)101()110(

)101()110(

−−

−

ΛΛ

ΛΛ

ΛΛ

+=

ττnn

nnC

The charge density of electrons in the sub-bands is calculated from the self-consistent solution of

the Schrödinger and Poisson equations[61]. The effective mass approximation is used for Ge[54,

62]. For a (100) surface oriented Ge device, the out-of-plane effective mass ( *nm ) can be defined

as )2/(3 tltl mmmm + , where lm and tm are the longitudinal and transverse effective masses of the

Λ valley, respectively ( 064.1 mml = and 008.0 mmt = )[54]. Once the basic Hamiltonian has

been identified, the electron charge density is calculated by summing the contributions of each

sub-band in the Λ valley. The electron charge density of each sub-band can be described by [63]

))exp(1ln()( *2 kT

EEgmkTn iF

di−

+=hπ

(3-7)

36

where k is the Boltzmann constant, T is room temperature, 300K, EF is the Fermi energy, *dm is

the density of state electron effective mass in the Λ valley ( *dm =0.3 0m ) [59], and Ei and g are

the energy level of the ith sub-band and the degeneracy of the Λ valley, respectively. Based on

the finite difference method [61], the self consistent solution provides the charge density and the

corresponding sub-band energy levels. The tunneling lifetime of the electron in each sub-band is

approximated by [64]

∫ −

=dxxEEm

ET

Cin

i

i )](/[2

)(1*τ

(3-8)

where EC(x) is the edge of the conduction band of Ge and T(Ei) is the transmission probability

calculated with a modified WKB approximation[63, 64]. An E(k) dispersion proposed by Franz,

which is consistent with two bands separated by an energy gap ( 2HfOgE =5.8eV), is used for the E-

k dependence of HfO2 [65, 66] and an oxide effective mass, OXm =0.18 0m is used for this

calculation[59]. The validity of the WKB approximation for high-k dielectrics has been shown

elsewhere[62].

3.1.3 Experimental Set-Up and Results

Four-point bending is used to apply uniaxial stress along the [100] and [110] directions on

(100) surface oriented Ge MOS samples.[13] The Ge MOS devices consist of TiN metal gate on

top of 3.0 nm HfO2 gate dielectric on p-well substrate. Large area 10-4 cm2 Ge MOS devices are

used to eliminate the fringe leakage components. The electron gate tunneling current from the Ge

substrate to gate is measured under inversion with positive gate bias and substrate grounded

using a Keithley 4200 DC characterization system.

37

Fig. 3-3 shows the [100] stress-altered electron gate tunneling current for different gate

biases. The tunneling currents increase with applied tensile stress. Unlike Si, stress along [100]

does not result in any change in the average conductivity effective mass via electron

repopulation—the inset shows the tunneling barrier height reduced by HydroEΔ .

Fig. 3-4 plots the change in the electron gate tunneling current for mechanical stress along

[110]. The change in the tunneling current for stress along [110] is slightly smaller than for stress

along [100].

It is instructive to compare [110] tensile stress altered tunneling currents for (100) surface

oriented Si and Ge n-MOS devices which is shown in Fig. 3-5. The trend for Si MOS devices

can be found in several recent publications all showing similar results[19, 67]. An opposite

stress dependence is observed with an increase in tunneling current for Ge and a decrease for Si.

The key difference in the gate tunneling mechanism between Si and Ge devices is due to the

position of conduction band minimum (X for Si and L for Ge)[54].

To understand the difference, strain effects on the conduction sub-band structure of Si and

Ge are illustrated in Fig. 3-6. For Si, due to different out-of-plane effective masses of ∆2 valley

(0.92m0) and ∆4 valley (0.19m0), electron repopulation between these two valleys plays an

important role in strain-altered gate leakage current[18]. The decrease in the gate tunneling

current of Si results from repopulation into the ∆2 sub-band with a larger out-of-plane effective

mass. In addition, the ∆2 sub-band shift leads to an increased barrier height. In Ge, the out-of-

plane effective masses of the 8-fold degenerate Λ valleys are the same (0.12m0)[54].

Since )110(Λ and )101(−

Λ have the same out-of-plane effective mass and barrier height (without

the applied stress), )0()101(

−Λ

τ is identical to )0()110(Λτ , resulting in A(0) in (6) equal to zero. The

38

degeneracy of )110(Λ and )101(−

Λ also results in )0()101(

−Λ

n = )0()110(Λn and B(0) = C(0) in (3-6).

Thus for Ge, )0(/)( τστΔ (second and third terms in (3-6)) is the dominant effect which is

altered via strain by changes in the HfO2 to Ge barrier height, as shown in Fig. 3-2(c). At lower

gate bias, the relative change ofτ as a function of stress is larger, based on (3-8). Therefore, the

relative change of stress altered gate leakage current at lower gate bias is larger than at higher

gate bias, consistent with the experimental data in Fig. 3-3 and 3-4. Also, we observe, in Fig. 3-5,

the increase of the gate leakage current in Ge device is approximately 3 times smaller than the

decrease in the Si device.

Figure 3-3. The [100] tensile stress-altered gate tunneling current for Ge MOS device under different gate biases. Current is increased due to reduced barrier height resulting from ∆EHydro. The inset represents schematic band diagram of sub-band in inversion with no stress and tensile stress along [100].

39

Figure 3-4. [110] tensile stress-altered gate tunneling current of Ge MOS device under different gate biases. Current is increased due to reduced barrier height of electrons in

)110(Λ energy level. The inset shows schematic band diagram with strain-induced sub-band splitting between )110(Λ and )101(Λ sub-bands.

Figure 3-5. The [110] tensile stress-altered electron gate tunneling current of Ge and Si devices at inversion charge of 1013/cm2, where 1.2 V and 0.6 V gate biases are applied for Si and Ge MOS devices, respectively.[68] Si data are from reference [19] (measured from n-MOSFETs with N+ poly gate and SiO2 dielectric). Note that strain-altered current is increased in Ge while decreased in Si due to the different position of conduction band minimum (X for Si and L for Ge).[54]

40

Figure 3-6. Schematic band diagrams for [110] tensile stress effects on electron gate tunneling in (a) Si and (b) Ge devices, respectively. A decrease in tunneling current for Si device is induced by 1) barrier height enhancement of mostly populated ∆2 and 2) electron repopulation into ∆2 sub-bands, which has higher out-of-plane effective mass(0.92m0), while only barrier height lowering of Λ(110) contributes to an increase of tunneling current of Ge MOS device.

3.1.4 Extraction of Conduction Band Deformation Potentials

In this section, the conduction band deformation potentials of Ge are extracted from the

strain-altered gate tunneling current. Since stress along [100] only causes a HydroEΔ shift and no

shear band splitting on the Λ valley structure, HydroEΔ can be determined from the data in Fig. 3-

3.

To extract HydroΞ and capture the change in the tunneling current under the applied stress in

the full range of gate voltages, Fig. 3-7 shows the change of slope in Fig. 3-3 or

σσ dIId GG /)]0(/)([Δ versus applied gate bias. HydroΞ is used to fit the experimentally measured

data[2, 53]. To illustrate the goodness of the model fit, maximum deviation curves are plotted in

which HydroΞ ranges from 1.2 to 1.5 eV. The model fits well with the data over the range of gate

41

bias from 0.5V to 1.1V. The same procedure is employed for stress along [110] to determine the

two deformation potentials of Ξd and Ξu. The slope of Fig. 3-4 was extracted and compared with

fitting models over the entire gate bias range (0.5~1.1 V) in Fig. 3-8. The obtained values of

deformation potential constants (Ξd and Ξu) are compared with hydrostatic deformation potential

constants ( HydroΞ ) from stress along [100], based on udHydro Ξ+Ξ=Ξ

31 [53]. The best fitting

values of Ξd and Ξu in Fig. 3-8 are in good agreement with HydroΞ in Fig. 3-7. The obtained

deformation potentials ( 3.03.4 ±−=Ξ d and eVu 5.05.16 ±=Ξ ) listed in Table 3-1 are close to

the theoretical values by Fischetti et al. ( 43.4−=Ξ d and eVu 8.16=Ξ )[17].

Figure 3-7. Change in slopes ( σσ dIId GG /)]0(/)([Δ ) versus gate voltage with 95% confidence error bars for tensile stress along [100]. Best fits (① and ②) for the entire data set occur for Ξ Hydro = 1.3 and 1.4 eV. Maximum deviations (③ and ④) from the data occur for Ξ Hydro = 1.2 and 1.5 eV.

42

Figure 3-8. Change in slopes ( σσ dIId GG /)]0(/)([Δ ) versus gate voltage with 95% confidence error bars for tensile stress along [110]. Best fits (②, ③, and ④) for the entire data set occur for Ξ d= -4.2 to -4.4 and Ξ u=16.5 to 16.8 eV. Maximum deviations (① and ⑤) from the data set occur for Ξ d= -4.1 and -4.5 and Ξ u=17.0 and 16.0 eV, respectively.

Table 3-1. Dilation (Ξd) and shear (Ξu) deformation potentials extracted from gate tunneling current of Ge MOS device under tensile stress along [100] and [110]. Comparison is made with previous theoretical and experimental results.[17, 53, 55, 69, 70] All quantities are in eV.

3.1.5 Summary

In summary, measurement of the electron gate leakage currents under two different

mechanical stress conditions provides a method to extract the Ge conduction band deformation

potentials. For uniaxial tensile stress along [110] and [100], the change in gate leakage current

for Ge is measured to be 3 times smaller than that of Si n-MOS device and opposite in sign. This

reverse behavior occurs because tensile stress for Si causes electron repopulation into Δ2

43

increasing the out-of-plane effective mass while, in Ge, a reduced tunneling barrier is the

dominant mechanism, resulting from the hydrostatic shift of the conduction band edge. Although

the hydrostatic shift of Si is larger than that of Ge, its contribution to the strain-altered gate

leakage current change in Si is not as critical as in Ge due to the primary role of electron

repopulation via shear strain-induced band splitting in Si.

3.2 P-type metal-oxide-semiconductor field effect transistors

3.2.1 Experimental Set-Up

Three different kinds of samples are used in this work: (1) Ge <110> channel/(100) surface

p-MOSFETs with TiN metal gate and 3.0 nm HfO2/interlayer (IL) stacked dielectric fabricated

on n-type Ge substrate, (2) Si <110> channel/(100) surface p-MOSFETs with p+ poly-Si gate

and 1.3 nm SiO2 fabricated on n-well, and (3) Si MOS capacitors with TaN gate and 2.5 nm SiO2

fabricated on p-type Si substrate.

Conventional carrier separation method is used to measure the electron and hole tunneling

currents for the Ge and Si p-MOSFETs[71-73]. Fig. 3-9 is a schematic illustration of carrier

separation and 4-point wafer bending. The electron (from the gate) and hole (from the substrate)

tunneling currents are measured with source and drain physically tied to ground and the gate

negatively biased. Mechanical uniaxial stress is applied longitudinal to the <110> channels of Ge

and Si MOSFETs. The hole and electron tunneling currents are measured using a Keithley 4200

dc characterization system. Devices with different areas are measured and the current density

exhibits no area dependence, which indicates a negligible edge tunneling effect[74]. To measure

the magnitude of metal gate work-function shift under mechanical stress, Si MOS capacitors

have been used for C-V measurements with HP 4294 to measure flat band voltage shift (∆VFB).

44

Figure 3-9. Carrier separation measurement of p-MOSFET and 4-point wafer bending. The gate tunneling current (IG) can be separated into electrons (IG,electron)and holes (IG,hole) tunneling from gate and substrate, respectively.[75]

3.2.2 Stress Altered Hole Tunneling Currents of Ge and Si p-MOSFETs

Fig. 3-10(a) shows the carrier separation for Ge and Fig. 3-10(b) for Si p-MOSFETs. For

both type of devices, the gate current, IG, is nearly identical with the source/drain current, IS/D,

showing hole tunneling current from inversion layer is the dominant mechanism consistent with

previous studies[64, 76, 77]. In Ge device, IS/D is lower and the portion of ISUB in IG is larger than

that in the Si device due to 1) HfO2 dielectric with larger equivalent oxide thickness and 2) TiN

metal electrode with free electrons[73, 77].

Fig. 3-11 shows the relative hole gate tunneling current change in Ge and Si p-MOSFET as

a function of applied external mechanical stress. Theoretical calculation for the stress altered

hole tunneling current, based on the self-consistent solution to the Poisson and Schrödinger’s

equation for Si and Ge, are also shown in Fig. 3-11[20]. A six band k•p approximation is used

for the calculation of charge density and out-of-plane effective mass[42]. The hole tunneling

probability, based on a WKB approximation,[64, 65] is used to fit the experimental data. The

45

dominant tunneling mechanism for high-k dielectric can be either trap-assisted tunneling (Poole-

Frenkel (PF) emission) or classical tunneling (direct or FN tunneling), depending on the

thickness of dielectric and the quality of the high-k/substrate interface and bulk dielectric[62, 67,

78]. In our samples, we determine the dominant mechanism for gate tunneling current to be

classical tunneling (direct or FN tunneling), based on two reasons: 1) PF plot is not linear (not

shown)[79] and 2) hole tunneling occurs through thin higher band gap interlayer (PF emission is

dominant for the device with thick dielectric)[67]. The strain altered hole tunneling current for

both Ge and Si p-MOSFETs increase with stress and the relative change in Ge is approximately

4 times larger than that in Si.

The measured data can be understood from strain altered out-of-plane effective mass and

hole repopulation between the top two sub-bands (E1 and E2)[80]. Fig. 3-12 shows a schematic

drawing of the hole tunneling process from E1 and E2 and the strain induced sub-band energy

shift. For both Ge and Si, the strain altered out-of-plane hole effective masses of E1 and E2 are

observed to be fairly constant at the Γ point for stress < ~200 MPa and listed in Fig. 3-12(c)[13].

The band splitting at low stress and moderate to high gate bias is set by confinement and with E1

having larger strain altered out-of-plane effective mass becomes the top band[80]. Applied

tensile stress causes the E1 to E2 band splitting to decrease resulting in hole repopulation from E1

to E2, as shown in Fig. 3-12(b)[19, 20]. For tensile stress, the hole tunneling current

enhancements of both Ge and Si devices result from hole repopulation into E2, which has a

smaller tunneling barrier height ( 1,2, BB φφ < ) and out-of-plane effective mass ( zE

zE mm

12< ).

Compared to Si, the larger increase in strain altered hole tunneling current of Ge can be

explained by larger 1) stress induced valence band edge splitting and 2) change in hole tunneling

attempt frequency.

46

The hole repopulation can be quantified from the valence band edge splitting (ΔEv) as a

function of stress[81]. Fig. 3-13 shows the valence band edge splitting in Ge and Si under no

confinement, based on ΔEV as follows: [55]

]110[

2/12

442

12112

V )32

(3)(21E σ⎥

⎦

⎤⎢⎣

⎡+−=Δ SdSSb (3-9)

where σ[110] is the applied longitudinal stress, Sij is the elastic compliance constants and b and d

are deformation potentials of valence band from Ref. [17]. Note that ΔEv of Ge is 1.5 times

larger than that of Si, causing more hole repopulation in Ge.

Fig. 3-14 plots the hole charge density in the top three sub-bands (E1, E2, and E3) as a

function of stress for a) Ge and b) Si, respectively. Note in this calculation, since the total charge

density is approximately constant with applied stress, we use ΔN1+ΔN2+ΔN3 = 0, where Ni is

hole charge density of each sub-band[20]. Since the 2D density of states of both Si and Ge do not

change significantly at low stress (<200MPa)[82], hole repopulation from E1 to E2 mainly results

from valence band edge splitting as seen in Fig. 3-13, leading to the larger increase in the hole

tunneling of Ge, relative to Si.

The inversion-layer hole attempt frequency on gate dielectric barrier is also different for E1

and E2[19]. Due to the larger mass ratio of Ge (E1/E2=0.12/0.05), compared to that of Si

(0.26/0.21), the relative change of stress altered hole tunneling attempt frequency in Ge is larger,

resulting in a larger increase in hole tunneling current for Ge.

47

Figure 3-10. Carrier separation measurement of a) Source/drain (IS/D) and substrate tunneling current (ISUB) as a function of gate voltage (VG) for Ge p-MOSFET. b) IS/D and ISUB as a function of VG for Si p-MOSFET.

48

Figure 3-11. Relative change in IS/D of Si and Ge p-MOSFET as a function of stress. Symbols and lines are measured data and modeling, respectively. The magnitude of hole tunneling current change in Ge is approximately 4 times larger than that in Si.

Figure 3-12. Schematic band diagram for the hole gate tunneling current in a p-MOSFET on a (100) wafer. a) each subband has different tunneling barrier height. b) E1 and E2 sub-bands shift under stress results in hole repopulation into E2 sub-band, which has lower tunneling barrier height and smaller out-of-plane effective mass. c) Strain altered out-of-plane effective mass for each sub-band is listed in table.

49

Figure 3-13. Valence band edge splitting of Ge and Si under tensile stress along [110] (not including confinement). Ge has larger valence band edge splitting than Si.

50

Figure 3-14. Charge density versus applied stress for the top (E1), bottom (E2), and third sub-bands (E3) at an inversion charge density of 3.5x1013/cm2 for a) Ge and b) Si, respectively. Strain altered out-of-plane effective mass of each sub-band is denoted (e.g., 0.12 m0). Note, due to larger valence band edge splitting of Ge, hole repopulation in Ge is more than in Si.

51

3.2.3 Stress Altered Electron Tunneling Currents From Metal Gate

The carrier separation technique also allows the electron tunneling current via ISUB to be

measured which is altered by strain due to a shift in the band offset between the gate electrode

and dielectric [83]. Fig. 3-15 shows the relative change of ISUB as a function of stress for the Ge

channel MOSFET. Due to the decreased TiN gate work-function with stress, ISUB increases,

showing that the work-function of metal gate decreases under tensile stress.

To quantify the metal work-function shift, ∆VFB, where OX

OXMSFB C

QV −= φ , is measured using

capacitance-voltage measurement. Since the permittivity of SiO2, the fixed oxide charge and the

interface trapped charge does not change appreciably with applied stress [84] and the Fermi

energy level of the silicon substrate only changes up to ~1mV at 200 MPa [85, 86], the metal

work-function shift ( MφΔ ) can be approximated from ∆VFB. Fig. 3-16 shows the C-V

characteristics of MOS capacitor with TaN gate and VFB is measured to increases/decreases with

compressive/tensile stress.

Fig. 3-17 plots MφΔ of the TaN gate as a function of stress, obtained from Fig. 3-16(b) and

compared to the work-function shifts of bulk metals[87, 88]. The stress altered work-function in

TaN gate follows a similar trend as that in bulk metal of Al and Cu. The TaN work-function

increases/decreases by approximately 4 mV at compressive/tensile stress of 200 MPa.

The relative change in the stress altered electron gate tunneling current from the TaN gate

to substrate is measured and plotted in Fig. 3-18[89]. The data is extracted at the gate bias of -1.7

V. The gate tunneling current increases/decreases with tensile/compressive stress. An analytical

equation based on the electron direct tunneling model is employed to fit experimental data [90,

91].

52

]2

))(2()()2(2exp[4

22/1*

2/32/1*

*22 qEdmdmmm

dqJ b

bhhh

σφσφπ

+−= (3-10)

where d

VVE SFBG Ψ−−=

222222 )()/(/ FBGOXSiAFBGOXSiAFBGS VVdqNVVdqNVV −−+−−+−=Ψ εεεε

where d is the oxide thickness and )5.0(* mm = [92] and E is the effective electron mass

and the electric field in the SiO2 layer, respectively. Also, m , SΨ and )(σφb is the electron mass

in the free space, the substrate bend bending and the effective barrier height as a function of

applied stress, respectively. We used the effective oxide thickness, )08.0(* nmdd =−= δδ

instead of the physical thickness due to the surface roughness or the uncertainty of electrical

measurement for the determination of the oxide thickness[90]. For modeling, )(σφb is estimated

with the linear fit of MφΔ in Fig.3-17. Our calculation shows good agreement with measured

data in Fig. 3-18. The relative change in electron tunneling current increases/decreases up to

1.0% under 200 MPa of tensile/compressive stress, resulting from the decreased/increased metal

gate work-function by 4meV.

53

Figure 3-15. Relative change in ISUB of Ge p-MOSFET as a function of stress at gate bias of -2.8V. Due to decreased work-function of TiN gate, electron gate tunneling current from TiN gate increases up to ~4% with 100MPa of stress. The inset shows the decreased tunneling barrier height via strain by the decreased work-function of TiN gate.

Figure 3-16. The VFB shift under uniaxial stress. (a) C-V curve of MOS capacitor, measured at 100KHz. VFB is extracted from CFB.[93] (b) VFB shift as a function of tensile and compressive stress. VFB decreases /increases with tension/compression.

54

Figure 3-17. Work-function shifts of TaN, bulk Al and bulk Cu as a function of stress[87]. Work-functions of three different metal increase/decrease with compressive/tensile stress. Line is the linear fit of extracted data.

Figure 3-18. Relative changes in gate tunneling current of MOS capacitor with TaN gate as a function of stress. Symbols and lines are measured data and modeling, respectively.

55

3.2.4 Summary

Due to larger 1) stress induced valence band edge splitting and 2) change in hole tunneling

attempt frequency in inversion-layer of Ge under uniaxial tensile stress, the change in stress

altered hole gate tunneling current in Ge is ~4 times larger than that in Si. The work-function of

the metal gate is measured to change with strain and decrease/increase ~20meV for each 1 GPa

of uniaxial tensile/compressive stress.

56

CHAPTER 4 IMPACT OF MECHANICAL STRESS ON DIRECT AND TRAP-ASSISTED GATE

LEAKAGE CURRENTS IN P-TYPE MOS CAPACITORS

4.1 Introduction

State-of-the-art logic devices requires uniaxial stress to enhance transistor performance[80,

94]. Uniaxial stress is also being used in nonvolatile memory (NVM) to improve the retention

time[95-97]. In NVM, trap-assisted gate tunneling current can be a dominate factor in the

retention time[98] and the reliability of the tunneling dielectric[22, 23]. The high electric field

during programming (Fowler-Nordheim tunneling) generates electron traps in the SiO2 dielectric

or at the SiO2/Si interface, resulting in trap-assisted gate tunneling[98].

It has been reported that mechanical stress affects trap generation in MOS devices [99, 100],

but less attention has been paid to mechanical stress-altered trap-assisted gate tunneling

current[67]. In this work, we report for the first time, the effects of uniaxial stress on trap-

assisted gate tunneling current using controlled applied mechanical stress and constant voltage

stress (CVS).

4.2 Experimental Set-Up

Samples used in this work consist of MOS capacitors with TaN metal gate on top of 2.5 nm

SiO2 dielectric fabricated on p-type (100) Si surface substrate. Large area 105 μm2 devices are

used to eliminate the fringe leakage components. The electric damage is created by -4.0 V of

gate voltage for 50 seconds[101]. By monitoring the gate leakage current as a function of time at

the fixed gate voltage, the CVS condition is adopted, where applied gate voltage generates traps,

but does not cause dielectric breakdown. Due to the generated traps during CVS, trap-assisted

tunneling becomes a dominant gate leakage mechanism, resulting in an increase in gate leakage

current after CVS, compared to one before CVS[23]. Next, uniaxial 4-point external mechanical

stress is apply along [110] direction while changes in the gate to substrate electron tunneling

57

current (negative gate bias) and electron gate tunneling from substrate to gate (positive gate bias)

are measured[13]. The maximum gate voltage used during the gate leakage measurement (VG =

±1.7 V) is limited below the magnitude of the gate voltage in CVS condition (VG = -4 V) to

ensure minimal gate oxide damage during this measurement.

4.3 Results and Discussions

To understand the effects of uniaxial mechanical stress on gate leakage current in samples

before and after CVS, both gate and substrate injections are measured under tensile and

compressive stresses. Figure 4-1 shows the relative change of gate leakage current in samples

before (Fig. 4-1(a)) and after CVS (Fig. 4-1(b)) as a function of mechanical stress. The relative

changes for gate and substrate injections are extracted at the gate voltage of -1.7 V and 0.8 V,

respectively[89]. In samples before CVS where direct electron tunneling is a dominant

mechanism, gate and substrate injections show an opposing dependence on mechanical stress, as

shown in Fig. 4-1(a). Under tensile (compressive) stress, gate injection increases (decreases)

while substrate injection decreases (increases). For sample after CVS where the dominant

leakage current is trap-assisted tunneling current, both gate and substrate injection is increased

under tensile and compressive stresses, as shown in Fig. 4-1(b). Fig. 4-1(b) also shows a larger

slope for the change in gate and substrate injections under compressive stress as compared to

tensile stress.

The effects of mechanical stress on direct and trap-assisted gate leakage currents can be

understood with Fig. 4.2. Fig. 4.2(a) illustrates the impact of mechanical stress on direct gate

tunneling for gate and substrate injections. Under gate injection, applied tensile (compressive)

stress decreases (increases) the tunneling barrier height of electrons from gate to substrate via

TaN gate work function shift, resulting in an increase (decrease) in gate leakage current[102].

58

Under substrate injection, mechanical stress-induced electron repopulation between Δ2 and Δ4

sub-bands in the n-type inversion layer changes the out-of-plane effective mass and tunneling

barrier height of electrons in Δ sub-bands as previously reported [18, 19, 21, 103].

During CVS for thin SiO2 (< 2.5 nm), energetic electrons injected from gate to the Si

substrate breaking dangling bonds in the [111] direction, normally passivated by hydrogen at Pb0

and Pb1 centers at near the SiO2/(100)Si interface [99]. These additional defects increase trap

assisted tunneling currents [98, 101].

For trap-assisted gate tunneling, the detrapping of the SiO2 electron plays a primary role in

gate leakage current [104]. The trap activation energy, Tφ , where TRAPOXCT EE −=φ , determines

the detrapping processes as illustrated in Fig. 4-2(b). Here, OXCE and TRAPE are the conduction

band edge of SiO2 and trap energy level, respectively, and Tφ is a function of applied mechanical

stress (σ) [105].

Uniaxial mechanical stress along [110] direction alters the structure of Pb0 and Pb1 centers,

as illustrated in Fig. 4-3 [99, 106-108]. This affects the stability of interface traps, resulting in a

change in Tφ [108]. In Pb0 center, compressive stress along [110] decreases bond angle Ө1 and

increases the other bond angle Ө2, due to 1) (100) Si substrate surface structure and 2) dangling

bond along [111] direction [99, 106]. For tensile stress along [110], it should have the opposite

effect as that for compressive stress. The Ө decrease, ∆Ө(σ) <0, means an increase in repulsive

force between the dangling bond and at least one of the three back bonds, resulting in the less

stable dangling bond, as described in Fig. 4-3(a) and table [106]. For Pb1 center, the dangling

bond with unstrained Ө (Ө = 45) is known to have minimum energy and either positive or

negative ∆Ө(σ) makes the dangling bond less stable, as shown in Fig. 4-3(b) [109]. Therefore,

both compressive and tensile stresses along [110] cause a decrease in the trap activation energy

59

at Pb0 and Pb1 centers, 0)( <Δ σφT [67, 99, 110], resulting in an increase in trap-assisted gate

leakage current for both gate and substrate injections, as shown in Fig. 4-1(b). It is reported that a

change in SiO2/(100) Si interface trap activation energy under compressive stress is larger than

one under tensile stress [105, 111, 112], matching with our results that the relative change of

trap-assisted gate leakage current under compressive stress is larger than under tensile stress

(observed for both gate and substrate injections in Fig. 4-1(b)).

4.4 Conclusions

Different dependences of gate leakage currents on uniaxial mechanical stress are observed

from direct and trap-assisted gate tunneling currents. The CVS technique is used to generate

traps at SiO2/(100) Si interface and monitor interface trap-assisted gate leakage current in MOS

capacitor with 2.5 nm thin SiO2. Both mechanical tensile and compressive stresses along [110]

increase trap-assisted gate leakage current via the lowering of trap activation energy of Pb0 and

Pb1 centers, showing that uniaxial stress along [110] may not be applicable to improve the gate

leakage of logic devices and the retention time of NVM devices when trap-assisted tunneling is a

dominant mechanism in gate leakage current.

60

Figure 4-1. Relative change of gate leakage currents in MOS devices (a) before constant voltage stress (CVS) and (b) after CVS as a function of applied mechanical stress along [110] direction, respectively.

61

Figure 4-2. Schematic band diagrams for a) direct and b) trap-assisted gate tunneling mechanisms. Key parameters for mechanical stress-altered electron gate tunneling currents before and after CVS are summarized in table.

Figure 4-3. Schematic of SiO2/(100) Si interface structure including Pb0 and Pb1 centers, showing mechanical stress-induced changes in dangling bond angles (Ө) and interface trap activation energy (ΦT).

1999

A. Toda et al. 2005

62

CHAPTER 5 STRAIN INDUCED CHANGES IN GATE LEAKAGE CURRENT AND DIELECTRIC

CONSTANT OF NITRIDED HF-SILICATE DIELECTRIC SILICON MOS CAPACITORS

5.1 Introduction

Hafnium silicate has been extensively studied as a gate dielectric material in advanced

metal oxide semiconductor field effect transistors (MOSFETs) due to a high crystallization

temperature, thermodynamic stability with Si, high permittivity and relatively large band gap

(5.68 eV) [113-116]. Nitrogen incorporated Hf-silicate (HfSiON) has received attention since

HfSiON minimizes interfacial layer formation and reduces boron diffusion from the poly-Si gate

into the channel [117, 118]. Also, recent reports have explained additional advantages of nitrided

Hf-silicate such as increased dielectric constant and improved reliability [119, 120].

Strained silicon technology has been adopted in high-k gate stack MOSFETs, showing

strain can improve mobility similarly for Hf-silicate MOSFETs compared to SiO2 MOSFETs

[82]. However, to date, there is no systematic and quantitative result on the strain altered

dielectric constant and gate leakage current of HfSiON dielectric film. In this work, we report on

the effect of mechanically applied uniaxial stress on the gate leakage current and dielectric

constant of Si MOS capacitors with HfSiON gate dielectric.

5.2 Experimental Procedures

The HfSiOx films are deposited directly on p-type (100) pre-cleaned (1% HF solution and

DI water rinse) 8 inch Si substrates with a resistivity of 3-25 Ωcm using atomic layer deposition

(ALD) at 300oC. The oxidizing agents for TEMAH and Si are O3 and H2O, respectively. HfSiOx

film deposition is followed by nitrogen incorporation by rapid thermal anneal (RTA) at 650 oC in

NH3 ambient for 60 s. MOS capacitors with Pt and Al gate electrode were fabricated using RF

magnetron sputtering. All of the metals were deposited by Ar plasma assisted RF sputtering at a

pressure of 15 mTorr and 150W RF (13.56 MHz) power. For all MOS devices, post metallization

63

annealing (PMA) was carried out in a tube furnace at 400oC in forming gas (10% H2 / 90% N2)

ambient for 30 min. Capacitance-voltage (C-V) and current-voltage (J-V) measurements were

measured with Agilent E4980A and Keithley 4200, respectively, using external mechanical

uniaxial stress along the [110] direction [13]. To extract the frequency-independent device

capacitance value and eliminate the effect of both series and shunt parasitic resistances, a two-

frequency method is adopted [121]. The flat band voltage (VFB) is extracted from the C-V

measurements [122]. To reduce the electrical instability from HfSiON charging [123], a constant

gate voltage (-1V) was applied for 160 s before J-V measurement. This reduces the J-V

instability to less than 0.2% variation.

5.3 Results and Discussions

Figure 5-1 shows the C-V (a) and J-V (b) characteristics of Hf-silicate dielectric MOS

capacitors. In order to verify the gate tunneling conduction mechanism, aluminum (Al) and

platinum (Pt) electrodes are used due to their large bulk work function difference ( Alφ ≈ 4.1 and

Ptφ ≈ 5.8 eV) [124]. The accumulation capacitance values are almost identical (~1.2 × 10-6

F/cm2) resulting in an equivalent oxide thickness of 2.7 nm regardless of the gate electrodes[125].

The nearly identical accumulation capacitance and parallel shift of C-V curves for Pt and Al gate

electrodes indicates that, regardless of gate material, a sharp interface and minimal interaction

between the metal gate and dielectric film are maintained. Due to the difference in the work

function of Pt and Al, a difference in VFB and larger leakage current under negative gate bias is

observed for the Pt devices. The larger leakage current in Pt devices can be explained by the

following: (1) the dominant leakage current mechanism is hole tunneling from the substrate to

gate as opposed to electron tunneling from gate to substrate[126], and 2) a higher built-in oxide

field of the Pt device results from a larger work function as illustrated in the inset of Fig. 5-2.

64

Figure 5-1. The C-V characteristics at 1MHz of the MOS device with Pt and Al gate on nitrided Hf-silicate film (a). The inset shows current density-voltage (J-V) measurements of both devices (b).

Figure 5-2. Poole-Frenkel (ln(J/E) vs E1/2) plot of Pt and Al gate on nitrided Hf-silicate film at 25

oC. Inset in figure shows a schematic band diagram for MOS capacitors with HfSiON dielectric and interlayer and metal gates (Pt and Al) under negative gate bias.

65

Fig. 5-2 shows the Poole-Frenkel (PF) plot for both metal electrodes with HfSiON gate

dielectric. The slope of PF plot can be expressed as

0)(

)/ln()(εσπε

σr

qkTq

EEJSlope =

ΔΔ

= (5-1)

where k, T, )(σε r and 0ε are the Boltzmann constant, temperature, high frequency dielectric

constant of the insulator under external stress, and vacuum permittivity, respectively. The high

frequency dielectric constant without external stress extracted from the slope of the PF plot is 4.9.

The refractive index, n, given by the square root of the high frequency dielectric constant,[127,

128] is found to be 2.23, showing that the extracted dielectric constant is within the range of

refractive indices reported for HfSiON films (1.8~2.4)[129].

The normalized change in strain-altered gate leakage currents for Al and Pt HfSiON

MOS capacitor are shown in Fig. 5-3. Regardless of electrodes, an increase in normalized

leakage current is observed for both tensile and compressive stresses. Recently, Choi et al

suggested that a decrease in trap activation energy results in an increase in trap-assisted gate

leakage current under mechanical stress[130]. Based on a decrease in hole trap activation energy

under mechanical stress [131] and a dominant hole tunneling gate leakage mechanism under

negative gate bias in high-k dielectric[132], an increase in PF emission-based gate leakage may

result from a decrease in hole trap activation energy in high-k dielectric under both tensile and

compressive stresses.

The measured normalized change in the strain altered dielectric constant of HfSiON,

HfSiOx, and HfO2 are shown in Fig. 5-4. Unlike HfO2 and HfSiOx, the dielectric constant of

HfSiON is observed to increase with both tensile and compressive stresses, as determined using

two separate techniques, C-V curve and slope extraction from the PF plot shown in Fig. 5-2.

66

We propose that the incorporated nitrogen in Hf-silicate film may be the origin of the

strain-induced dielectric constant change. The nitrogen incorporation creates a N p band above

the valence band edge of HfSiO[119]. The N p band splitting by applied mechanical stress may

lead to band gap narrowing of HfSiON, increasing the electronic transition from the N p band to

the conduction band[133, 134]. This band gap narrowing should increase the HfSiON dielectric

constant[119].

Figure 5-3. Changes in gate leakage current of Si MOS capacitors with HfSiON dielectric as a function of applied stress.

67

Figure 5-4. Changes in dielectric constant of HfSiON, HfSiOx and HfO2, measured from C-V and PF slope change.

To date, there have been no reports on strain altering the dielectric constant of SiON

which is commonly used for gate dielectrics in advance logic technologies. One explanation is

that for SiON, nitrogen incorporation into SiO2 primarily occurs at the SiO2/Si interface. XPS

measurement results show no observed band gap narrowing of SiO2 due to N p band formation

near valence band edge of SiO2[135]. Thus, the dielectric constant of SiON is not expected to

change significantly for mechanical stress range (<100 MPa) used in this work.

5.4 Conclusions

The impact of four point wafer bending uniaxial stress on gate leakage and gate dielectric

constant of Si MOS capacitor with HfSiON has been studied. A measured increase in strain-

altered gate leakage is attributed to a decrease in hole trap activation energy in HfSiON. An

increase in HfSiON dielectric constant is also observed under both tensile and compressive

68

stresses. Thus, in additional to strain enhanced channel mobility, strained HfSiON may provide a

slight additional improvement via an increase in oxide capacitance.

69

CHAPTER 6 IMPACT OF DIFFERENT GATE STACKS AND CHANNEL MATERIALS ON

THRESHOLD VOLTAGE SHIFTS IN P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER MECHANICAL STRESS

6.1 Introduction

Uniaxial strained-Si has been adopted to increase performance in sub-90nm production

technologies[24, 31, 80]. Strain-induced threshold voltage, Vth, shift can be a critical issue[136].

However, little attention has been given to Vth shift in uniaxial technology[137]. Vth shift in Si p-

MOSFETs is generally regarded as insignificant without any quantitative explanation[138].

Because scaling has reached fundamental material limits for gate stacks and channels, we

can now scale with new materials and/or device architectures. TiN/HfO2 gate stack and strained-

Ge have been expected to be substitutes for poly Si/SiO2 gate stack and strained-Si because of

their smaller gate leakage and higher channel mobility, respectively[139, 140]. Therefore the

investigation of strain-altered Vth shift of these devices is timely and worthy. In this work,

uniaxial strain-induced Vth shifts of both Ge and Si p-MOSFETs with TiN/HfO2 gate stacks are

explained and compared to poly Si gate stacks. The contribution of strain-induced mobility

change to measured Vth shifts is also considered.

6.2 Threshold Voltage Shift Models

The Vth shift for a Si p-MOSFET with a poly Si gate under mechanical stress can be

derived from [136, 137];

))()0(

ln())()0(

ln()1()()(σσ

σσdp

dp

C

Cgth m

mq

kTmNN

qkTmEmV −−−Δ−=Δ (6-1)

where )(σgEΔ , m, CN and dpm are the change in the band gap with stress, the body-coefficient,

the effective densities of states (DOS) in the 3-D conduction band and the 2-D hole DOS

70

effective mass in the predominant sub-band, respectively. The same derivation can be used for Si

and Ge p-MOSFETs with TiN gate, as shown in (6-2)

))()0(

ln())()0(

ln()1()()()()(σσ

σσσφσdp

dp

C

CgCMth m

mq

kTmNN

qkTmEmEV −−−Δ−Δ+Δ=Δ (6-2)

where )(σφMΔ and )(σCEΔ are the changes in the gate work-function [102] and channel electron

affinity and CEΔ and gEΔ contribute to the Vth, but with different signs. Here, MφΔ is

positive/negative under compression/tension[87, 102, 141]. Note that, in (6-2), a TiN gate device

has both CEΔ and gEΔ , while, in (1), a poly Si gate device has gEΔ only. This is because both

the Si channel and the poly Si gate are being strained in poly Si gate device[137].

Deformation potential theory is used to express CEΔ and gEΔ as a function of stress. Strain

induces the hydrostatic shift and shear band splitting of conduction band edges, which can be

expressed as; [53, 55, 84]

iiuijdiC TrE εε Ξ+Ξ=Δ )( (6-3)

where dΞ and uΞ are dilation and shear deformation potential constants, Tr(εij) is the trace of the

strain tensor ( ijε ) and i denotes the various valleys (X for Si and L for Ge). For Si and Ge

, CEΔ and gEΔ are calculated and listed in Table 6-1[17, 55].

Strain-induced changes in DOS-related terms also shift Vth (last two terms in (6-1) and (6-

2)). The change in the effective DOS in the 3-D conduction band is given

by 2/3*2/3* )(/)0()(/)0( σσ CCCC mmNN = .[142] In both Si and Ge, CN -related term is negative,

irrespective of the type of stress, because stress along [110] causes )0()( **CC mm <σ via band

splitting [137]. For low stress and moderate to high gate bias, the predominant sub-band in the

hole inversion-layer can be determined by gate bias since the energy level splitting from

71

confinement is dominant[80]. Therefore, applied stress alters )(σdpm only via valence band

warping, resulting in )(σdpm to increase/decrease with compression/tension[13, 80].

Therefore, dpm -related term is positive/negative with compression/tension. The contribution of

CN - and dpm -related terms are significant under tension because both of terms are negative,

while under compression, the two terms are opposite in sign.

Both (6-1) and (6-2) were derived based on equal inversion charge at the threshold

condition [136]. To relate these expressions to the measured Vth shift [143], the correction term

is needed to account for the change in mobility in the strained channel and given;

))0()(ln()(

μσμσ

qkTmVth =Δ (6-4)

6.3 Results And Discussion

Strain-induced Vth shifts are calculated and compared with wafer bending data. Fig. 6-1(a)

plots Vth shifts of Si p-MOSFETs with poly Si and TiN gates, respectively. Under compression,

the Vth shift in TiN gate devices is ~2/3 times of that in poly Si gate devices, while it is larger

than that in poly Si gate devices under tension. This mainly results from subtractive CEΔ in TiN

gate devices, as explained in Sec. 6.2. It is also found that, for poly Si gate devices, the Vth shift

under compression is larger than tension, because there is larger band gap narrowing from

compression and smaller contribution of DOS-related terms[84]. Fig. 6-1(b) plots Vth shifts of

Ge and Si p-MOSFETs with TiN gate. Based on the calculation using (6-2), larger Vth shifts for

Ge are expected under compression because, relative to Si p-MOSFET, the Ge channel has larger

band edge shift terms ( )()( σσ gC EmE Δ−Δ ).

Next, the mobility correction term is considered. Uniaxial stress along [110] causes

channel mobility to change significantly relative to biaxial strain[80]. The contribution of

72

mobility change to the Vth shift, which has been regarded as insignificant in biaxial strain, may

be critical in uniaxial strain [136]. Fig. 6-2 plots the strain-induced Vth shift of Ge and Si p-

MOSFETs with TiN gates with the mobility correction. The inset shows that the relative change

in mobility of Si is slightly larger than that of Ge, which is extracted from measured drain current

change [82, 93]. Based on mobility change, we calculate the contribution of mobility change

terms, listed in Table 6-2, where model-predicted contributions of band-edge shift, DOS-related

terms, and MφΔ are also indicated. As expected, the contribution of mobility change to measured

Vth shifts is significant and even dominant for Si devices. Note that after the correction, the Vth

shift of Ge is slightly larger than that of Si, resulting in insignificant Vth shifts of both Ge and Si

p-MOSFETs with TiN/HfO2 gate stacks.

6.4 Conclusion

Both Ge and Si p-MOSFETs with TiN gates are observed to have insignificant Vt variation

under uniaxial stress. The simple Vth shift model including the mobility correction shows good

agreements with the measured data from different types of p-MOSFETs, demonstrating its

universality [144].

73

Table 6-1. Deformation potential constants used in this study [17] and CEΔ and gEΔ of Si and Ge, calculated at 300 MPa of uniaxial tension and compression along [110] direction.

DEFORMATION

POTENTIAL CONSTANTS [EV]

STRESS TYPE ∆EC [mV] @300MPA

∆EG [mV] @300MPA

TENSION -5.14 -3.48 Si

dΞ =1.0, uΞ =9.6 B=-2.33, D=-4.75

aud −

Ξ+Ξ

3 =0.29 COMPRESSION -8.99 -10.6

TENSION -5.52 -1.33 Ge

dΞ =-4.3, uΞ =16.5 b=-2.16, d=-6.06

aud −

Ξ+Ξ

3 =-0.83 COMPRESSION -8.68 -13.9

74

Table 6-2. Model-predicted, with m=1.3, contributions of band edge shifts, DOS change, Δµ and ΔΦM terms. (ΔΦM is estimated from [102])

THEORETICAL VALUE EXPERIMENTAL VALUE ∆VTH FROM BAND EDGE

SHIFT

∆VTH FROM DOS-RELATED

TERMS ∆VTH FROM Δµ ∆VTH FROM

ΔΦM

STRESS TYPE

[mV] @ 100MPA

TENSION -0.21 -1.46 -2.45 -1.5 Si

COMPRESSION 1.32 0.13 1.97 1.5

TENSION -1.50 -1.15 -1.79 -1.5 Ge

COMPRESSION 2.12 0.43 1.81 1.5

75

Figure 6-1. Plots of uniaxial stressed Vth shifts of p-MOSFETs with (a) different gate stacks

(poly Si/SiO2 vs TiN/HfO2) and (b) different channels (Ge vs Si). Symbols and lines are experimental data and calculated models, respectively. Note here that

0<Δ thV would mean that the magnitude of Vth (which is negative) is increased by stress.

W. Zhao 2004

S. Suthram 2008

76

Figure 6-2. Plots of Vth shifts of Ge and Si p-MOSFETs with the mobility correction as a function of stress. Symbols and lines are experimental data and calculated models, respectively. The inset shows the relative changes in mobility of Ge and Si p-MOSFETs with TiN/HfO2 gate stack as a function of stress.

77

CHAPTER 7 RELIABILITY OF NITRIDED HAFNIUM SILICATE GATE DIELECTRICS UNDER [110] UNIAXIAL MECHANICAL STRESS: TIME DEPENDENT DIELECTRIC BREAKDOWN

7.1 Introduction

State-of-the-art CMOS devices requires uniaxial stress to enhance the performance of

transistor with high k gate stack[145]. Among the candidates for high-k dielectrics, nitrided

hafnium silicate (HfSiON) is a promising material due to high crystallization temperature and

thermodynamic stability with Si[146]. The reliability of HfSiON Si MOS device, such as time

dependent dielectric breakdown (TDDB), bias temperature instability (BTI) and threshold

voltage (VTH) instability, and hot carrier injection (HCI) also has been extensively studied to help

improve device lifetime[147].

It has been reported that applied mechanical stress changes TDDB and negative bias

temperature instability (NBTI) in SiO2 dielectric Si MOS device[100, 148-150] but less attention

has been focused on impact of applied mechanical stress on TDDB and NBTI in HfSiON[111,

151]. Furthermore, most of these works have used process-induced strain, such as a nitride

stressor, which can contain hydrogen and water and introduce ambiguity into the strain effect on

device reliability[100, 152-154].

In this work, we report on the effects of both uniaxial tensile and compressive stresses on

TDDB in HfSiON Si MOS devices using controlled applied external mechanical stress. From the

mechanical stress dependence and thickness independence, possible degradation mechanisms are

identified. Mechanical stress-induced BTI, HCI, and VTH instability of high k MOSFETs are also

briefly discussed.

78

7.2 Experimental Setup

Samples used in this work consist of MOS capacitors with aluminum metal gate on top of

7 and 8 nm HfSiON dielectrics fabricated on p-type (100) Si substrate[155]. Samples with gate

area of 0.000857, 0.0016, 0.0026, and 0.0052 cm2 are used. Constant negative gate voltage

stressing is performed with a gate leakage current compliance limit of 10 pA using a Keithley

4200 DC characterization system. We define the time to breakdown (tBD) as the first sudden

increase in the gate leakage current (soft breakdown), as shown in Figure 7-1[147, 156-158]. The

steep increase in the gate leakage current upon onset of breakdown allows measurement of the

breakdown event at a well-defined electric field. A custom built four point wafer bending setup

is used to apply external mechanical stress along the [110] direction during constant voltage

stressing (CVS)[13]. The impact of mechanical stress on the distribution of tBD and charge to

breakdown (QBD) is monitored in the HfSiON MOS capacitor samples.

Figure 7-1. Current-time curve for 7 nm HfSiON dielectric Si MOS device during CVS

79

7.3 Experimental Results

In this section, experimental data on the distributions of tBD and QBD in HfSiON Si MOS

capacitors under both mechanical tensile and compressive stress is reported. Figure 7-2(a) shows

tBD Weibull plots with different area samples with 7 nm thick HfSiON dielectrics, where an area-

dependent tBD distribution is observed [159]. When the results are scaled by area as in Figure

2(b), the scaled tBD Weibull curves coincide which indicates an intrinsic breakdown mechanism.

The area scaled tBD is computed based on the following equation.

ij AAij tFtF /))(1(1)( −−= (7-1)

where jF and iF are the probability of failure at area jA and iA [111, 160]. The Weibull slope (β)

is 1.2, which is close to the published value[156].

To understand the impact of uniaxial mechanical stress on tBD in samples, CVS is

performed with VG = -5.2 and -7 V under tensile and compressive stresses, respectively. Fig.7-3

and 7-4 show impact of mechanical stress on tBD Weibull plots. Applied tensile stress reduces

time to breakdown at 50% (tBD,50%) from 44 to 15 sec and β from 1.4 to 1.1, respectively, as

shown in Fig. 7-3(a) and (b). In addition, compressive stress, in Fig. 7-4(a) and (b), also reduces

tBD,50% from 24 to 7.3 sec and β from 0.81 to 0.74, respectively. In summary, both applied tensile

and compressive stresses degrade tBD of HfSiON dielectric, consistent with the previously

reported data from process-induced strain and SiO2 dielectrics[111, 148, 161].

Mechanical stress dependence on tBD can be investigated by (1) monitoring the relative

change in gate injection current of HfSiON Si MOS device as a function of applied mechanical

stress[149] and (2) mechanical stress-induced increase in HfSiON/Si interface trap generation

during CVS[111]. In our previous work[155], we already observed an increase in gate injection

current, based on Poole-Frenkel emission, under both tensile and compressive stresses, matching

80

with our mechanical stress dependence on tBD in this work. Hence, it is consistent with the

observation that an increase in gate injection current results in a decrease of tBD.[149].

It has been reported that, for gate stack with high-k dielectric thicker than 7~8 nm, QBD for

gate injection is equivalent with those for SiO2 with a thickness identical to the interfacial layer

[158]. In Fig. 7-5, QBD for 8 nm thick HfSiON is measured and compared to QBD in samples with

7 nm thick HfSiON in order to confirm this interfacial layer breakdown mechanism. Since

interface quality is independent of the thickness of HfSiON [162], it shows almost similar QBD

distributions under 84 MPa of tensile and no mechanical stresses. Therefore, impact of

mechanical stress on tBD in HfSiON Si MOS device can be explained by mechanical stress-

altered trap generation in Si-rich HfSiON interlayer (IL) or at IL / (100) Si interface during CVS

[111]. Both tensile and compressive mechanical stresses facilitate trap generation at IL / (100) Si

interface or Si-O bond breaking in IL [99, 100, 105, 109, 111].

Figure7-2. The tBD distributions and area scaled tBD distributions for different size samples under VG = -5.2 V.

81

Figure 7-3. Uniaxial tensile stress effect a) on tBD distributions and b) on area scaled tBD distributions under VG = -5.2 V.

Figure 7-4. Uniaxial compressive stress effect a) on tBD distributions and b) on area scaled tBD distributions under VG = -7 V.

82

Figure 7-5. The QBD distributions for samples with two different HfSiON dielectrics thickness (7 and 8 nm) under tensile mechanical stress

7.4 Discussion

In this section, physical insight into impact of mechanical stress on reliability issues, such

as BTI, HCI, thermal stress-induced subthreshold leakage and VTH instability, will be provided

based on how applied mechanical stress affects high k/Si interface trap generation and trap

activation energy in high k dielectric.

In previous section, impact of mechanical stress on TDDB of 7 nm thick HfSiON Si MOS

device with negative gate voltage stressing was discussed. If TDDB occurs in thin (< 3 nm) high

k or with positive gate voltage stressing, it does not involved significant interface trap generation

and may be dependent on high k layer not Si rich interlayer[158]. This can result in improved

TDDB with mechanical stress if mechanical stress reduces gate tunneling current[149]. Since a

dominant gate tunneling mechanism in thick (> 3 nm) high k MOS device is Poole-Frenkel

emission[158] and mechanical stress increases Poole-Frenkel emission or trap-assisted gate

83

tunneling[130, 155], TDDB under mechanical stress may be improved only in thin (< 3 nm) high

k, where mechanical stress can decrease direct gate tunneling current[102].

It is widely proposed that NBTI also results from the generation of trap via Si-H bond

breaking at high k/Si interface[158, 163-165]. Fig. 7-6(a) shows high resolution TEM image of

HfSiON Si MOS capacitor, which contains SiO2-like Si rich interlayer. Since mechanical stress

makes Si-H bond less stable, as illustrated in Fig. 7-6(b) and (c)[109], both [110] tensile and

compressive mechanical stresses may degrade NBTI in high k Si MOSFETs [100, 166].

As discussed above, positive bias temperature instability (PBTI) may not generate

interface trap but involve charge trapping in high k bulk or high k/Si interface [158, 165]. This

may result in improved PBTI via mechanical stress-induced increase in charge detrapping in

thick (> 7 nm) HfO2 Si MOSFET [131]. An insignificant process-induced stress dependence of

PBTI in thin (3 nm) high k Si MOSFET has been already reported, resulting from negligible

charge trapping in thin high k layer [151, 167].

Thermal stress-induced sub-threshold leakage, which can degrade the retention time of

dynamic random access memory (DRAM) [168], also results from Si-H bond breaking at high

k/Si interface [168, 169]. Therefore, both [110] tensile and compressive stresses likely increase

thermal stress-induced sub-threshold leakage in high k Si MOSFETs via strain-enhanced

hydrogen depassivation at high k/Si interface [109].

It has been reported that HCI and VTH instability likely result from a trapping of charges in

the pre-existing traps in high k/Si interface and/or high k dielectric without creation of additional

traps [105, 107, 108, 158, 170]. Due to its technological importance, impact of external

mechanical stress on HCI has been aggressively studied, showing opposite trends[105, 107, 108,

170, 171]. Two strain-related models can explain this discrepancy: (1) a decrease in charge

84

trapping in relative thick gate dielectric via strain-altered trap activation energy[105, 107, 108]

and (2) strain-induced Si band gap narrowing and an increase in impact ionization at drain

edge[170, 171]. For both uniaxial tensile and compressive stresses, a decrease in a trapping of

injected hot carriers in high k likely results in an improved HCI, [130, 131] while an increase in

impact ionization may multiply a number of hot carriers, leading to an degradation of HCI [84].

In high k integration, VTH instability has been one of challenges[158]. As explained above,

applied mechanical stress reduces electron or/and hole trap activation energy in high k/Si

interface and/or high k dielectric[130, 131]. This results in (1) an increase in trap-assisted gate

tunneling (or Poole-Frenkel emission) and (2) a decrease in charge trapping in high k[130, 131].

Therefore, VTH instability can be improved at the expense of an increased trap-assisted gate

tunneling leakage under both uniaxial tensile and compressive stresses. Due to substantial

reduction of gate leakage in high k device,[165] this trade-off will be beneficial for device

performance.

Table 7-1 and Fig. 7-7 summarize impact of uniaxial mechanical stress on reliability issues

with thick (~ 7 nm) high k Si MOSFETs as discussed above. Most of reliability issues in strained

Si technology may be evaluated with impact of mechanical stress on trap activation energy in

high k and on high k/Si interface trap generation.

85

Figure 7-6. Interface trap generation under mechanical stress. a) High resolution TEM image of HfSiON Si MOS capacitor. The gate dielectric is composed of Hf rich HfSiON and Si rich interlayer. b) Schematic of Si rich interlayer/ (100) Si interface including Si-H bonding. c) The calculated energies corresponding to the hydrogen position [109]. Here, ESi-H is Si-H bonding energy and σ is applied uniaxial stress.

Figure 7-7. Schematic band diagram for key strain-related parameters for reliability issues.Here, EA,H and EA,E is hole and electron trap activation energy, σ is applied uniaxial stress, Qot, IG, and Nit is trapped charge density, gate leakage, and the number of interface trap, respectively.

1999

86

7.5 Conclusion

Uniaxial mechanical stress may not be beneficial for > 7nm thick HfSiON Si MOS device

from the view point of reliability issues, such as TDDB, BTI and thermal stress-induced sub-

threshold leakage[172]. Applied tensile and compressive stresses degrade TDDB in HfSiON Si

MOS device, which results from mechanical stress-induced increase in (1) trap generation in

HfSiON/Si interface during negative gate voltage stressing and/or (2) trap-assisted gate

tunneling. For state-of-the-art strained-Si techniques, where up to 1.5 GPa of stress can be

achieved in channel area, process-induced mechanical stress in HfSiON/Si interface is inevitable.

Therefore, interface engineering, which can improve the quality of HfSiON/Si interface, may be

required to improve TDDB, NBTI, and thermal stress-induced sub-threshold leakage of HfSiON

Si MOSFETs together with strain engineering[152]. Uniaxial strain engineering shows the

potential to decrease HCI and VTH instability in high k MOSFETs via a decrease in charge

trapping.

87

Table 7-1. Measured and estimated reliability issues of thick (> 7 nm) high k Si MOSFET as a function of uniaxial mechanical stress.

KEY MECHANISM

KEY STRAIN-RELATED

PARAMETER TENSION COMPRESSIO

N REF.

VG < 0

POOLE-FRENKEL

EMISSION & INTERFACE

TRAP GENERATION

TRAP ACTIVATION

ENERGY & SI-H BOND

DEPASSIVATION

DEGRADED DEGRADED THIS WORK

TDDB

VG > 0 POOLE-

FRENKEL EMISSION

TRAP ACTIVATION

ENERGY DEGRADED DEGRADED [155]

VG < 0 INTERFACE

TRAP GENERATION

SI-H BOND DEPASSIVATION DEGRADED DEGRADED

[100, 151, 166]

BTI (VTH

SHIFT) VG > 0 CHARGE

TRAPPING

TRAP ACTIVATION

ENERGY IMPROVED IMPROVED [131]

THERMAL STRESS

INDUCED SUB-THRESHOLD

LEAKAGE

INTERFACE TRAP

GENERATION

SI-H BOND DEPASSIVATION DEGRADED DEGRADED

IMPACT IONIZATION DEGRADED DEGRADED [170,

171] HCI CHARGE

TRAPPING TRAP ACTIVATION

ENERGY IMPROVED IMPROVED

[105, 107, 108]

VTH INSTABILITY

CHARGE TRAPPING

TRAP ACTIVATION

ENERGY IMPROVED IMPROVED [131]

88

CHAPTER 8 SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK

8.1 Summary

This study mainly focuses on externally applied mechanical uniaxial stress effects on Si &

Ge MOSFETs in terms of channel mobility, gate tunneling leakage, and gate stack, such as high

k dielectric and metal gate.

The physics and advantages of uniaxial process induced stress are understood. Calculations

and experimental data show that low in-plane and large out-of-plane conductivity effective

masses and a high density of states in the top band are all necessary for large hole and electron

mobility enhancement.

It is explained that, for n-MOSFETs under uniaxial tensile stress along [110] and [100], the

change in direct gate tunneling current for Ge is measured to be 3 times smaller than that for Si

and opposite in sign. This reverse behavior occurs because tensile stress for Si causes electron

repopulation into Δ2 increasing the out-of-plane effective mass while, in Ge, a reduced tunneling

barrier is the dominant mechanism, resulting from the hydrostatic shift of the conduction band

edge.

This is followed by the study about the direct gate tunneling current of Ge and Si p-

MOSFETs. Due to larger 1) stress induced valence band edge splitting and 2) change in hole

tunneling attempt frequency in inversion-layer of Ge under uniaxial tensile stress, the change in

stress altered hole direct gate tunneling current in Ge is ~4 times larger than that in Si. The work-

function of the metal gate is measured to change with mechanical stress and decrease/increase

~20meV for each 1 GPa of uniaxial tensile/compressive stress.

Impacts of mechanical stress on direct and trap-assisted gate tunneling leakage current are

also observed. The applied mechanical stress increases trap-assisted tunneling current via the

89

lowering of trap activation energy showing uniaxial stress may not be applicable to reduce gate

leakage current when trap-assisted tunneling conduction is dominant.

The roles of HfSiON dielectric in strained Si technology are explored. Unlike HfSiOx and

HfO2, HfSiON shows strain altered increased dielectric constant, which allows scaling to achieve

an increased gate capacitance.

Both Ge and Si p-MOSFETs with TiN gate are observed to have insignificant Vt variation

under uniaxial stress. The simple Vth shift model including the mobility correction shows good

agreements with the measured data from different types of p-MOSFETs (poly Si/SiO2 vs

TiN/HfO2 gate stacks and Si & Ge channels).

Finally, impact of mechanical uniaxial stress on time dependent dielectric breakdown of

HfSiON dielectric is studied. Under constant voltage stressing with negative gate bias, applied

mechanical stress causes HfSiON/Si interface to become less stable. This results in more trap

generation at interface and leads to a decrease in time to dielectric breakdown.

8.2 Recommendations for Future work

The demand for novel material and structure becomes increasing in the CMOS regime.

With strain engineering becoming a mainstream in VLSI technology, there will be much interest

in studying its effects in channel mobility of novel devices, such as FINFET with Ge or III-V

channel.

While aggressive researches have been done on how strain improve channel mobility of

planar novel channel devices, such as Ge and III-V, less attention has been paid to strain effect

on reliability of these devices. As a part of future work, it is interesting to continue the work on

impact of mechanical stress on reliability of novel channel devices, such as time dependent

dielectric breakdown, hot carrier injection, bias temperature instability and so on.

90

The aggressive scaling of VLSI technology will push the channel length to ballistic

transport regime and the importance of surface roughness scattering limited mobility gets

significant. Therefore, it is interesting to study strain effects on physical surface roughness

or/and surface roughness scattering in order to fully understand mobility enhancement

mechanism in very short channel length devices.

91

LIST OF REFERENCES

[1] J. Bardeen and W. Shockley, "Deformation Potentials and Mobilities in Non-Polar Crystals," Physical Review, vol. 80, pp. 72-80, 1950.

[2] C. Herring and E. Vogt, "Transport and Deformation-Potential Theory for Many-Valley Semiconductors with Anisotropic Scattering," Physical Review, vol. 101, pp. 944-961, 1956.

[3] G. L. Bir and G. E. Pikus, Symmetry and Strain-Induced Effects in Semiconductors. New York: John Wiley & Sons, 1974.

[4] H. M. Manasevit, I. S. Gergis, and A. B. Jones, "Electron mobility enhancement in epitaxial multilayer Si-Si1–xGex alloy films on (100) Si," App. Physics Letters, vol. 41, pp. 464-466, 1982.

[5] R. People, J. C. Bean, D. V. Lang, A. M. Sergent, H. L. Stormer, K. W. Wecht, R. T. Lynch, and K. Baldwin, "Modulation doping in GexSi1–x/Si strained layer heterostructures," App. Physics Letters, vol. 45, pp. 1231-1233, 1984.

[6] K. Rim, "Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs," presented at Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 3.1.1, 2003.

[7] A. Shimizu, "Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement," presented at Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 19.4.1, 2001.

[8] S. Gannavaram, N. Pesovic, and C. Ozturk, "Low temperature (800 degrees C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS," Technical Digest of the IEEE International Electron Devices Meeting, 437-440, 2000.

[9] A. Murthy, R. S. Chau, T. Ghani, and K. R. Mistry, "Semiconductor transistor having a stressed channel," Intel, Ed. United States, 2005.

[10] S. Thompson, "A 90nm Logic Technology Futuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Intercinnects, Low k ILD, and 1 μm2 SRAM Cell," presented at Technical Digest of the IEEE International Electron Devices Meeting, Washington, 61-64, 2002.

[11] M. V. Fischetti, "Six-band k.p Calculation of the Hole Mobility in Silicon Inversion Layers: Dependence on Surface Orientation, Strain, and Silicon Thickness," J. Appl. Phys., vol. 94, pp. 1079-1095, 2003.

[12] G. Fitzgerald, "A quick primer on strained silicon," in EE Times, 2004.

92

[13] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key Differences For Process-induced Uniaxial vs. Substrate-induced Biaxial Stressed Si and Ge Channel MOSFETs," Tech. Dig. - Int. Electron Device Meet., 9.4.1, 2004.

[14] J. G. Fossum and W. Zhang, "Performance Projections of Scaled CMOS Devices and Circuits With Strained Si-on-SiGe Channels," IEEE Trans. Electron Devices, vol. 50, pp. 1042-1048, 2003.

[15] K. Rim, J. Chu, H. Chen, K. A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. Wong, "Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., pp. 98, 2002.

[16] C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate," Tech. Dig. - Int. Electron Device Meet., pp. 437, 2002.

[17] M. V. Fischetti and S. E. Laux, "Band Structure, deformation Potentials, and Carrier Mobility in Strained Si, Ge, and SiGe alloys," J. Appl. Phys., vol. 80, pp. 2234-2252, 1996.

[18] J. S. Lim, X. Yang, T. Nishida, and S. E. Thompson, "Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress," Appl. Phys. Lett., vol. 89, pp. 073509, 2006.

[19] W. Zhao, A. Seabaugh, V. Adams, A. Jovanovic, and B. Winstead, "Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain," IEEE Electron Device Lett., vol. 26, pp. 410-412, 2005.

[20] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, "Strain-induced changes in the gate tunneling currents in p-channel metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 88, pp. 052108, 2006.

[21] Y. S. Choi, J.-S. Lim, T. Numata, T. Nishida, and S. Thompson, "Mechanical stress altered electron gate tunneling current and extraction of conduction band deformation potentials for Germanium," Journal of Applied Physics, vol. 102, pp. 104507, 2007.

[22] B. Ricco, G. Gozzi, and M. Lanzoni, "Modeling and simulation of stress-induced leakage current in ultrathin SiO2 films," IEEE Trans. Electron Devices, vol. 45, pp. 1554-1560, 1998.

[23] A. I. Chou, K. Lai, K. Kumar, P. Chowdhury, and J. C. Lee, "Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism," Applied Physics Letters, vol. 70, pp. 3407-3409, 1997.

93

[24] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Y. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, pp. 191-193, 2004.

[25] P. R. Chidambaram, B. A. Smith, L. H. Hall, H. Bu, S. Chakravarthi, and Y. K. a. e. al., "35% Drive Current Improvement from Recessed-SiGe Drain extensions on 37 nm Gate Lenght PMOS," presented at Symp. VLSI Tech. Dig., Hawaii, 48-49, 2004.

[26] W.-H. Lee, A.Waite, H. Nii, H. M. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, and et al., "High Performance 65 nm SOI Technology with Enhanced Transistor Strain and Advanced-Low-K BEOL," presented at Technical Digest of the IEEE International Electron Devices Meeting, 2005.

[27] P. Bai, "A 65nm Logic Technology Featuring 35nm Gate Lenghts, Enhanced Channel Strain, 8 cu interconnects Layesrs, Low-k ILD and 0.57um2 SRAM Cell," presented at Technical Digest of the IEEE International Electron Devices Meeting, 28.2.1, 2004.

[28] H.S.Yang, "Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing," presented at Technical Digest of the IEEE International Electron Devices Meeting, 28.8.1, 2004.

[29] C. Chien-Hao, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, and a. Diaz et, "Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application," presented at Symp. VLSI Tech. Dig., 56-57, 2004.

[30] V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, and a. e. al., "High Speed 45nm Gate Length CMOSFETs Integrated Into a 90nm Bulk Technology Incorporating Strain Engineering," presented at Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 3.8.1, 2003.

[31] A. Al-Bayati, L. W. L. Q. Xia, M. Balseanu, Z. Yuan, and M. Kawaguchi, "Production processes for inducing strain in CMOS channels," in Semiconductor Fabtech, 26 ed, 2004, pp. 84-88.

[32] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, and a. e. al., "A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films," presented at IEDM, Tokyo, Japan, 9.2.1, 2004.

[33] J. J. Wortman and R. A. Evans, "Youngs Modulus Shear Modulus and Poissons Ratio in Silicon and Germanium," Journal of Applied Physics, vol. 36, pp. 153, 1965.

[34] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, "Physical Mechanisms of Electron Mobility Enhancement in Uniaxial Stressed MOSFETs and Impact of Uniaxial Stress Engineering in Ballistic Regime," presented at Technical Digest of the IEEE International Electron Devices Meeting, 2006.

94

[35] V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, J. Chen, E. Nowak, X.-D. Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, H. Ng, S.-F. Huang, and C. Wann, "High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering," Tech. Dig. - Int. Electron Device Meet., pp. 3.8.1, 2003.

[36] T. Ghani, S. E. Thompson, and M. B. a. e. al., "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors," presented at Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 11.6.1, 2003.

[37] C. Y.-P. Chao and S. L. Chuang, "Spin-Orbit-Coupling Effects on the Valence-Band Structure of Strained Semiconductor Quantum Wells," Phys. Rev. B, vol. 46, pp. 4110-4122, 1992.

[38] D. Zhang, B.Y.Nguyen, T. White, B. Goolsby, T.Nguyen, V.Dhandapani, and a. e. al., "Embedded SiGe S/D PMOS in thin body SOI substrate with drive current enhancement," presented at Symp. VLSI Technology, 26-27, 2005.

[39] Q. Quyang, M. Yang, J. Holt, S. Panda, H. Chen, U. H, and a. e. al., "Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientaion substrates," Symp. VLSI Technology, 28-29, 2005.

[40] K. Rim, J. Welser, J. L. Hoyt, and J. F. Gibbons, "Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs," IEDM Tech. Dig, pp. 517-520, 1995.

[41] F. Stern, "Self-consistent results for n-type Si inversion layers," Physical Review B (Solid State), vol. 5, pp. 4891-4899, 1972.

[42] R. Oberhuber, G. Zandler, and P. Vogl, "Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET's," Phys. Rev. B, vol. 58, pp. 9941-9948, 1998.

[43] L. Shifren, X. Wang, P. Matagne, B. Obradovic, C. Auth, and S. Cea, "Drive current enhancement in p-type metal–oxide–semiconductor," App. Physics Letters, vol. 85, pp. 6188, 2004.

[44] A. Pirovano, A. L. Lacaita, G. Zandler, and R. Oberhuber, "Explaining the dependences of the hole and electron mobilities in Si inversion layers," IEEE Transactions on Electron Devices, vol. 47, pp. 718-724, 2000.

[45] F. Gamiz, J. B. Roldan, and J. A. Lopez-Villanueva, "Surface roughness at the Si-SiO2 interface in fully depleted silicon-on-insulator inversion layers," Journal of Applied Physics, vol. 86, pp. 6854-6863, 1999.

[46] E. Wang, "Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress," presented at Technical Digest of the IEEE International Electron Devices Meeting, 6.4.1, 2004.

95

[47] K. Seeger, Semiconductor Physics: An Introduction. Berlin Heidelberg New York: Springer-Verlag, 2004.

[48] K. Takeda, K. Sakui, and M. Sakata, "Valence-band parameters and hole mobility of Ge-Si alloys-theory," J. Appl. Phys., vol. 16, pp. 2237-2249, 1983.

[49] K. Matsuda, H. Nakatsuji, and Y. Kamakura, "Strain Effect on the Final State Density-of-State for Hole Scattering in Silicon," presented at Tech. Proc. Nanotechnology Conference and Trade Show, 2003.

[50] T. Yamada and D. K. Ferry, "Monte-Carlo Simulation of Hole Transport in Strained Si1-Xgex," Solid-State Electronics, vol. 38, pp. 881-890, 1995.

[51] S. Yamakawa, H. Ueno, K. Taniguchi, C. Hamaguchi, K. Miyatsuji, K. Masaki, and U. Ravaioli, "Study of interface roughness dependence of electron mobility in Si inversion layers using the Monte Carlo method," J. Appl. Phys., vol. 79, pp. 911-916, 1996.

[52] M. Lundstrom, Fundamentals of carrier transport, 2nd ed: Cambridge University Press, 2000.

[53] C. G. Vandewalle and R. M. Martin, "Theoretical Calculations of Heterojunction Discontinuities in the Si/Ge System," Phys. Rev. B, vol. 34, pp. 5621-5634, 1986.

[54] A. Rahman, M. S. Lundstrom, and A. W. Ghosh, "Generalized effective-mass approach for n-type metal-oxide-semiconductor field-effect transistors on arbitrarily oriented wafers," J. Appl. Phys., vol. 97, pp. 053702, 2005.

[55] I. Balslev, "Influence of Uniaxial Stress on Indirect Absorption Edge in Silicon and Germanium," Phys. Rev., vol. 143, pp. 636-&, 1966.

[56] P. Y. Yu and M. Cardona, Fundamentals of Semicondictors, 3 ed: Springer, 2003.

[57] F. H. Pollak and M. Cardona, "Piezo-Electroreflectance in Ge Gaas and Si," Phys. Rev., vol. 172, pp. 816-&, 1968.

[58] C. Kittle, Introduction to Solid State Physics, 6th ed. ed. New York: John Wiley & Sons, Inc., 1996.

[59] T. Low, Y. T. Hou, M. F. Li, C. Zhu, D. L. Kwong, and A. Chin, "Germanium MOS: an evaluation from carrier quantization and tunneling current," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., pp. 117, 2003.

[60] G. Dorda, "Piezoresistance in Quantized Conduction Bands in Silicon Inversion Layers," J. Appl. Phys., vol. 42, pp. 2053-&, 1971.

[61] S. Datta, Quantum Transport: Atom to Transistor. New York: Cambridge, 2005.

96

[62] S. Mudanai, Y.-Y. Fan, Q. Ouyang, A. F. Tasch, F. Register, D. L. Kwong, and S. Banerjee, "Modeling of direct tunneling current through gate dielectric stacks," Simulation of Semiconductor Processes and Devices, pp. 200, 2000.

[63] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, "Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices," IEEE Trans. Electron Devices, vol. 46, pp. 1464-1471, 1999.

[64] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, "Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices," J. Appl. Phys., vol. 91, pp. 258-264, 2002.

[65] J. Maserjia and G. Petersson, "Tunneling through Thin Mos Structures - Dependence on Energy (E-K)," Appl. Phys. Lett., vol. 25, pp. 50-52, 1974.

[66] J. C. Garcia, L. M. R. Scolfaro, J. R. Leite, A. T. Lino, V. N. Freire, G. A. Farias, and E. F. d. Silva, "Effective masses and complex dielectric function of cubic HfO2," Appl. Phys. Lett., vol. 85, pp. 5022-5024, 2004.

[67] L. Yan, S. H. Olsen, M. Kanoun, R. Agaiby, and A. G. O'Neill, "Gate leakage mechanisms in strained Si devices," J. Appl. Phys., vol. 100, pp. 104507, 2006.

[68] B. Govoreanu, P. Blomme, K. Henson, J. V. Houdt, and K. D. Meyer, "An effective model for analysing tunneling gate leakage currents through ultrathin oxides and high-k gate stacks from Si inversion layers," Solid-State Electronics, vol. 48, pp. 617-625, 2004.

[69] F. J. Morin, T. H. Geballe, and C. Herring, "Temperature Dependence of the Piezoresistance of High-Purity Silicon and Germanium," Phys. Rev., vol. 105, pp. 525-539, 1957.

[70] M. K. Roy and B. K. Deb, "Phonon conductivity in As-, Sb-, and P-doped Ge for intermediate donor concentration," Phys. Rev. B, vol. 57, pp. 12229-12233, 1998.

[71] S. Takagi, M. Takayanagi, and A. Toriumi, "Experimental examination of physical model for direct tunneling current in unstressed/stressed ultrathin gate oxides," Tech. Dig. - Int. Electron Device Meet., 18.7.1, 1999.

[72] W. Mizubayashi, N. Yasuda, K. Okada, H. Ota, H. Hisamatsu, K. Iwamoto, K. Tominaga, K. Yamamoto, T. Horikawa, T. Nabatame, H. Satake, and A. Toriumi, "Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics," Microelectronics Reliability, vol. 45, pp. 1041-1050, 2005.

[73] W. Mizubayashi, N. Yasuda, H. Ota, H. Hisamatsu, K. Tominaga, K. Iwamoto, K. Yamamoto, T. Horikawa, T. Nabatame, and A. Toriumi, "Carrier separation analysis for clarifying leakage mechanism in unstressed and stressed HfAlOx/SiO2 stack dielectric layers," IEEE International reliability physics symposium, pp. 188, 2004.

97

[74] K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Ang, C. H. Yu, and M. S. Liang, Tech. Dig. - Int. Electron Device Meet., pp. 679, 2000.

[75] S. Takagi and M. Takayanagi, "Carrier transport properties of thin gate oxides after soft and hard breakdown," Microelectronic Engineering, vol. 59, pp. 5-15, 2001.

[76] Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, "Polarity dependent gate tunneling currents in dual-gate CMOSFET's," IEEE Transactions on Electron Devices, vol. 45, pp. 2355-2360, 1998.

[77] W. Y. Loh, B. J. Cho, M. S. Joo, M. F. Li, D. S. Chan, S. Mathed, and D.-L. Kwong, "Analysis of Charge Trapping and Breakdown Mechanism in High-K Dielectrics with Metal Gate Electrode using Carrier Separation," Tech. Dig. - Int. Electron Device Meet., 38.3.1, 2003.

[78] E. M. Vogel, K. Z. Ahmed, B. Hornung, W. K. Henson, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. J. Wortman, "Modeled Tunnel Currents for High Dielectric Constant Dielectrics," IEEE Trans. Electron Devices, vol. 45, pp. 1350-1355, 1998.

[79] J. P. Chang and Y.-S. Lin, "Dielectric property and conduction mechanism of ultrathin zirconium oxide films," Appl. Phys. Lett., vol. 79, pp. 3666-3668, 2001.

[80] S. E. Thompson, G. Y. Sun, Y. S. Choi, and T. Nishida, "Uniaxial-process-induced strained-Si: Extending the CMOS roadmap," IEEE Trans. Electron Devices, vol. 53, pp. 1010-1020, 2006.

[81] P. Kleimann, B. Semmache, M. L. Berre, and D. Barbier, "Stress-dependent hole effective masses and piezoresistive properties of p-type monocrystalline and polycrystalline silicon," Phys. Rev. B, vol. 57, pp. 8966-8971, 1998.

[82] S. Suthram, P. Majhi, G. Sun, P. Kalra, P. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B. J. Cho, M. M. Hussain, C. Smith, S. Banerjee, W. Tsai, S. E. Thompson, H. H. Tseng, and R. Jammy, "Demonstration of High Performance PMOSFETs Using Si/SixGe1-x/Si Quantum Wells with High-k/Metal Gate Stacks and Uniaxial Strain Additivity for 22 nm Technology and Beyond," Tech. Dig. - Int. Electron Device Meet., 2007.

[83] J. G. Simmons, "Generalized Formula for the Electroc Tunnel Effect between Similar Electrodes Seperated By a Thin Insulating Film," J. Appl. Phys., vol. 34, pp. 1793-1803, 1963.

[84] K. Matsuda and Y. Kanda, "Stress-induced effects on depletion-layer capacitance of metal-oxide-semiconductor capacitors," Appl. Phys. Lett., vol. 83, pp. 4351-4353, 2003.

[85] T. Toriyama and S. Sugiyama, "Analysis of piezoresistance in p-type silicon for mechanical sensors," Journal of Microelectromechanical Systems, vol. 11, pp. 598-604, 2002.

98

[86] D. Vasileska and D. K. Ferry, "The influence of space quantization effects on the threshold voltage, inversion layer and total gate capacitances in scaled Si-MOSFETs," Nanotechnology, vol. 10, pp. 192-197, 1999.

[87] W. Li and D. Y. Li, "In situ measurements of simultaneous electronic behavior of Cu and Al induced by mechanical deformation," J. Appl. Phys., vol. 99, pp. 073502, 2006.

[88] W. Li and D. Y. Li, "Effects of elastic and plastic deformations on the electron work function of metals during bending tests," in Philosophical Magazine, vol. 84, 2004, pp. 3717-3727.

[89] Y. T. Hou, M. F. Li, T. Low, and D. L. Kwong, "Metal gate work function engineering on gate leakage of MOSFETs," IEEE Trans. Electron Devices, vol. 51, pp. 1783-1789, 2004.

[90] S. Nagano, "Mechanism of leakage current through the nanoscale SiO2 layer," J. Appl. Phys., vol. 75, pp. 3530-3535, 1994.

[91] K.-F. You and C.-Y. Wu, "A new quasi-2-D model for hot-carrier band-to-band tunneling current," IEEE Trans. Electron Devices, vol. 46, pp. 1174-1179, 1999.

[92] Z. A. Weinberg, "Tunneling of electrons from Si into thermally grown SiO2," Solid-State Electronics, vol. 20, pp. 11-18, 1977.

[93] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices: Cambridge, 1998.

[94] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Y. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shiften, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices, vol. 51, pp. 1790-1797, 2004.

[95] R. Arghavani, N. Derhacobian, V. Banthia, M. Balseanu, N. Ingle, H. M'Saad, S. Venkataraman, E. Yieh, Z. Yuan, L. Q. Xia, Z. Krivokapic, U. Aghoram, K. MacWilliams, and S. E. Thompson, "Strain engineering to improve data retention time in nonvolatile memory," IEEE Trans. Electron Devices, vol. 54, pp. 362-365, 2007.

[96] Y. M. Park, J. S. Lee, M. Kim, M. K. Choi, T. K. Kim, J. I. Han, D. W. Kwon, W. K. Lee, Y. H. Song, and K. D. Suh, "The mechanical stress effects on data retention reliability of NOR Flash memory," IEDM Tech. Dig, 32.4.1, 2001.

[97] J. Om, E. Choi, S. Kim, H. Lee, Y. Kim, H. Chang, S. Park, and G. Bae, "The effect of mechanical stress from stopping nitride to the reliability of tunnel oxide and data retention characteristics of NAND Flash memory," IRPS, 2005.

[98] D. J. Dimaria and E. Cartier, "Mechanism for Stress-Induced Leakage Currents in Thin Silicon Dioxide Films," Journal of Applied Physics, vol. 78, pp. 3883-3894, 1995.

99

[99] A. Toda, S. Fujieda, K. Kanamori, J. Suzuki, K. Kuroyanagi, N. Kodama, Y. Den, and O. Nishizaka, "Impact of mechanical stress on interface trap generation in flash eeproms," presented at IEEE International Reliability Physics Symposium, San Jose, 2005.

[100] H. S. Rhee, H. Lee, T. Ueno, D. S. Shin, S. H. Lee, Y. Kim, A. Samoilov, P.-O. Hansson, M. Kim, H. S. Kim, and N.-I. Lee, "Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters," presented at Tech. Dig. - Int. Electron Device Meet., 2005.

[101] L. Pantisano and K. Cheung, "Stress-induced leakage current (SILC) and oxide breakdown: Are they from same oxide traps?" IEEE Trans. Devices and Material Reliability, vol. 1, pp. 109-111, 2001.

[102] Y. S. Choi, T. Numata, T. Nishida, R. Harris, and S. Thompson, "Impacts of mechanical stress on gate tunneling currents of Germanium and Silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work-function," Journal of Applied Physics, vol. 103, pp. 064510, 2008.

[103] X. Yang, Y. S. Choi, T. Nishida, and S. E. Thompson, "Gate Direct Tunneling Currents in Uniaxial Stressed MOSFETs," Electron Device and Semiconductor Technology, pp. 149, 2007.

[104] C. Chaneliere, J. L. Autran, and R. A. B. Devine, "Conduction mechanisms in Ta2O5/SiO2 and Ta2O5/Si3N4 stacked structures on Si," Journal of Applied Physics, vol. 86, pp. 480-486, 1999.

[105] A. Hamada, T. Furusawa, and E. Takeda, "A new aspect on mechanical stress effects in scaled MOS devices," presented at IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 1990.

[106] J. T. Yount, P. M. Lenahan, and P. W. Wyatt, "The Effects of Thermal Nitridation and Reoxidation on the Interfacial Stress and Structure of Silicon Dioxide Gate Dielectrics," Journal of Applied Physics, vol. 77, pp. 699-705, 1995.

[107] A. Hamada and E. Takeda, "Hot-Electron Trapping Activation Energy in PMOSFET’s Under Mechanical Stress," IEEE Electron Device Lett., vol. 15, pp. 31-32, 1994.

[108] A. Hamada and E. Takeda, "AC Hot-Carrier Effect Under Mechanical Stress," presented at IEEE Trans. Very Large Scale Integr. (VLSI) syst., 1992.

[109] B. Tuttle and C. G. Van de Walle, "Structure, energetics, and vibrational properties of Si-H bond dissociation in silicon," Phys. Rev. B, vol. 59, pp. 12884-12889, 1999.

[110] J. Mitsuhashi, S. Nakao, and T. Matsukawa, "Mechanical stress and hydrogen effects on hot carrier injection," Tech. Dig. - Int. Electron Device Meet., pp. 386, 1986.

100

[111] T. Onizawa, M. Terai, A. Toda, M. Oshida, N. Ikarashi, T. Hase, S. Fujieda, and H. Watanabe, "Impact of crystalline phase of Ni-Full-Silicide gate electrode on TDDB reliability of HfSiON gate stacks," IEEE International reliability physics symposium, pp. 195, 2006.

[112] C. C. Hong and J. G. Hwu, "Degradation in metal-oxide-semiconductor structure with ultrathin gate oxide due to external compressive stress," Applied Physics Letters, vol. 79, pp. 3797-3799, 2001.

[113] K. Yamamoto, S. Hayashi, M. Niwa, M. Asai, S. Horii, and H. Miya, "Electrical and physical properties of HfO2 films prepared by remote plasma oxidation of Hf metal," Applied Physics Letters, vol. 83, pp. 2229-2231, 2003.

[114] J. F. Kang, H. Y. Yu, C. Ren, M. F. Li, D. S. H. Chan, H. Hu, H. F. Lim, W. D. Wang, D. Gui, and D. L. Kwong, "Thermal stability of nitrogen incorporated in HfN[sub x]O[sub y] gate dielectrics prepared by reactive sputtering," Applied Physics Letters, vol. 84, pp. 1588-1590, 2004.

[115] K. Ramani, C. R. Essary, S. Y. Son, V. Craciun, and R. K. Singh, "Low temperature nitrogen incorporation method for enhanced electrical properties in hafnia based gate dielectrics," Applied Physics Letters, vol. 89, pp. 242902, 2006.

[116] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, "Application of HfSiON as a gate dielectric material," Applied Physics Letters, vol. 80, pp. 3183-3185, 2002.

[117] K. Chang Yong, L. Pat, C. Rino, L. Byoung Hun, R. Se Jong, C. Chang Hwan, M. S. Akbar, and C. L. Jack, "Nickel-silicide phase effects on flatband voltage shift and equivalent oxide thickness decrease of hafnium silicon oxynitride metal-silicon-oxide capacitors," Applied Physics Letters, vol. 86, pp. 222906, 2005.

[118] M. A. Quevedo-Lopez, M. El-Bouanani, M. J. Kim, B. E. Gnade, R. M. Wallace, M. R. Visokay, A. LiFatou, J. J. Chambers, and L. Colombo, "Effect of N incorporation on boron penetration from p[sup +] polycrystalline-Si through HfSixOy films," Applied Physics Letters, vol. 82, pp. 4669-4671, 2003.

[119] H. Momida, T. Hamada, T. Yamamoto, T. Uda, N. Umezawa, T. Chikyow, K. Shiraishi, and T. Ohno, "Effects of nitrogen atom doping on dielectric constants of Hf-based gate oxides," Appl. Phys. Lett., vol. 88, pp. 112903, 2006.

[120] M. Koyama, H. Satake, M. Koike, T. Ino, M. Suzuki, R. Iijima, Y.Kamimuta, A. Takashima, C. Hongo, and A. Nishiyama, "Degradation mechanism of HfSiON gate insulator and effect of nitrogen composition on the statistical distribution of the breakdown," presented at Tech. Dig. - Int. Electron Device Meet., 38.4.1, 2003.

[121] K. J. Yang and C. M. Hu, "MOS capacitance measurements for high-leakage thin dielectrics," Ieee Transactions on Electron Devices, vol. 46, pp. 1500-1501, 1999.

101

[122] J. R. Hauser and K. Ahmed, "Characterzation of ultra-thin oxides using electrical C-V and I-V measurements," presented at Characterization and metrology for ULSI technology, 1998.

[123] Z. M. Rittersma, J. J. G. P. Loo, Y. V. Ponomarev, M. A. Verheijen, M. Kaiser, F. Roozeboom, S. Van Elshocht, and M. Caymax, "Characterization of thermal and electrical stability of MOCVD HfO2-HfSiO4 dielectric layers with polysilicon electrodes for advanced CMOS technologies," Journal of the Electrochemical Society, vol. 151, pp. G870-G877, 2004.

[124] Y. C. Yeo, "Metal gate technology for nanoscale transistors - material selection and process integration issues," Thin Solid Films, vol. 462-63, pp. 34-41, 2004.

[125] S. Y. Son, P. Kumar, J. S. Lee, H. Cho, H. S. Jung, K. J. Min, C. J. Kang, and R. K. Singh, "An evaluation of Ti-based metal gate electrodes on Hf-silicate dielectrics for dual-metal-gate applications," Electrochemical and Solid State Letters, vol. 11, pp. H81-H83, 2008.

[126] S. J. Doh, J. H. Lee, J. P. Kim, J.-H. Lee, Y.-S. Kim, H.-J. Lim, H.-S. Jung, S. K. Han, M. J. Kim, N.-I. Lee, H.-K. Kang, S. G. Park, and S. B. Kang, "Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis," presented at IEEE International Reliability Physics Symposium, San Jose, 2005.

[127] J. Doo Seok, P. Hong Bae, and H. Cheol Seong, "Reasons for obtaining an optical dielectric constant from the Poole--Frenkel conduction behavior of atomic-layer-deposited HfO[sub 2] films," Applied Physics Letters, vol. 86, pp. 072903, 2005.

[128] D. Eom, S. Y. No, C. S. Hwang, and H. J. Kim, "Deposition characteristics and annealing effect of La2O3 films prepared using La(iPrCp)(3) precursor," Journal of the Electrochemical Society, vol. 154, pp. G49-G53, 2007.

[129] M. Liu, Q. Fang, G. He, L. Li, L. Q. Zhu, G. H. Li, and L. D. Zhang, "Effect of post deposition annealing on the optical properties of HfO[sub x]N[sub y] films," Applied Physics Letters, vol. 88, pp. 192904, 2006.

[130] Y. S. Choi, T. Nishida, and S. E. Thompson, "Impact of mechanical stress on direct and trap-assisted gate leakage current in p-type silicon metal-oxide-semiconductor capacitors," App. Physics Letters, vol. 92, 2008.

[131] H. Park, S. K. Dixit, Y. S. Choi, R. D. Schrimpf, D. M. Fleetwood, T. Nishida, and S. E. Thompson, "Total ionizing dose effects on strained HfO2-based nMOSFETs," IEEE Nuclear and Space Radiation Effects conference, 2008.

[132] L. Wen-Tai, L. Po-Ching, H. Tiao-Yuan, C. Chao-Hsin, Y. Ming-Jui, H. Ing-Jyi, and L. Peer, "The characteristics of hole trapping in HfO[sub 2]/SiO[sub 2] gate dielectrics with TiN gate electrode," Applied Physics Letters, vol. 85, pp. 3525-3527, 2004.

102

[133] H. Mayer, U. Rossler, K. Wolf, A. Elstner, H. Stanzl, T. Reisinger, and W. Gebhardt, "Strain splitting of nitrogen acceptor levels in ZnSe," Phys. Rev. B, vol. 52, pp. 4956-4964, 1995.

[134] N. Umezawa, K. Shiraishi, T. Ohno, H. Watanabe, T. Chikyow, K. Torii, K. Yamabe, K. Yamada, H. Kitajima, and T. Arikado, "First-principles studies of the intrinsic effect of nitrogen atoms on reduction in gate leakage current through Hf-based high-k dielectrics," Applied Physics Letters, vol. 86, pp. -, 2005.

[135] S. Miyazaki, T. Tamura, M. Ogasawara, H. Itokawa, H. Murakami, and M. Hirose, "Influence of nitrogen incorporation in ultrathin SiO2 on the structure and electronic states of the SiO2/Si(100) interface," Applied Surface Science, vol. 159, pp. 75-82, 2000.

[136] W. Zhang and J. G. Fossum, "On the Threshold Voltage of Strained-Si-Si1-xGex MOSFETs," IEEE Trans. Electron Devices, vol. 52, pp. 263-268, 2005.

[137] J.-S. Lim, S. E. Thompson, and J. G. Fossum, "Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs," IEEE Electron Device Lett., vol. 25, pp. 731 - 733, 2004.

[138] Y. G. Wang, D. B. Scott, J. Wu, J. L. Waller, J. Hu, K. Liu, and V. Ukraintsev, "Effects of Uniaxial Mechanical Stress on Drive Current of 0.13 m MOSFETs," IEEE Trans. Electron Devices, vol. 50, pp. 529-531, 2003.

[139] P. Zimmerman, G. Nicholas, B. D. Jaeger, B. Kaczer, A. Stesmans, R. L-A, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, "High performance Ge pMOS devices using a Si-compatible process flow," Tech. Dig. - Int. Electron Device Meet., 1-4. 2006.

[140] T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K. C. Saraswat, "High-Mobility Ultrathin Strained Ge MOSFETs on Bulk and SOI With Low Band-to-Band Tunneling Leakage: Experiments," IEEE Trans. Electron Devices, vol. 53, pp. 990-999, 2006.

[141] W. Li, M. Cai, Y. Wang, and S. Yu, "Influences of tensile strain and strain rate on the electron work function of metals and alloys," Scripta Materialia, vol. 54, pp. 921-924, 2006.

[142] V. Venkataraman, S. Nawal, and M. J. Kumar, "Compact analytical threshold-voltage model of nanoscale fully depleted strained-Si on silicon-germanium-on-insulator (SGOI) MOSFETs," IEEE Trans. Electron Devices, vol. 54, pp. 554-562, 2007.

[143] A. Ortiz-Conde, F. J. G. Sanchez, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, "A review of recent MOSFET threshold voltage extraction methods," Microelectronics Reliability, vol. 42, pp. 583-596, 2002.

[144] W. Zhao, J. He, R. Belford, L. Wernersson, and A. Seabaugh, "Partially Depleted SOI MOSFETs Under Uniaxial Tensile Strain," IEEE Trans. Electron Devices, vol. 51, pp. 317-323, 2004.

103

[145] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," IEDM Tech. Dig, pp. 247-250, 2007.

[146] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, "Application of HfSiON as a gate dielectric material," App. Physics Letters, vol. 80, pp. 3183, 2002.

[147] R. O’Connor, G. Hughes, R. Degraeve, B. Kaczer, and T. Kauerauf, "Reliability of HfSiON gate dielectrics," SEMICONDUCTOR SCIENCE AND TECHNOLOGY, vol. 20, pp. 68-71, 2005.

[148] H. Miura, S. Ikeda, and N. Suzuki, "Effect of Mechanical Stress on Reliability of Gake-Oxide Film in MOS Transistors," IEDM Tech. Dig, pp. 743, 1996.

[149] T. Irisawa, T. Numata, E. Toyoda, N. Hirashita, T. Tezuka, N. Sugiyama, and S. Takagi, "Physical Understanding of Strain Effects on Gate Oxide Reliability of MOSFETs," IEEE Trans. Very Large Scale Integr. (VLSI) syst., pp. 36, 2007.

[150] S. S. Chung, D. C. Huang, Y. J. Tsai, C. S. Lai, C. H. Tsai, P. W. Liu, Y. H. Lin, C. T. Tsai, G. H. Ma, S. C. Chien, and S. W. Sun, "New Observations on the Uniaxial and Biaxial Strain-Induced Hot Carrier and NBTI Reliabilities for 65nm Node CMOS Devices and Beyond," IEDM Tech. Dig, pp. 1, 2006.

[151] Y. T. Hou, J. C. Liao, P. F. Hsu, C. L. Hung, K. C. Lin, K. T. Huang, T. L. Lee, Y. K. Fang, and M. S. Liang, "BTI and Electron Trapping in Hf-based Dielectrics with Dual Metal Gates," IEEE International reliability physics symposium, pp. 624, 2007.

[152] K. Sasada, M. Arimoto, H. Nagasawa, A. Nishida, H. Aoe, T. Dan, S. Fujiwara, Y. Matsushita, and K. Yodoshi, "The Influence of SIN Films on Negative Bias Temperature Instability and Characteristics in MOSFET’s," IEEE International Conference on Microelectronic Test Structures, vol. 11, pp. 207, 1998.

[153] K.-W. Ang, C. Wan, K.-J. Chui, C.-H. Tung, N. Balasubramanian, M.-F. Li, G. Samudra, and Y.-C. Yeo, "HOT CARRIER RELIABILITY OF STRAINED N-MOSFET WITH LATTICE MISMATCHED SOURCE/DRAIN STRESSORS," IEEE International reliability physics symposium, pp. 684, 2007.

[154] A. Shickova, B. Kaczer, P. Verheyen, G. Eneman, E. S. Andres, M. Jurczak, P. Absil, H. Maes, and G. Groeseneken, "Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior," IEEE Electron Device Lett., vol. 28, pp. 242, 2007.

104

[155] S. Y. Son, Y. S. Choi, P. Kumar, H. W. Park, T. Nishida, R. K. Singh, and S. E. Thompson, "Strain Induced Changes in Gate Leakage Current and Dielectric Constant of Nitrided Hf-Silicate Dielectric Silicon MOS Capacitors," App. Physics Letters, accepted on Oct. 20, 2008.

[156] Y. PEI, H. MURAKAMI, S. HIGASHI, S. MIYAZAKI, S. INUMIYA, and Y. NARA, "Evaluation of Dielectric Reliability of Ultrathin HfSiOxNy in Metal-Gate Capacitors," IEICE TRANS. ELECTRON., vol. E90–C, pp. 962, 2007.

[157] R. O'Connor, R. Degraeve, B. Kaczer, A. Veloso, G. Hughes, and G. Groeseneken, "Weibull slope and voltage acceleration of ultra-thin (1.1–1.45 nm EOT) oxynitrides," Microelectronic Engineering, vol. 72, pp. 61-65, 2004.

[158] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, "Review on High-k Dielectrics Reliability Issues," IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol. 5, pp. 5-18, 2005.

[159] E. Y.Wu, E. J. Nowak, R.-P. Vollertsen, and L.-K. Han, "Weibull Breakdown Characteristics and Oxide Thickness Uniformity," IEEE Trans. Electron Devices, vol. 47, pp. 2301-2309, 2000.

[160] R. P. Vollertsen and W. G. Kleppmann, "Dependence of Dielectric Time to Breakdown Distributions on Test Structure Area," Proceedings of the IEEE Int. Conf. on Microelectronic Test Structures, vol. 4, pp. 75, 1991.

[161] S. Jeffery, C. J. Sofield, and J. B. Pethica, "The influence of mechanical stress on the dielectric breakdown field strength of thin SiO2 films," Applied Physics Letters, vol. 73, pp. 172-174, 1998.

[162] P. D. Kirsch, M. A. Quevedo-Lopez, S. A. Krishnan, B. H. Lee, G. Pant, M. J. Kim, R. M. Wallace, and B. E. Gnade, "Mobility and charge trapping comparison for crystalline and amorphous HfON and HfSiON gate dielectrics," Applied Physics Letters, vol. 89, pp. -, 2006.

[163] D. K. Schroder and J. A. Babcock, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," Journal of Applied Physics, vol. 94, pp. 1-18, 2003.

[164] B. Tuttle and R. Meade, "Microscopic Aspects of the Variations in the Retention Times of MOSFET DRAM," App. Physics Letters, vol. 90, pp. 202105, 2007.

[165] S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer, "BTI RELIABILITY OF 45 NM HIGH-K + METAL-GATE PROCESS TECHNOLOGY," IEEE International reliability physics symposium, pp. 352, 2008.

105

[166] C. Y. Lu, H. C. Lin, and T. Y. Huang, "Impacts of uniaxial compressive strain on dynamic negative bias temperature instability of p-channel MOSFETs," Electrochemical and Solid State Letters, vol. 9, pp. G138-G140, 2006.

[167] S. K. Dixit, X. J. Zhou, R. D. Schrimpf, D. M. Fleetwood, S. T. Pantelide, R. Choi, G. Bersuker, and L. C. Feldman, "Radiation induced charge trapping in ultrathin HfO2-based MOSFETs," Ieee Transactions on Nuclear Science, vol. 54, pp. 1883-1890, 2007.

[168] M. H. Cho, Y. I. Kim, D. S. Woo, S. W. Kim, M. S. Shim, Y. J. Park, W. S. Lee, and B. I. Ryu, "ANALYSIS OF THERMAL VARIATION OF DRAM RETENTION TIME," IEEE International reliability physics symposium, pp. 433, 2006.

[169] S. N. Rashkeev, D. M. Fleetwood, R. D. Schrimpf, and S. T. Pantelides, "Proton-induced defect generation at the Si-SiO2 interface," IEEE Trans. Nucl. Sci., vol. 48, pp. 2086, 2001.

[170] S. Suthram, H. R. Harris, M. M. Hussain, C. Smith, C. D. Young, J.-W. Yang, K. Mathews, K. Freeman, p. Majhi, H.-H. Tseng, R. Jammy, and S. E. Thompson, "Understanding Strain Effects on Double-Gate FinFET Drive-Current Enhancement, Hot-Carrier Reliability and Ring-Oscillator Delay Performance via Uniaxial Wafer Bending Experiments," International Symposium on VLSI-TSA, 2008.

[171] S. Dey, M. Agostinelli, C. Prasad, X. Wang, and L. Shifren, "EFFECTS OF HOT CARRIER STRESS ON RELIABILITY OF STRAINED-SI MOSFETS," IEEE International reliability physics symposium, pp. 461, 2006.

[172] J. R. Shih, J. J. Wang, K. Wu, Y. Peng, and J. Yue, "The Study of Compressive and Tensile Stress on MOSFET’s I-V, C-V Characteristics and It’s Impacts on Hot Carrier Injection and Negative Bias Temperature Instability," IEEE International reliability physics symposium, pp. 612, 2003.

106

BIOGRAPHICAL SKETCH

Younsung Choi received the B.S. degree in material science and engineering, and the M.S.

degree in physics from Yonsei University, Seoul, Korea, in 1998 and 2002, respectively. He is

currently working toward the Ph.D. degree in electrical engineering at the University of Florida,

Gainesville and has been with Dr. Thompson since 2004.

He was with the Semiconductor Research and Development Center, Samsung Electronics,

Korea, as a process engineer from 2002 to 2004. During that period, he was involved in the dry

etch process development of memory device. His current research involves electrical

characterizations and theoretical modeling of strained-Si and Ge MOS devices.