I May 1994 UILU-ENG-94-2216DAC-46

A nalog and Digital Circuits AD-A281 081]iii 111 a 11i mu nlnIII

II Timing and AreaOptimization for VLSI t DI"OP i n IELECTE'

Circuit and Layout J 0, 6.1994

Wei-Tong Chuang

I\I

I 94-20408* !1111111 II !1I11II il iL DI'CQTArrMDTC QUALM ITY 7-M

I Coordinated Science LaboratoryCollege of Engineering

"1 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN

Approvcd for Public Relcase. Distribution Unlimitcd.

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* a. NAME OF FUNDING/SPONSOUNG bSb. OFFICE SYMBOL 9. PROCUREMENT INSTRUMENT IDENTIFICATION NUMBERORGANIZATION Joint Services I Of a"'aw' 1N00014-90-J-1270Electronics Program

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11 ITE(k~0 Sacuny Qanfcag&O,Timing and Area Optimization foa VLSI Cir-. uit and Layout

12.I PERSONAL AUTHOR(S)Chuang, Wei-Tong

13a. TYPE OF REPORT 13b. TIME COVERED 14. DATE ZQREiQRT (Yow, MonmfDy) IS. PAGE COUNTTechncal FROM 8/91 O 4/94 94 149

IL SUPPLEMENTARY NOTATION

17. COSATI CODES 1. SUBJECT TERMS (Coninue on rown if necy and idmntfy by bkxa mnmber)ED GROUP SU"-RO4P Time-area optimization; VLSI layout;lierpoamngdelay estimation; sequential circuits; physical design;

placement; gate sizing19. ASRAC (Continue an revere if necemay and kihenfy by blInk mmb

(Attached)

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UNCLASSIFIED

I

I This thesis considers two problems in computer-aided design of VLSI circuits: (1) discrete gate sizingand (2) timing-driven placement improvement.

I The discrete gate-sizing problem is described as follows. A standard cell library typically containsseveral versions of any given gate type, each of which has a different gate size. We consider the prob-lem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuitarea) while meeting the timing constraints imposed on the circuit. After presenting an efficient solu-tion algorithm for combinational circuits, we examine the problem of minimizing the area of a synchro-nous sequential circuit for a given clock period specification. This is done by appropriately selecting asize for each gate in the circuit and by adjusting the delays between the central clock distribution nodeand individual flip-flops. Existing methods treat these two problems separately, which may lead tovery suboptimal solutions in some cases. We develop a novel unified approach to tackle them simul-taneously. We also address the problem of making this work applicable to very large synchronoussequential circuits by partitioning these circuits to reduce the computational complexity.

Traditionally, gate sizing is performed before the actual physical design steps are performed. A draw-back of such an approach is that the interconnect wire lengths are not available at the gate-sizing stage.The gate sizes selected to be optimal at that stage may no longer be optimal later in the physical designprocess in which large interconnect capacitances are introduced at the output of each gaze. To remedythis problem, we propose a novel algorithm which performs delay and area optimization for a givencompact placement by resizing and relocating cells in the circuit layout. The algorithm combines gatesizing with the placement adjustment procedure into one formulation. Since the gate-sizing procedureis embedded within the placement adjustment process, interconnect capacitance information is includedin the gate-size selection process.I

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TIMING AND AREA OPTIMIZATION FOR VLSI CIRCUIT AND LAYOUTiII

BY

m WEI-TONG CHUANG

B.S., National Taiwan University, 19863 M.S., University of Maryland at College Park, 1989UU

THESIS

Submitted in partial fulfillment of the requirementsfor the degree of Doctor of Philosophy in Electrical Engineering

in the Graduate College of theUniversity of Illinois at Urbana-Champaign, 1994

Um Urbana, mlinois

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i Copyrigh by WeiTong Chun,+ 1994

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I TIMING AND AREA OPTIMIZATION FOR VLSI CIRCUIT AND LAYOUTWei-Tong Chuang, Ph.D.

Department of Electrical and Computer EngineeringUniversity of Illinois at Urbana-Champaign, 19945 I.N. Hajh, Advisor

3 This thesis considers two problems in computer-aided design of VLSI circuits:I (1) discrete gate sizing and (2) timing-driven placement improvement.

The discrete gate-sizing problem is described as follows. A standard cell library

I typically contains several versions of any given gate type, each of which has a different3 gate size. We consider the problem of choosing optimal gate sizes from the library to

minimize a cost function (such as total circuit area) while meeting the timing constraints

U imposed on the circuit. After presenting an efficient solution algorithm for combinational3 circuits, we examine the problem of minimizing the area of a synchronous sequentiali circuit for a given clock period specification. This is done by appropriately selecting a

size for each gate in the circuit and by adjusting the delays between the central clock

I distribution node and individual flip-flops. Existing methods treat these two problems3 separately, which may lead to very suboptimal solutions in some cases. We develop a

novel unified approach to tackle them simultaneously. We also address the problem of

making this work applicable to very large synchronous sequential circuits by partitioning

3 these circuits to reduce the computational complexity.Traditionally, gate sizing is performed before the actual physical design steps are per-

formed. A drawback of such an approach is that the interconnect wire lengths are not

I available at the gate-sizing stage. The gate sizes selected to be optimal at that stageI

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may no longer be optimal later in the physical design process in which large intercon-

i nect capacitances are introduced at the output of each gate. To remedy this problem,3 we propose a novel algorithm which performs delay and area optimization for a given

compact placement by resizing and relocating cells in the circuit layout. The algorithm

-- combines gate sizing with the placement adjustment procedure into one formulation.

Since the gate-sizing procedure is embedded within the placement adjustment process,

interconnect capacitance information is included in the gate-size selection process.

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ACKNOWLEDGMENTS.

I would like to express my sincere appreciation and thanks to my advisor, Professor

Ibrahim Hajh, for all of his assistance, technical or otherwise, patience and support that

he has provided during my studies. I would like to acknowledge him for sharing his

knowledge, insight and experience with me. I would also like to express my thanks

to Professor Sachin Sapatnekar of the Iowa State Univertisy for initially suggesting the

gate-sizing problem and for many fruitful discussions on various matters relating to the

contents of this thesis. Thanks are also due to Professors Chung Laung Liu, Farid Najm,

and Resve Saleh for serving on my committee.

I am grateful to my family for all of their help, support and tutelage. I would also

I like to thank all of my friends (who are too numerous to enumerate here), particularlyI Yao-Jen Chang, Shu-Ling Cheng, Terry Lee, Ping-Chung Li, Jaidip Singh, and Chin-Chi

Teng for making my stay in Champaign-Urbana a pleasant one.

Finally, I thank all of the members of the Digital and Analog Circuits Group at the

Coordinated Science Laboratory of the University of Illinois.

v

TABLE OF CONTENTS

CHAPTER PAGE

1 INTRODUCTION ............................... 11.1 Introduction . ................................. 11.2 The Process of Electronic System Design 2.................2

1.2.1 System design ............................ 21.2.2 Logic design ............................. 31.2.3 Circuit design .......... . ................... 41.2.4 Physical design ............................ 5

1.3 Design Styles ................................. 51.4 Standard-cell Design ............................. 81.5 Discrete Gate-Sizing Problem ........................ 9

1.5.1 Optimization for combinational circuits ................... 91.6 Optimization for Sequentia