[IEEE Software (ISPASS) - Austin, TX, USA (2011.04.10-2011.04.12)] (IEEE ISPASS) IEEE INTERNATIONAL...

1
Keynote I The Era of Heterogeneity: Are we prepared? Ravishankar Iyer, Intel Monday, April 11 2011 Abstract: Usage models and applications are rapidly changing as a new class of devices (smart phones, smart TVs, etc) and rich cloud computing services (on datacenter servers) enter the marketplace. In this talk, I will start by describing some key examples of these radical changes in usage models, applications and devices. I will then highlight why the next decade of computing (clients and servers) will be based on heterogeneous architectures consisting of asymmetric cores, accelerators and hybrid cache/memory structures. The rest of the talk will be an in-depth discussion of the power/performance analysis challenges for heterogeneous architectures, such as (i) how do we analyze applications to determine the right mix of cores and accel- erators, (ii) how do we provide performance/power prediction techniques for efficient OS scheduling on heterogeneous architectures?, (iii) how do we enable runtimes and applications to achieve the required QoS on heterogeneous architectures?, (iv) how do simulation/emulation methodologies and infrastructure have to change for rapid and consistent heterogeneous architecture exploration? For each of these, I will also give examples of work that is on-going and outline potential areas for future work on performance/power analysis for heterogeneous architectures. Speaker Bio: Ravi Iyer is a Principal Engineer and Director of SoC Platform Architecture research group in Intel Labs. His research focus is on future SoC and CMP architectures, with specific emphasis on small cores, accelerators, cache/memory hierarchies, fabrics, QoS, emerging applications and performance evaluation. He has published 120+ papers and has filed 30+ patent applications. He will serve as the General Co-Chair for ISCA 2011 and was the Program Co-Chair for ANCS 2010. He is also an Associate Editor for ACM TACO and was previously an Associate Editor for IEEE TPDS. He has served on program committees for many conferences and workshops. Ravi received his Ph.D. in Computer Science from Texas A&M University. 1 978-1-61284-368-1/11/$26.00 ©2011 IEEE

Transcript of [IEEE Software (ISPASS) - Austin, TX, USA (2011.04.10-2011.04.12)] (IEEE ISPASS) IEEE INTERNATIONAL...

Page 1: [IEEE Software (ISPASS) - Austin, TX, USA (2011.04.10-2011.04.12)] (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE - Keynote I: The era of

Keynote I

The Era of Heterogeneity: Are we prepared?Ravishankar Iyer, Intel

Monday, April 11 2011

Abstract:

Usage models and applications are rapidly changing as a new class of devices (smart phones, smart TVs,etc) and rich cloud computing services (on datacenter servers) enter the marketplace. In this talk, I willstart by describing some key examples of these radical changes in usage models, applications and devices. Iwill then highlight why the next decade of computing (clients and servers) will be based on heterogeneousarchitectures consisting of asymmetric cores, accelerators and hybrid cache/memory structures. The restof the talk will be an in-depth discussion of the power/performance analysis challenges for heterogeneousarchitectures, such as (i) how do we analyze applications to determine the right mix of cores and accel-erators, (ii) how do we provide performance/power prediction techniques for efficient OS scheduling onheterogeneous architectures?, (iii) how do we enable runtimes and applications to achieve the required QoSon heterogeneous architectures?, (iv) how do simulation/emulation methodologies and infrastructure have tochange for rapid and consistent heterogeneous architecture exploration? For each of these, I will also giveexamples of work that is on-going and outline potential areas for future work on performance/power analysisfor heterogeneous architectures.

Speaker Bio:

Ravi Iyer is a Principal Engineer and Director of SoC Platform Architecture research group in IntelLabs. His research focus is on future SoC and CMP architectures, with specific emphasis on small cores,accelerators, cache/memory hierarchies, fabrics, QoS, emerging applications and performance evaluation.He has published 120+ papers and has filed 30+ patent applications. He will serve as the General Co-Chairfor ISCA 2011 and was the Program Co-Chair for ANCS 2010. He is also an Associate Editor for ACMTACO and was previously an Associate Editor for IEEE TPDS. He has served on program committeesfor many conferences and workshops. Ravi received his Ph.D. in Computer Science from Texas A&MUniversity.

1978-1-61284-368-1/11/$26.00 ©2011 IEEE