A Novel Ultra Low–Leakage Switch forSwitched Capacitor Circuits

Mahdi Ahangarian Abhari, Student Member, IEEE, and Adib Abrishamifar, Member, IEEE

Electrical Engineering Department of Iran University of Science and Technology (IUST), Tehran, 1684613114, Iran

Abstract — The voltage drop rate in switched capacitor circuits is typically limited by OFF state of switch. Past low–leakage switch designs have assumed that subthreshold conduction and drain–to–bulk diode leakage dominate over other leakage sources. However, recent researches revealed a third important mechanism, accumulation–mode source–drain coupling, which can contribute significant leakage. This paper presents a novel switch, which minimizes the overall effect of these three leakage sources. Therefore, it is proper for high–accuracy switched–capacitor circuit applications. This switch has been simulated in 0.35-μm CMOS technology. At 3.3-V power supply, 22.07-pW total power consumption and 337-aA maximum leakage current were obtained.

Index Terms — Accumulation–mode source–drain coupling, Drain–to–Bulk Diode, Leakage Current, Low–Leakage Switch, Subthreshold Conduction, Switched Capacitor Circuit.

I. INTRODUCTION

Low–leakage switch is commonly employed in the design of accurate analog storage cells to increase hold time of the stored signal [1]. Analog storage can be easily implemented using only a capacitor and a MOS switch. This form of data storage is very compact, low–power, and precise storage technique, but is useful only for short time scales since the OFF state leakage of the MOS switch quickly degrades the stored charge [2].

Long term cells extend the storage time of short terms cells by completely counteracting MOS leakage rather than simply reducing it. Some cells contract leakage by periodically quantizing the capacitor voltage using some form of analog–to–digital conversion [2]. This scheme has the disadvantages of added circuit complexity and power due to both the analog–to–digital converter and the bussing required for multiplexing the converter among cells. A second long–term storage approach is to eliminate the MOS switch altogether by employing floating–gate technology [2], [5], [6]. The disadvantagesof this scheme are that it requires high voltages for writing to the cells which exhibits slow write time, and requires additional supporting circuitry to accomplish the writing [2]. It has been assumed in these past switch designs that subthreshold and drain–to–bulk diode leakages are the dominant conduction paths [1]. However, recent researches revealed that an accumulation–mode source–to–drain diffusion current,

which has been ignored in the previous low–leakage switch design, dominates diode leakage under many bias conditions [2].

This paper presents an approach using the floating–body technique to counteract MOS switch leakage. Section II simply introduces leakage sources of MOS transistor. Section III proposes a novel ultra low–leakage switch structure based on floating–body technique. Simulation results of the proposed switch are presented in section IV. Finally, section V concludes the paper.

II. LEAKAGE SOURCES OF MOS TRANSISTOR

Prior works on MOS switch leakage reduction has assumed that drain leakage has been dominated by subthreshold conduction and drain–to–bulk diode leakage [1]. This section not only reviews these leakagesbut also illustrate accumulation–mode source–drain coupling mechanism.

A. Subthreshold Conduction

Subthreshold current in an NMOS transistor isaccurately modeled by the following relation (VGS<<VTS):

( )- -

1-GS TS DS

t t

V V VV V

DS OSWI I e eL

κ ⎛ ⎞= ⎜ ⎟

⎝ ⎠(1)

where IOS is a process–dependent current–scaling constant, VTS is the transistors threshold voltage, W/L is its width over length ratio, and κ is a parameter which is function of the applied source–to–bulk voltage and has a magnitude less than one [1]. The threshold voltage of a MOS transistor with body effect is described by:

( )0 0TS TO SBV V Vγ φ φ= + + − (2)

and is a function of the nominal threshold voltage VTO, it’s fixed for a given technology, the applied source–to–bulk voltage VSB, γ and φ0, which both the last are process–dependent parameters.

Nothing the exponential dependence of IDS on the difference (VGS–VTS) leads to two approaches whichdrastically reduce subthreshold conduction. The first approach reduces IDS by increasing VSB, and thus VTS

Fig. 1. Empirical model of accumulation–mode NMOS leakage structure [2]. Fig. 2. Ultra low–leakage NMOS switch structure.

[1–3]. The second method takes the alternate approach which reduces IDS by VGS reduction [1].

B. Drain–to–Bulk Diode Leakage

Drain–to–bulk diode leakage for nonzero drain–to–bulk voltage is the second dominant leakage source. In an NMOS transistor, this current can be modeled to first order by the ideal diode equation:

1DB

t

VV

DB SI I e−⎡ ⎤

= − −⎢ ⎥⎣ ⎦

(3)

where IDB is the diode current, VDB is the applied voltage, IS is the diode saturation current which is constant proportion to a linear combination of the junction area and its perimeter, and Vt is the thermal voltage. Several designs have attempted to counterbalance the leakage of the opposite sign from a PMOS drain–to–bulk diode [1], [3]. This approach is well–suited to the design of low–voltage transmission gates. An alternate approach employed in design of single–transistor switches forcesVDB=0V by using external circuitry when the switch is OFF [1].

C. Accumulation–Mode Source–Drain Coupling

Equation (1) is valid only when the NMOS structure is biased in the weak inversion, but by reduction of gate–source voltage, VGS, the transistor will be bias in a different region of MOS operation known as accumulation–mode. In this region, the source–drain interaction is still quite strong [2]. Since the source and drain are symmetric terminals in the MOS transistor, the observed interaction will also be symmetric. Therefore, it suggests a significant component of the accumulation–mode leakage current is due to a coupling of the source–to–bulk diode current to the drain terminal [1], [2].

An empirical model of this accumulation–mode conduction mechanism in the NMOS transistor is shown in Fig. 1. The distributed drain–to–bulk and source–to–bulk diodes are modeled as two pairs of lumped diodes. The first diode in each pair, DSB1 and DDB1, are lumped models of the portion of the distributed diodes that only interact with the bulk. The second diode in each pair, DSB2 and DDB2, represent the portion of these distributed

diodes that only interact with the opposite MOS terminal. It is postulated that the mechanism linking these two diodes is carrier diffusion under the accumulation layer. The empirical model explains this behavior as a reduction in the cross–sectional areas of DDB2 and DSB2 due to the increasing depth of the accumulation layer with decreasing VGS [2].

A second interpretation of this empirical model is to view the coupled diodes DDB2 and DSB2 as single symmetric lateral bipolar transistor acting among the source, bulk, and drain terminals. A detailed device–physics–based characterization of this leakage mechanism could be developed based on either of these equivalent views [2].

From the symmetry of the empirical leakage model, it is expected that the accumulation–mode source/drain interaction can be minimized by ensuring that VSB=VDB. Under these conditions, the currents flowing in DDB2 and DSB2 will be equal in magnitude on opposite in direction, summing to zero like in traditional subthreshold conduction or symmetric lateral bipolar conduction [1], [2].

III. PROPOSED LOW–LEAKAGE SWITCH

A. Low–Leakage Switch Structure

The ultra low–leakage NMOS switch structure that was developed to minimize the overall leakage of all mentioned leakages, is shown in Fig. 2. This switch is proper for using in high–accuracy switched–capacitor circuits. In this structure, M1 forms the kernel of switch and M2 is the lateral transistor which was employed for leakage reduction. The basic idea of this switch is using minimum number of transistors by minimum possible dimension in signal transfer path. Thereby, minimum delay is obtainable. As it is observable in Fig. 2, transistor M1 is kernel of switch and therefore, there is only one transistor in signal transmission path. In this switch not only leakage reduction is obtained by using proper bias condition but also leakage compensation is used. Leakage reduction is performed by using proper voltage, introduced by voltage regulator, and leakage compensation is attained by using secondary leakage current path which introduced by transistor M2.Transistor M2 introduces a current path for drain leakage current of transistor M1 in OFF state. By the way there are two paths for leakage compensation of M1; drain

current of transistor M2 and current of stored signal on capacitive load. It is notable that summation of these two currents, stored signal and transistor M2, is equal to leakage current of M1 in OFF state. As mentioned before, increasing hold time of stored signal is desirable, thus generated current by stored signal should be minimized. In other words, generated current by M2should be very close to leakage current of M1 in OFF state. This condition is obtainable by biasing M2 at proper voltages which is described in the following.

In this switch, T1 and T2 are input and output nodes, respectively, and the aim is decreasing the leakage at node T2 toward circuits that are connected to this node. Minimization of the overall leakage is attainable by biasing body of M1, source and body of M2 at ground, Vref and Vcont, respectively. By choosing these voltages, the current generated by transistor M2 will overcomesignal’s current when the switch is OFF. The leakage at output node, T2, is coupled to voltage at node T1, input voltage, and variation of voltage at node T1 changes the leakage at node T2. Therefore, the influence of input signal variations should be eliminated from output node’s leakage current to attain independent output leakage current from input signal variations. This effect can be minimized by voltage regulation at body of M2. Ideal voltage for Vcont, to eliminate forementioned effect, can be obtained by:

cont DD ref inV V V V= + − (4)

where Vcont is the voltage presented at body of M2, Vin is the input voltage, and Vref =VDD /2. In this scheme, input voltage can vary from Vref toward VDD, until M1 operates at the linear region.

Data transmission in switch occurs while φ is high andthe switch is ON. During this phase, M1 and M2 are ON and OFF, respectively, thus T1 and T2 are electrically connected. When φ transmits high–to–low, M1 and M2

turn OFF and ON, respectively. Therefore, T1 and T2 are electrically disconnected, the switch is OFF. In this phase, dominant share of remained leakage is compensated with drain current of M2. Therefore, by this scheme minimization of the overall leakage for variable input voltage is reasonable.

B. Ultra Low–Power Voltage Regulator Structure

As mentioned earlier, body of M2 should be biased at Vcont, and this structure was used for proposed switch in OFF state. Thus, the voltage regulator should have ultra low–power consumption. Two structure of ultra low–power voltage regulators are shown in Fig. 3. In both structure of voltage regulators, all of transistors operate in the cutoff region. Thereby, both voltage regulators have ultra low–power consumption. For two reasons the structure of Fig. 3(a), 4T–Vcont, is superior to structure of Fig. 3(b), 3T–Vcont. First, the accuracy of Vcont introduced by 4T–Vcont is higher than 3T–Vcont and therefore, the leakage of switch with 4T–Vcont is lower than 3T–Vcont. Second, it is impossible to replace two similar cascaded transistors by a single transistor with twice channel length due to exponential dependence of current and voltage of NMOS transistor in the cutoff region. To access the same accuracy, dimension of the single transistor increases strongly which leads to increase of die size and its costs.

It is notable that all gates of transistors, except gate of transistor M4, should be connected to their sources untilboth voltage regulators, transistors M3, M4, M5, M6 in Fig. 3(a) and transistors M3, M4, M5 in Fig. 3(b), operatein the cutoff region. Therefore, this bias condition forces M4 operates in the cutoff region.

IV. SIMULATION RESULTS

This ultra low–leakage switch was simulated under Bsim3v3 model, and used it into the simulator, Hspice. It adopts 0.35-μm CMOS standard technology for simulation. The supply voltage is 3.3-V, and Vref is 1.65V. This switch was simulated with both voltage regulators of Fig. 3. For 4T–Vcont and 3T–Vcont, the maximum current leakage, 337-aA and 548-aA in input voltage range were attained, respectively. Total power consumption of proposed switch including 4T–Vcont and3T–Vcont, power consumption of switch with voltage

TABLE ISummary of Simulated Results for Novel Switch

Parameter Valuesupply voltage (VDD) 3.3Vreference voltage (Vref) 1.65Vinput voltage range (Vin) 1.65V – 2.2V4T–Vcont maximum current leakage 337aA3T–Vcont maximum current leakage 548aA4T–Vcont power consumption 22.07pW3T–Vcont power consumption 23.84pWtechnology 0.35μm, 3.3V CMOS

Fig 3. Ultra low–power voltage regulators. (a) 4T–Vcontstructure. (b) 3T–Vcont structure.

regulators, are 22.07-pW and 23.84-pW, respectively. These results are summarized in table I. In the proposed switch all of transistors and also both of voltage regulators, were sized by W/L=0.7μm/0.35μmdimensions.

There is another ultra low–leakage switch with 10-nW power consumption and 10-aA leakage which fabricated in 1.5-μm CMOS technology [2]. In this structure, the input voltage has to be close to Vref and therefore, it uses a feedback circuit which causes this higher power consumption. By simulation of mentioned switch, without feedback circuit and Vin=Vref in 0.35-μm CMOS technology, 67.2-pW power consumption and 444-aA current leakage were attained. The proposed ultra low–leakage switch, with 4T–Vcont, in comparison with Ref. [2], the same as technology, not only decreases leakage current to 76% but also has less than 33% total power consumption. There are many low leakage switches, but in comparison with Ref. [2] they have much leakage current [1–3]. Therefore, the proposed switch not only has ultra low–leakage current but also ultra low–power consumption.

V. CONCLUSION

This paper presents a novel ultra low–leakage switch by reviewing the others’ recent works on low–leakage switches. In this switch two topologies was used to minimize the overall leakage; biasing all of transistors at proper voltages and secondary leakage current pathwhich introduced by lateral transistor. Therefore a new ultra low–leakage voltage regulator was used to introduce proper voltage. Moreover, secondary path was used to compensate the rest of leakage current of initial transistor which forms the switch’s kernel. Thereby, increase in the hold time of stored signal is evident. The proposed switch has been simulated under Bsim3v3model with Hspice simulator in 0.35-μm CMOS technology. At 3.3-V power supply voltage, 22.07-pW total power consumption and 337-aA maximum leakage current was obtained.

ACKNOWLEDGEMENT

The authors would like to thank Mrs. S. Ghorbani for her precious help in grammatical correction of the paper.

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