A Critical-ConCuction-Mode Single-Stage Power-Factor-Correction Electronic Ballast*

Fengfeng Tao and Fred C. Lee Center for Power Electronics Systems

Virginia Polytechnic Institute and State University Blacksburg, VA 2406 1-0 1 1 1

Abstract- A critical-conduction-mode single-stage power- factor-correction (PFC) electronic ballast is presented in this paper. The proposed ballast combines the power-factor- correction stage with a conventional half bridge DC/AC inverter into a single-stage to reduce the cost. The power factor correction stage is a boost-like converter operating in critical conduction mode so that a high power factor is achieved naturally. By exploiting voltage divider, the ratio of line peak voltage to de-bus voltage can be chosen as a large value of near one, yet a good power factor can be achieved. Theoretical analysis and experimental results for two 45-watt fluorescent lamps are presented.

I. . INTRODUCTION

High-frequency electronic ballasts for gas discharge lamps are used widely in lighting systems today because of their merits of small size, light weight, high light luminous efficiency, no flicker, no audible noise, and long life [l]. Currently, the electronic ballast has to meet the regulation of IEC 61000-3-2 class C to reduce the line rms current and line-current harmonic distortion. The power line then can be utilized more efficiently. Usually, a two-stage approach with a PFC stage followed by a DC/AC inverter stage is used. The two-stage approach has good performances such as a near- unity power factor and wide range of line input voltage variation. Besides, the design procedure is relatively easy. The main problem of the two-stage approach is that it has more components and, thus, a high cost. This is not good for cost-sensitive products. Several single-stage PFC electronic ballasts, aimed at reducing the cost, have been proposed previously [4-lo]. In the single-stage approach, the PFC stage is combined with the DC/AC inverter stage into one single stage; one switch and its controller can be saved, and conseqwntly the cost is reduced. The most commonly used method is to combine a boost converter with the DC/AC inverter stage by sharing a common switch [4-71. A high power factor can be achieved by deliberately operating the boost inductor in the discontinuous conduction mode (DCM) with constant duty-cycle control. However, there exist several problems for the DCM operation. It draws pulsating input current and requires a relatively large input filter. Second, the peak switch current of the PFC stage is much higher, so that a

high-current rating device has to be used. In addition, the bus voltage has to be designed high enough to avoid the non- linear term of the averaged line current [ 121. High-voltage rating devices may be required. J. Alonso et al. presented a DCM flyback semi-stage as the PFC stage to solve the t h d problem [9]. However, a DCM flyback converter needs a gaped transformer and usually has a lower efficiency. M. A. CO et al. proposed a good topology where the PFC stage operates in critical conduction mode to solve the above- mentioned problems [ lo]. The problem is that a transformer is necessary to couple the bus voltage. Taking into account the transformer ratio, the peak switching current of the PFC stage is even bigger than that of DCM boost at the same power factor condition. Four fast recovery diodes are also necessary to rectify the boost inductor current. Component counts increase, which may increase the cost.

In this paper, a critical-conduction-mode single-stage PFC ballast is presented and analyzed. The presented single-stage electronic ballast employs two small capacitors as a voltage divider to half the rectified line voltage so that three-level voltage is obtained. The boost inductor is arranged in such a way that the inductor current naturally operates in critical- conduction-mode. Because of voltage divider, the effective ratio of the bus voltage to linz peak can be doubled to reduce the line current distortion [12]. The magnitude of the dc-link current is the same as that of [lo]. Like in [lo], the dc-link current frequency is twice the switching frequency and the switching ripple currents are removed with a small input filter, and the two vo1ta:e-divir' :r capacitors also fimction as filter capacitors. Compared with [ 101, the presented circuit only adds one boost inductor with a smaller value (about one- fourth), two fast recovery diodes, and two small capacitors to the non-PFC electronic ballast. It has a good performance and a low cost. In the next section, the critical-conduction-mode single-stage PFC electronic ballast is first derived. The operation principle is analyzed in Section 111. Based on the steady-state analysis, design equations are derived. Section IV provides the simulation and experimental results to verify the theoretical analysis. The paper is concluded in Section V.

This work was sponsored by Matsushita Electric Works (MEW), Ltd, JAPAN, and supported in part by the ERC Program of the National Science Foundation under Award Number EEC-973 1677.

0-7803-5864-3/00/$10.00 0 2000 IEEE 603

, -. . . -. . .. __ . .. - .- . . . . .. . . . . . . . . 11. CIRCUIT DERIVATION

Fig. la shows a conventionally used two-stage PFC electronic ballast with a boost converter followed by a series- resonant parallel-loaded inverter. The boost converter usually operates in DCM for low power applications and in CCM for high power applications. If the PFC stage is split into two cells and shares a common boost inductor, a critical- conduction-mode boost converter is obtained, which is shown in Fig. lb. Two diodes, D D ~ and DD~, are inserted in series with the voltage source to ensure unidirectional input current. TWO switches, s B 1 and SB2, operate in 180’ out of phase so that the boost inductor current never stays at zero. This makes the critical conduction mode operation for the rectified boost inductor current. However, two more switches are used, which is not desirable for low-power applications. In the literature, researchers have proposed a systematic strategy to integrate a two-stage approach into a single-stage approach to save a switch and control [4-lo]. Actually, two complementary switches already exist in the inverter stage. It is easy to combine the two boost cells with the inverter stage. Fig. 2 shows the proposed circuit. MOSFETs S1 and S2 perform the switching function of s B 1 and SB2. The function of boost diode, D B ~ and D B ~ , is performed by the body diodes of S2 and SI. Two capacitors, Cdl and Cu, function as the two rectified voltage source, Vhl and Vh2. So, with this configuration, adding two capacitors and one boost inductor can obtain a critical-conduction-mode boost converter to achieve PFC to the electronic ballast.

111. PRINCIPLE OF THE CIRCUIT

In order to simplify the analysis, some assumptions are

1)MOSFETs SI and S2 operate complementarily with a

2)The bus capacitance, CB, is large enough to be

3)Bus voltage, VB, is always higher than the line peak. 4)The voltages across the filter capacitor, Cf, and voltage

divider capacitors, Cdl and Cu, keep constant during a switching cycle since switching frequency is hgh enough that capacitor impedance is much lower than load.

made as follows.

fixed frequency of 0.5 duty ratio.

considered a voltage source.

5)The lamps are modeled as a resistor, Ria, at steady state. Based on the above assumption, the proposed circuit can

be de-coupled as two independent circuits, as shown in Fig. 3 and Fig. 4. The circuit shown in Fig. 3 is a series-resonant parallel-load inverter and was well analyzed in [2]. The circuit shown in Fig. 4 is the PFC converter. Based on the assumption 4), the voltage Vhl equals Vh2, half of the rectified line voltage, Vh. This paper will focus on the steady-state analysis of the circuit in Fig. 4.

DCM Boost PFC DCIAC Inverter (a)

~ - .__ ___ -\ I’

~ .. \

Critical-conduction-mode Boost PFC DC/AC Inverter

Fig. 1 Two-stage power-factorcorrection electronic ballast @)

Fig. 2 Critical-conduction-mode single-stage power-factor- correction electronic ballast

In steady shge, four topological stages exist in one switching cycle, as shown in Fig. 5. Key waveforms are shown in Fig. 6. The operation principle is as follows.

[to, tl+linear charging LB : Before to, switch S2 is off and body diode DI conducts the inductor current, iLb. The gate drive voltage for S1 has already been applied when Dl conducting current. At to, iLb becomes zero. The diode DDI is turned on by the voltage Vhl, and the diode D D ~ is turned off by the negative voltage (vj”l+vs-vB). The inductor current iLb linearly increases by the voltage Vinl. Fig. Sa shows the equivalent circuit.

Switch SI is turned off at tl. The positive inductor current forces the body diode D2 turn on. The negative voltage (VB-Vhl) is applied to the inductor, causing the current of iLB to decrease linearly. At time t2, the inductor current becomes

[tl, t+linear discharging LB :

604

n

- Fig. 3 Half-bridge series-resonant parallel-load inverter

iin OD1

Vi"

OD I i 3"

Vin

Fig. 5 Topological stages within one switching cycle

, zero, and ends this mode. The gate voltage should apply to S2 during this interval.

The inductor current becomes zero at time t2. The switch S2 is turned on at ZVS. The diode D D ~ is turned off by the negative voltage (Vhl+V,-VB). The inductor current linearly increases by the voltage Vh2. The equivalent circuit is shown in Fig. 5c.

Switch S2 is turned off at t3. Due to the negative inductor current iLB, the body diode of SI is forced to turn on, and diverts the inductor current from Sz to diode D1. The voltage source (VB- V,) is

[t2, t+linear charging LB :

[t3, t+linear discharging LB:

Vin

Fig. 4 Simplified critical-conduction-mode power-factor- correction converter

&v Lb

Fig. 6 Key switching waveforms of the circuit

applied to the boost inductor, Lg, and inductor current linearly decreases. The equivalent circuit is shown in Fig. 5d. This mode ends at h, where a new switching cycle begins.

From the above analysis, it can be seen that the boost inductor current iLB operates bi-directionally. The charging voltage is half of the rectified line voltage and the discharging voltage equals the bus voltage minus half of the rectified line voltage. The peak inductor current naturally follows the sinusoidal line voltage waveform. Because the ratio of charging voltage to discharging voltage is small compared with the DCM boost PFC converter at the same bus voltage, the non-linear term of the line current will be small. Due to the rectifier-bridge composed with DD,, DD2,

605

D:, and D2, the dc-link current frequency is twice the switching frequency. The ripple current can be removed with a smaller input filter than that for a DCM boost PFC converter. In the following, the equations of line current, power factor, THD, and circuit parameters are derived.

A . Input Current, power factor, and THD

one switching cycle is given by From Fig. 6 , the boost inductor peak current, I&, during

1 1 --vi,

I,, =-* (YTS -.)

(1) Lb

1 (VB -3.C)

' b

.z - -

where T, is the switching period, and .is the linear discharging time.

From (l), the linear discharging time is given by

The peak current I,,k can be obtained as I =T".(l--).V, Y n

pk 4Lb 2VB (3)

The dc-link current iin equals to half of the iLB. Due to the input filter and rectifier, the instantaneous line current equals the average dc-link current over one switching cycle, which is given by

= K . ( 1 - a .sinw,t) .a -sin w,t where

Equation (4) shows that line current will contain certain

The line rms current is given by distortion due to the non-linear term of ( 1 - a -sin q t ) .

1 "

= ' ] V p sin0 - [K(1 - a .sin e ) .a -sin Old0 K O

1 4 2 3

where y E - 7 ~ ---a

The power factor is defined as the ratio of real power to appearance power, and is given as

(7)

If displacement is assumed unit, the THD can be obtained by

THD = 1. Jr-pFz- PF

Fig. 7 and Fig. 8 show the power factor and THD curve as a function of a. The curves are the same as those in [ l o ] because the boost inductor operates in the same conduction mode if seen from the line input.

B. Circuit parameters The main circuit parameters of the proposed, circuit are

boost inductance, Lg, resonant inductance, L, and resonant

0985 , 0 1 01 0 3 0 4 0 5

J

Fig. 7 Power factor as a function of a

The input real power is given by

a, Fig. 8 Total harmonic distortion as a function of a

606

capacitance, C,.

or

where Po is the output power, and 7 is the conversion eficiency, the boost inductance, LB, can be obtained by

Based on the power balance between the input and output,

Po =7.e:, (9)

vp’ 7.Y .Ts L, =- 167~. Po

By using the fimdamental component approximation [2], the series-resonant parallel-load circuit can be described by

1 The comer frequency: w, = - JL,c,

7

0 the resonant frequency: w, = w, 1 - - d d: /? 0 the characteristic impedance: 2, =

quality factor: Q, =F 4 0 The rms lamp voltage (output voltage) is given by

The rms lamp current is given by

The peak value of the switch current (only the inverter stage is considered) is given by

0 s 2 2 ws 2 Zo *,/Qi .[1-(-) 1 +(-) 0 0 0 0

7r

The resonant tank should provide high starting voltage to start up the lamp and current limiting to stabilize lamp operation after start-up. From equation ( l l ) , the output voltage will be sufficiently high due to the very high quality factor before the fluorescent lamps are turned on. At the steady state, the resonant tank provides lamp current specified by equation (12). The lamp voltage is described by equation (1 1). Choose an operation frequency slightly greater than w,, say W , = k, - W , ; the quality factor, QL, and the characteristic impedance, Z,, can be obtained from equation (1 l), which are given by

VL The resonant inductance and capacitance is obtained as

z o .ks L. =- . , WS

k c, =s (17) z, ‘ 0 s

For a given bus voltage, VB, switchmg frequency, cy, lamp power, and ks, the resonant parameters can be calculated from (14) to (17).

Iv. SIMULATION AND EXPERIMENTAL RESULTS

The proposed critical-conduction-mode single-stage PFC electronic ballast was simulated using Pspice to verify circuit operation with 200-V, line input and 85 watt lamp power. The simulated waveforms are shown in Fig. 9. The line current is sinusoidal with non-linear distortion. The switchmg waveforms are in good agreement with the waveforms in Fig. 6. A prototype was built based on the above analysis. The lamp voltage for two lamps in series is about 230 V,, and lamp resistance is 620 S Z . If the switching frequency is selected to be 52 kHz, VB =l.lVp =3 11 V, ks = 1.05, and q =

85%, the boost inductor, LB, resonant inductor, L, and resonant capacitor, C,, can be calculated using equations (10) and (14 -17)

The parameters of the input filter and voltage divider are LB =323 pH L, =1.14 mH C, ~ 9 . 2 nH

Lrz3mH Cf=0.22 pH Cdl =Ca =0.33

Fig. 10 shows the measured line current waveform with a 0.969 power factor and 21.2% THD. The THD is worse than that of calculated results because there exists a severe reverse recovery problem near line zero crossing for diodes DD1 and DD2. However, each measured harmonic component still meets the IEC1000-3-2 Class C requirement as shown in Fig. 11. The rectified line voltage and boost inductor current waveforms are shown in Fig. 12. The envelope of the boost inductor current follows the line voltage. The measured switching-current waveform is shown in Fig. 13. It is seen that the ZVS is ensured over the line cycle. The maximum switching current is about 2.83A. The lamp current envelope is shown in Fig. 14 with a flat envelope of 1.48 crest factor. The measured efficiency is 83.7% except for filament loss.

607

k@W

21W

a

-2.1

- a m

@.Mu

111

-@.=U

-0.IKU

-1.2uu

.oomr (67 1 10 131UI 1999 t: 2 ms/div v,: 100 V/div i,: 0.5 A/div iz:58:33

Fig. 10 Measured line voltage and current waveforms

__..._._...___._____I_._.__...

! IEC 61000-3-2 class C limits 1 - 25 i E l

3 5 7 9 11 13 15 17 19

Harmonic order

Fig. 1 1 Measured line current harmonics

63 Acqs r 1

1 € " " " " " "" ' ' ' . . I ' " " ' ' ~ ' ' ' ' ' ~ ' " " I Tek 2.50MSIS

t

t: 2 ms/div v,": 100 Vdiv i : 2 A/div l 3 Os 34

Fig. 12 Measured boost inductor current envelope

TeK nun: Z.SOMS/S HI Res I' """"""""""" " ' ' . " ' " ' " ' ' ' I I r 1

i

:i_l i o o , C n a ala"/ ,M';;-; , , j . m . mr - 13Jul1999

t: 2 msldiv v,: 100 V/div is: 2 A/div 13:03:23

Fig. 13 Measured switching-current envelope

608

t

V. CONCLUSION

A critical-conduction-mode single-stage PFC electronic ballast was proposed, analyzed, and implemented in this paper. The proposed circuit has features of simple structure, critical-conduction line current, and high power factor with low harmonic distortion. The circuit also features low lamp current crest factor, and simple structure with potential low cost.

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