A 2.4-GHz Low-Power Low-IF Receiver in 0.18-CMOS for wireless sensor networl( applications

Mohsen N asri, Abdelhamid Helali, Amina Msolli, Hassen Maaref Laboratory of Micro-Optoelectronics and Nanostructures (LMON),

Faculty of Sciences of Monastir, Tunisia Mohsen l2 nasri@yahoo.fr

Abstract-In wireless sensor network applications, low-cost

and low-power operation of the wireless receiver are critical.

To address this need with high performance wireless front-end,

many intensive researches on CMOS radio-frequency (RF)

front-end circuits have been proposed. The ultimate goal is

adaptive receiver design to minimize the trade-off between

high performance and low-cost, low power consumption. In

this paper, an ultra low power receiver operating in 2.4GHz

ISM band targeting wireless sensor network applications is

presented. The proposed circuit has an integrated noise figure

of 9.97 dB. The proposed receiver consumes 9.97-mW from a

1.8-V.

Keywords- low-power RF; Low Cost; Wireless Sensor Network

1. INTRODUCTION

Advances in MicroElectroMechanical Systems (MEMS) and wireless communication have heralded the advent of sensors. Sensors are small, low-cost and low-power communication devices capable of limited computation, wireless communication, and sensing [I]. Basically, a single sensor node consists of a three main electronic blocks which are the microcontroller (MCU), an Analog-to Digital Converter (ADC) for data acquisition and RF transceiver. The sub-blocks of a sensor node are summarized in Figure. 1. The transceiver is the most power-hungry block. Consequently, a reduction in the power consumption of transceiver contributes highly to the lowering of total power budget of a node. For this reason, we target the transmitter design step to minimize the energy consumption.

Sensor ADC Microcontrollerl Storage

Battery

Figure 1. Sub-Blocks diagram of a sensor node

RF transceiver

In this paper, we will describe the design and implementation of low-power RF receiver for 2.4- GHz­band IEEE 802.15.4 standard. A low-power CMOS RF transmitter for 2.4-GHz-band IEEE 802.15.4 standard is presented in [2]. In the receiver design, trade-offs between many figures of merits such as gain, noise figure, power, impedance matching and stability must be considered. The goal of the present study is to reduce the power consumption, which leads to an increase in the battery-use time, thus prolonging network lifetime. This design is very suitable for ultra low voltage and low power circuits for RF applications. The proposed architecture is based on the CMOS technology. The principal benefits of CMOS technology are low cost and single-chip integration capability. The CMOS technology allows the integration of digital baseband processing, RF/analog circuits and system memory in the same physical silicon chip. For CMOS RF design, the inbuilt trade-offs between speed, noise and power can be remedied by concurrent system and circuit design. These characteristics agrees with the IEEE 802.15.4 PRY specification which has been developed focusing on highly integrated and low cost, low power silicon solutions. The proposed receiver architecture requires a minimum number of external components, low power consumption, ease-of-integration, silicon area and requirement of external components. The receiver design can solve the problems related to IEEE 802.15.4 standard and Zigbee technology witch address easy, low cost deployment of power-friendly and flexible implementations of a virtually unlimited number of wireless low data rate monitoring and control applications [3].

The rest of the paper is organized as follows. In Section 2, we examine the receiver architecture. Simulation results are shown in Section 3. We conclude the paper in Section 4

2. THE RECEIVER ARCHITECTURE

The choice of the architecture depends on the required wireless sensor network application performance. The receiver design related to wireless sensor network applications are classified in a three categories: (I) super­heterodyne; (2) low-intermediate frequency (Iow- IF); and (3) direct conversion [4]. The super-heterodyne architecture requires several mixers; therefore, it leads to greater power and makes the receiver implementation more complicated. This architecture is not optimal solutions for achieving the low cost, low power targets of the IEEE 802.15.4 PRY

978-1-4799-3351-8/14/$31.00 ©2014 IEEE

specification. In the direct-conversion architecture, a minimum number of external components is used such as the image rejection filter which is not needed and the IF band-pass filter is re-placed by the low-pass filter. The direct-conversion receiver architectures are not optimal solutions for achieving the low power targets of the IEEE 802.15.4 PHY specification [5].

Under such a power constraint condition, the low-IF receiver architectures are excellent candidates for completely integrated receivers with good performance at low power and small chip area. In a Low-IF receiver, the RF signal is mixed down to a nonzero, low or moderate frequency, typically a few megahertz for IEEE 802.15.4, 2.4 GHz, PHY signals. Low-IF receiver topologies have many of the desirable properties of zero-IF architectures, but avoid the DC offset and lIf-noise problems. However, the use of a non-zero IF re-introduces the image issue. Fortunately, the relatively relaxed image and neighboring channel rejection requirements of the IEEE 802.15.4 PHY can be satisfied by carefully designed low-IF receivers. The image signal and unwanted blockers are rejected by the quadrature down-conversion (complex mixing) and subsequent filters in both analog and digital domains. After the I1Q down-conversion, which enables complex signal processing in all zero-IF and low-IF receiver architectures, a wide range of solutions exists for the tasks of image rejection, analog channel filtering and analog-to-digital conversion (ADC) (Nyquist, sigma-delta, etc.). Figure 2 illustrates the block schematic of the proposed receiver.

As depicted in Figure 2, Low noise amplifier (LNA) is one of the most important and essential block in RF receivers.

).tix.eurs

LNA is the first stage of any communication receiver, and its main function is to overcome the noise problem for the subsequent stages providing enough gain to make the signal easier to process. In LNA design, trade-offs between many figures of merits such as gain, noise figure, power, impedance matching and stability must be considered. The goal of the present study is to reduce the power consumption, which leads to an increase in the battery-use time. One solution is to reduce the supply voltage [6]. Cascode topology is one of the most popular topologies used for CMOS LNA designs [7]. Using this architecture, it is easier to achieve input matching for both the power gain and the noise figure (NF). This structure is shown in Figure 3. Since, in the CMOS technologies the output impedance (ro) of the transistors is very small. The LNA should be composed of a PMOS differential cascade to increase rO as well as the gain. In the ideal case (ro > (R21IRt)), the gain can be computed as a product of the gm transconductance and the resistance of load (R21IRt). However, to obtain the wanted input impedance, ro must be considerable in front of (R21IRt).

The design creativity of the proposed circuit is using a common gate configuration. Another feature of the proposed LNA is using additional capacity C2 that makes it to be different compared to similar topologies. The added capacitance allows the adjustment of the input matching conditions. Moreover, even if the capacity C2 causes the LNA gain degradation, its use is advantageous because the effect of NF improvement is greater than the gain degradation. Therefore, the capacity C2 is added for low­power consumption and input matching. The small signal equivalent circuit of the proposed LNA is shown in Figure3. The input impedance of the LNA proposed in Figure 2 is given by the equation (1)

Channel filter

1------ tS V' RF filter

LNt\

Q

Figure 2. Receiver block diagram

LNA+

R4 +

SRC1 -=-

C3

+

�+

out+ out-

ii SRC2 L1

,-. ,

�.-.-.-.-.-.-�.-�-.-.-�

- Yin

2

2 +

R5

1 SRC3

rds1

Figure 3. Small signal equivalent circuit of the LNA.

z = V;n = (R3ig + Vc + jWLJ1) In ig ig

1

R4

i 1 = i g + g m V c et C t = (C 2 + C gs )

1 g L �Zin =R3 +-- + jwLj +_111_1

jwcl CI 1 g L

� Zin = R3 + . + jw Lj + 111 1 JW(Cgs +c2) ' (Cgs +C2)

Where, Cgs is gate-source capacitor of the transistor M2.

3. SIMULATION RESULTS AND DISCUSSION

The proposed circuit is simulated with ADS simulation

tools in O.18-l..lm CMOS. The circuit is designed for 2.4-

GHz ISM frequency band using the 2.4-2.48 GHz

bandwidth. The receiver dissipates 5.54-mA from a 1.8-V

LNA-

(I)

supply. S-parameters of the Low Noise Amplifier have

been shown in Figure 4.

-1

41 I I I I I I R-----/;/ \ /'

��

1/ V o- j

f -4

-5 n

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

freq, GHz

Figure 4. Input return loss, output return loss and reverse isolation of the proposed LNA

As the results of simulations indicate the input reflection coefficients (Sll) of -15 dB, the output reflection coefficients (S22) of -7 dB and the reverse isolation (SlZ) of -3 dB. The input and the output matchings at 2.4 GHz are very good. The Figure 5 depicts a power gain of 17 dB at 2.4 GHz for the proposed LNA. This gain meets the Zigbee requirements (2: 15dB).

20_.----------------------.---�--�----__.

1 0 , ,

-� , ..-- I

('oJ 0 H - + +-I

(f) I , I

IT) -11 U-10 I +-I ,

-20 U I I

:

-30�--_.--._--._--._--n_--._--._--._--._� QO Q5 1.0 1 5 20 25 10 15 �O �5 i O

fre q . G Hz Figure 5. Power gain of the proposed LNA

Table 1 shows a summary of the proposed 2.4 GHz CMOS

LNA characteristics. Good performance of the LNA was

obtained even at a very low noise figure of 7.2 mW.

Parameters Gain (dB) NF (dB) S II (dB) S22 (dB)

Supply voltage (V) Power (mW)

TABLE1. LNApERFORMANCES

Values -1 7

0.010

-15

-7 1. 8

7.2

Another vital performance parameter for a receiver is the noise figure. The noise figure impacts the signal sensitivity of the amplifier. In figure 6, it can be seen that the noise figure is blew 9.97 dB at 2.4 GHz.

'13

12

11

5: 1 0 ... ... --c

S ...

.9 , ,

t 7

2 2A 2. 3 3.2 3.0 4 '; A � . B 5.2 5.0 0

freq, GHz

Figure6. Noise figure

From table 2, we have observed that the proposed circuit is more meaningful in terms of power consumption and noise figure.

4. CONCLUSION

In this paper, a low-power low-cost Low-If-receiver for the 2.4-GHz-band IEEE 802.15.4 standard was presented. Then, the specifications for Low Noise Amplifier module in the receiver were assigned, which is the sensitive module. The proposed receiver was fabricated using 0.18-[.tm CMOS technology with a supply voltage of 1.8-V. The Low Noise Amplifier dissipated 7.2-mW. The proposed receiver dissipated 9.97- mW .

TABLE 2. COMPARISON OF THE SIMULA nONs RESULTS OF THE PROPOSED RECEIVER AND OTHER WORKS

Parameters 18J 19J Technology (/lm) CMOS 0.18 CMOS 0.18

Supply voltage (V) 1. 8 1. 8

Power (mW) 9 10.08

NF (dB) 5 .7

Architecture Low-IF Low-IF

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<10 6 40 9.972

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