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PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014 1

A Radiation Hardened Static RAMfor High-Energy Physics Experiments

Seyedruhollah Shojaii, Alberto Stabile, and Valentino Liberali

Abstract— This paper presents the design of a staticRAM cell in 65 nm CMOS technology. A good level ofradiation hardness against cumulative dose effects caneasily achieved by using a 65 nm technology, as the oxidethickness is thin enough to provide intrinsic radiationhardness against total ionizing dose. Single event effectscan be mitigated by using ad-hoc techniques. The SRAMis based on Dual Interlocked cells (DICE) to reduce theupset occurrence in the internal node of memory latches.Electrical simulations demonstrate a very good toleranceto single event effects.

I. Introduction

Modern high-energy physics experiments require re-liable read-out electronics in high radiation environ-ments.This work aims at a radiation hardened static RAM

(SRAM), which can work properly near the vertex of ahigh-energy physics experiment. A SRAM array basedon DICE element [1] has been designed using a 65 nmCMOS conventional technology.

II. Radiation Effects

The high radiation level within the experiment areacan produce critical effects on electronic devices. Ra-diation effects can be divided in two major categories:(1) cumulative effects due to the long time exposureto the radiation, and (2) single event effects, which aredue to a single particle interaction, and can be eitherdestructive or non destructive.

A. Cumulative Effects

Cumulative effects is mainly due to two physics phe-nomena: (1) the Total Ionization Dose (TID) and, (2)the Displacement Dose Damage (DDD). Both phenom-ena lead to a degradation of electronic performances inCMOS devices. Carrier mobility decreases and thresh-old voltage could shift. In addition, parasitic leakagecurrents could affect the functionality of transistors.Total Ionizing Dose (TID) effects can be strongly re-

duced by using a CMOS technology with thin oxides.Technologies nodes below 100 nm provide compatibleoxide thickness for this purpose. In particular, if the

S. Shojaii and V. Liberali are with the Department of Physics,Universita degli Studi di Milano, and with INFN - Sezionedi Milano, Via G. Celoria 16, 20133 Milano, Italy, Email:s.shojaii@unimi.itA. Stabile is with INFN - Sezione di Milano, Via G. Celoria 16,

20133 Milano, Italy

gate oxide of MOS transistors is thinner than 3 nm, cu-mulative dose effects can be neglected. At the 65 nmtechnology node, MOS transistors have been proven totolerate up to 200 MRad of total dose [2].

B. Single Event Upset

The two most important non destructive effects forthe SRAM are the Single Event Upset (SEU) and theMultiple Bit Upset (MBU).SEU of the logic state of memory due to ionizing radi-

ation is one of the most important limitation for mem-ory circuits. It occurs when a single particle strikes asensitive volume of a memory cell, generating sufficientcharge to cause a change in the logic state of the cell,which will remain in the wrong state until new data iswritten into the memory element.MBUs are due to simultaneous upsets of bits belong-

ing to the same byte of data, and they can be reducedby physical separation of bits [3].

C. Single Event Latch-up

In CMOS logic, the most important destructive ef-fect is the Single Event Latch-up (SEL), which is dueto a p-n-p-n structure (thyristor) which can be switchedon by the current generated by an impinging particle.Our circuit is designed to operate with a supply volt-age VDD = 1.0 V. At low supply voltage values, SELoccurrence is unlikely, unless the temperature is high.However, SEL must be avoided, as it is a destructiveeffect.SEL mitigation requires to minimize the resistance

path from substrate and wells towards the power supplynetworks. Guard ring insertion is a good solution forthis purpose [4].

III. DICE Memory Design

The DICE memory element employs circuit-level de-sign techniques to prevent SEU. A DICE memory con-tain duplicated data: nodes D and D1 in Fig. 1 are ‘ho-mologous’ nodes, as they have the same logic value (Dnand Dn1 are the homologous node pair at the oppositelogic value). If a single particle is affecting the voltageof only one of the homologous nodes in a DICE, thenthe cell will not exhibit a SEU.The layout of the DICE element is shown in Fig. 2.

To obtain a regular layout, all the MOS transistors havebeen designed with the same size, i.e., W = 200 nm and

360

Fig. 1. DICE schematic diagram.

Fig. 2. DICE layout.

L = 60 nm. PMOS transistors are placed on the topand on the bottom of the cells; NMOS transistors are

in the middle, with the pass-transistors on the left andon the right sides. The cell area is 2.2 µm × 3.3 µm.

IV. SRAM Architecture

A 256 × 256 array has been designed using the mem-ory cell illustrated in Figs. 1 and 2. The array has beenorganized in 256 bit lines and 256 word lines.

The cell selection is made by decoders. Bit line de-coders consists in two CMOS pass-transistor switchesin series, the first being controlled by the first level ofaddress selection (Ym), and the second being controlledby the second level of address section (Yn). Yn and Ym

are address buses of 16 wires in which only one wirecan assume a high logic state. Demultiplexers are usedto decode the binary bus address into Yn and Ym. Inthe same way, word line decoders are organized in twoselection levels.

A control logic has been designed to switch be-tween the write mode, the read mode and the pre-charge/equalization mode.

A sense amplifier performs a differential voltage read-ing. The output of the sense amplifier is buffered by twocascaded inverters.

V. Simulation Technique

The SRAM DICE block has been extensively simu-lated in all worst cases. Simulation results demonstratethe functionality with a good trade-off between timingand power consumption.

361

Fig. 3. Example of an area affected by parasitic currents; theblack dot marks the position of the interaction, and the colortransparency indicates the amount of generated charge.

A. Parasitic Extraction

To validate the design, RC parasitic elements havebeen extracted from the layout to perform simulationson the back-annotated netlist. Since the parasitic net-work of the complete 256 × 256 array is too large,we simulated a memory cell at position (i, j) after ex-tracting the parasitics of the i-th row, of the j-th col-umn, and of the 3 × 3 sub-array from (i − 1, j − 1) to(i + 1, j + 1). In this way, the back-annotated netlistcontains all the RC parasitics related to the simulatedcell.

B. Single-Event Charge Injection

A fault injection simulation technique has been usedto inject parasitic charge.At nanometric scale, the area ionized by the imping-

ing radiation is much larger than a single MOS transis-tor. Therefore, charge injection occurs in several neigh-boring nodes, according to layout geometry [5].The layout area of DICE elements has been divided

in 24 squares with side l = 0.55 µm, and an arrayof 5 × 5 squares is considered affected by a singleevent. This corresponds to a radius of the ionized region

NMOSD

Gn

Gp

−Qn

InC R

+Qp

C IpR

Fig. 4. Equivalent circuit for SEE.

r ≈ 1.35 µm. The total charge delivered by the radia-tion at a given position is divided among the squares,as illustrated qualitatively in Fig. 3.The charge generated by the single event is collected

by reverse-biased p-n junctions; if generation occurs inan area without junctions, then the charge will recom-bine. The electrical model of charge collection is shownin Fig. 4. Current generators In and Ip model thecharge generation occurring inside each square of thecircuit.The parasitic charges −Qn and +Qp may recom-

bine, with a time constant τ = RC (in our simula-tions, τ = 0.1 ms). If there are reverse-biased p-njunctions, they collect the charge, and the amount ofcharge collected by each junction is proportional to thearea. Voltage-controlled current generators Gn and Gpmodel the charge collected by the drain-substrate junc-tion of the NMOS transistor. The current injected intothe n side of the p-n junction is:

IGn = αn · (−Qn) · V,

where αn is a gain factor, which corresponds to the frac-tion of the total junction capacitance belonging to thenode, and V is the reverse voltage of the p-n junction.Similarly, the current injected into the p side is:

IGp = αp ·Qp · V.

C. Simulation Results

Fig. 5 shows the voltages at the internal nodes of aDICE element affected by a single event which occurs atthe position shown in Fig. 3 and delivers a total chargeQ = 1 pC.The DICE memory has been initialized at the logic

value D = 1, and charge injection occurs at simulationtime t = 2.9 µs. From simulation results, we see thatall the internal nodes are affected by Single Event Tran-sients (SETs). The larger voltage transients occur adnodes D1 and Dn1. The transient at node D1 is thelargest one, because the NMOS transistor M6 is turned

362

1.0

0.0

.5

.75

V (V

)

.25

time (us)2.901 2.9032.9 2.902

D

Dn

D1

Dn1

Fig. 5. Simulation of a single event occurring in the position indicated in Fig. 3, with a parasitic charge equal to 1 pC.

on by the rising voltage at node Dn1. In a conventional6-transistor SRAM, the SEE would have triggered anupset. However, in the DICE memory element, thePMOS and the NMOS transistors of each branch aredriven by different nodes: the PMOS transistor M2,driven by the node Dn, is not turned off by the SEE,and the DICE memory recovers the state in about 2.5ns. If no other events occur before the end of the SET,then the data is maintained.

VI. Discussion and Conclusion

A SRAM block has been designed to be used in high-energy physics experiments. A DICE memory elementhas been used to reduce SEUs, while 65 nm technologyguarantees a good level of radiation hardness againstcumulative effects. The SRAM cell has been extensivelysimulated in worst cases, including RC parasitics, andwith fault injection to simulate single events.

Simulation results demonstrate a very good toleranceto SEE. A higher robustness could be achieved by phys-ically separating homologous nodes of the single DICE,to a distance that prevents a single particle to affectboth of them: for example, by interleaving two (ormore) DICE elements [6].

Better robustness against SEL could be achieved by

using guard rings that surround completely the NMOStransistors in the substrate and the PMOS transistorsinside n-wells, at the expense of a larger silicon areaand of an increase of routing complexity.

References

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[2] S. Bonacini, P. Valerio, R. Avramidou, R. Ballabriga,F. Faccio, K. Kloukinas, and A. Marchioro, “Characterizationof a commercial 65 nm CMOS technology for SLHCapplications,” IOP J. Instr., vol. 7, pp. P01 015.1–P01 015.12,Jan. 2012. [Online]. Available: http://stacks.iop.org/1748-0221/7/i=01/a=P01015

[3] C. Calligaro, V. Liberali, A. Stabile, M. Bagatin, S. Gerardin,and A. Paccagnella, “A multi-megarad, radiation hardenedby design 512 kbit SRAM in CMOS technology,” in Proc.IEEE Int. Conf. on Microelectronics (ICM), Cairo, Egypt,Dec. 2010, pp. 375–378.

[4] A. Stabile, V. Liberali, and C. Calligaro, “Design of a rad-hard library of digital cells for space applications,” in Proc.Int. Conf. on Electronics, Circuits and Systems (ICECS),Malta, Sept. 2008, pp. 149–152.

[5] E. Do, V. Liberali, A. Stabile, and C. Calligaro, “Layout-oriented simulation of non-destructive single event effects inCMOS IC blocks,” in Proc. Eur. Conf. on Radiation andIts Effects on Components and Systems (RADECS), Bruges,Belgium, Sept. 2009, pp. 217–224.

[6] M. Haghi and J. Draper, “The 90 nm Double-DICE stor-age element to reduce single-event upsets,” in Proc. MidwestSymp. on Circ. and Syst., Cancun, Mexico, Aug. 2009, pp.463–466.