[IEEE 2013 10th International Multi-Conference on Systems, Signals & Devices (SSD) - Hammamet,...

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Abstract—Networks-on-chip represent promising communication

infrastructures for highly integrated circuits to deal with future

systems design challenges, such as interconnection difficulties,

design productivity, and power consumption. Given the

difficulties associated with the design of network on chip and the

necessary time to validate the simulation network topology, or

the choice of network topology before the implementation at RTL

level, the Transaction-level modeling has been proposed as a

framework which allows rapid exploration of several networks

topology containing different descriptions of system components.

The Transaction-level represents a modeling technique that is

intended to separate the specification of computation and

communication while providing efficient methods to implement

the various elements at different levels of abstraction. This paper

introduces a library of generic TLM models of router

components that allow constructing several types of router which

can be used later to construct several network on chip topologies

for performance evaluation purpose. It allows taking decision of

the best topology for a given traffic or application target. To

prove our approach, several router types are proposed based on

these models of components and are used to build a mesh and

STAR-RING network on chip at transaction level.

Keywords-Network on Chip; Transaction Level Modeling; TLM

router; Traffic pattern

I. INTRODUCTION

The Intercommunication platform of SoCs composed

by hundreds of cores will not be feasible using a single

shared bus or a hierarchy of buses since they both have proved

their poor scalability with system size. Moreover these two

have a limited shared bandwidth between all the cores attached

to them. To overcome these problems of complexity and

scalability, Network on Chip (NoC) appears to be an

appropriate possible solution proposed as a promising

replacement for buses and dedicated interconnects [1, 2, and 3].

This is essentially based on on-chip packet switched

communication thanks to on-chip integrated routers [4]. The

use of NoC offers several advantages such as communication

scalability, better performance, modularity and structured

communication schemes [5]. This communication platform

allows perfect flexibility and reusability in the design of

complex SoC applications and fits the natural communication

scheme of any given application.

These properties of Network-on-chip have been verified in

several research works and have been implemented in both

VHDL [6, 4] and systemC [7] description.

Given the difficulties that are associated with the

integration of complex systems, the designer is faced with new

challenges. Therefore it is necessary to validate the simulation

system before the implementation. The Transaction-level

modeling framework allows rapid exploration of several

architecture containing different descriptions of system

components. The Transaction-level represents a modeling

technique intended to separate the specification of computation

and communication while providing efficient methods for

implementing the various elements at different levels of

abstraction [8], [9].

The Transaction Level Modeling (TLM) approach has been

proposed ([10], [11], [12]) as a way to tackle firstly the

HW/SW co-design problems and secondly the early

architecture analysis. The two standards that are closely related

to TLM are the open SystemC initiative (OSCI) [13] and the

Open Core Protocol (OCP) [14], that standardizes a modeling

language and an intellectual property (IP) interface

respectively. TLM model therefore works only on function of

calling and transfer data packets. The idea is to represent as

closely as possible for the designer the overall behavior of the

circuit without going into details of the description of the

signals which are carried at Register Transfer Level (RTL).

There are many variations in the level of the chosen

abstraction. It is the same case with TLM. This latter has two

models which are PV and PVT.

. At PV level, the model contains all the necessary

information for the software development teams to work. The

PVT model includes time information that can include work on

performance analysis of the circuit, without excessively

penalizing the simulation time. In the next sction we will

present related work for communication on chip.

A MODULAR AND GENERIC ROUTER TLM

MODEL FOR SPEEDUP NETWORK-ON-CHIP

TOPOLOGY GENERATION Nourddine Abid,

wissem Chouchene

Electronics and Micro-

Electronics Laboratory

Faculty of Sciences of Monastir

Monastir University, Tunisia

Email: [email protected]

Brahim Attia,

Electronics and Micro-Electronics

Laboratory


Monastir University, Tunisia

Email: [email protected]

Abdelrim Zitouni and Rached

Tourki Electronics and Micro-

Electronics Laboratory


Monastir University,

SSD'13 1569695475

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2013 10th International Multi-Conference on Systems, Signals & Devices (SSD) Hammamet, Tunisia, March 18-21, 2013

978-1-4673-6457-7/13/$31.00 ©2013 IEEE

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II. RELATED WORKS

The idea of using TLM to describe communication in

network structures has been investigated in [15], [16] and [17],

where TLM is employed to model of the communication

between the adjacent switches on a packet’s path. While these

approaches can already improve simulation performance

significantly in comparison to RTL. A detailed description of

Methodologies of transaction level modeling with SystemC is

introduced in [18] and [19]. Communication mechanisms are

modeled as channels and presented to modules using SystemC

interface classes. Transaction requests take place by calling

interface functions of these channel models, which encapsulate

low-level details of the information exchange [18]. The authors

of [20] introduced and applied Parallel Discrete Event

Simulation techniques to build SoC simulation environment at

Transaction Level Model with Time (TLM/T) using NoC as its

interconnect architecture. In [21] a novel modeling technique,

called Result Oriented Modeling, which delivers the same

speed as TLM with fully accurate timing, is proposed. They

described the AMBA AHB bus architecture in this technique

and show its efficient simulation. Methodologies of transaction

level modeling have been already widely used in describing

electronic systems that are based on NoC. In [22], the writers

enumerated NoC characteristics to be modeled and expose

SystemC models' properties of a NoC system at several

abstraction levels. In [23], a scalable and parametrical NoC is

implemented in SystemC. The NoC is composed of resources

and routers connected by channels, with a mesh topology and

wormhole routing. In [24] and [25], the authors modeled a

MIMO-OFDM receiver at transaction level abstraction based

on NoC platform in SystemC, and then analyze and compare

the performance and complexity of the model for various

configurations in terms of throughput. Since the on-chip

interconnects topology is the key to determine the main

performance metrics of the NoC , the objective of this paper is

to build libraries of models of components that allow

constructing several type of router that can be used later to

construct several network on chip topologies for performance

evaluation propose. It allows taking decision of the best

topology for given traffic or application target. To prove our

approach, several routers type is proposed based in these

models of components and are used to build a mesh and

STAR-RING network on chip at transaction level. In the next

section will give a short introduction to TLM modeling, Mesh

topology, and detailed description of the STAR-RING

topology and routing algorithm used by it. After we will

present the TLM model proposed of router components.

Finally, the traffic generator and traffic analyzer are presented.

Section 4 presents a comparative study of the two network

topology in terms of performance evaluations using two traffic

models with the same network sizes. Finally, we conclude in

section 5 with remarks.

III. THE CONSIDERED PROPOSED TLM NETWORK ON CHIP

The connection is made through a bidirectional macro-

socket as shown in figure 1. A socket is a high level

mechanism that is introduced in the TLM 2.0 standard which

combines a port with an export to provide designers with the

facility of sending packet in two ways. Sockets belong to

protocol layer of interoperability TLM layers. The initiator and

target sockets group the TLM 2.0 interfaces including blocking

and non-blocking transport interfaces (transport layer) for both

forward and backward paths together into a single object.

Figure 1. TLM interconnection modules

The generic payload belonging to the application layer is

introduced to improve the interoperability of memory-mapped

bus models and facilitate the IP reuse of TLM2.0 IPs . It also

provides the extension mechanism which can be added to

generic payload object when generic payload attributes are not

adequate to model the full functionality of the architecture

(NoC). Moreover, it is capable of creating detailed models of

specific bus protocols, while reducing the implementation cost

and increasing the simulation speed of the whole design. The

main features of the generic payload are illustrated in figure 2.

We use in this work the mesh 2D topology with

deterministic routing function called XY routing. In this kind

of the routing, the transaction is routed in the X direction until

the destination address and the current address are equal. After,

the transaction is routed in the Y direction until it reaches the

destination router. In the X direction, the transaction is routed

to the east port or to the west port. In the Y direction, the

transaction can be routed to the north port or to south port.

Finally, the local port can route transaction to the north, south,

east, and west ports. For more information about the TLM

modeling of the mesh 2D can be found in [30].

Figure 2. TLM Generic_Payload

In this section we propose a new determinist routing

algorithm that allows obtaining a fixed diameter equal to two

hops regardless the network size and the STAR valence. The

STAR RING topology is characterized by a diameter of two

links independently of the total number of routers (N) as shown

in figure 3.

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The proposed STAR-RING topology was been build with two types of routers. The first one is used to build the ring topology and it is composed by four I/O ports numbered from 0 to 3 and positioned in a ring around the central node such presented in table I and named peripheral router.

TABLE I. I/O PORTS ATTRIBUTE

Reference Port Symbol

0 Local Port L

1 CLOCKWISE Port CW

2 COUNTER CLOCKWISE

Port

CCW

3 ACCROSS Port AC

The second router is the star router with high radix valence.

The number of its I/O ports is equal to the number of the

routers placed in the ring plus one. It has V+1 I/O ports from

numbered from 0 to V with their local port has the value V.

The figure 7 present a star router with 9 input ports. It uses a

local port and 8 ports to connect the star router with the 8

peripheral routers.

As shown in figure 4 each peripheral router uses 4 ports.

The first one is the local port where the IP core is connected.

The others ports are used to connect the peripheral router with

neighboring routers called respectively CW port and CCW

port, and AC port. The AC port establishes the connection

between peripheral router and the STAR router.


When a peripheral router initiate a transaction through its

local port to other router, the routing function of the initiator

router computes the address difference between initiator and

target address, if the difference are greater than 2 or smaller

than -2 the routing function send a request to the Across port

and the transaction are routed to the STAR router. It will be

routed later to the destination peripheral router. When the

difference is equal to 1 or 2 then the transaction will be routed

to the CW port. Finally if the difference is equal to -1 or -2 then

the transaction will be routed to the CCW port. The next figure

presents the pseudo code used to implement the routing

function for local port.

All the peripheral routers can send transaction to the STAR

router by using its unique address. The routing function used

by the STAR router is not the same. When the local port of the

STAR router wants to send transaction to a peripheral router, a

connection is made with the across port of the destination

router through the SATR router.


The routing function of the port K of STAR router cannot route packet only for routers K-2, K-1, K+1, and K+2. The central router is connected to all routers in the ring on its peripheral ports. Figure 6 presents the pseudo code used to implement the routing function sub routine for STAR router which is different to then used by the local port.

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In order to model TLM mesh 2D or STAR RING topologies, we present in figure 9 our extension including several attributes able to perform the used routing algorithm. Moreover this extension employs priority of the transaction that can be used to improve QoS. “Adress_Port_int” attribute corresponds to the source address of the initiator module providing the transaction (Master IP) while “Adress_Port_dest” refers to the destination address of the target module (Slave IP) accepting the transaction. In fact, those parameters indicate the essential factors of the communication network specified in the routing functions. To ensure the scalability of the 2D mesh or STAR RING, we specify a setting in the template entry that indicates the number of rows and columns or the valence needed for the automatic mapping instance of the network object.


The mapping of the network instance is characterized by the interconnection of different types of routers as presented in figure 4 and figure 7. There two type of router in the STAR RING topology and 4 types of routers distributed symmetrically on the network and have the same functionality. The local port of each router is connected with an IP. As shown in Figure 11, the IP is modeled in the form of a macro- block composed by a traffic generator and traffic analyzer.


The traffic generator use an initiator socket connected to a target socket to the input port of the router. The traffic analyzer has a target socket connected to an initiator socket to the output port of the router. We note that each router processing type depends on its position with regards to the limits of the network, as shown in Figure 10. For example, the central switch has all five ports. However, each corner switch has only three ports.

Figure 9. Our TLM extension

Transaction generator: (initiator module: TG) is used to inject transactions into the network to be emulated according to the configure information. The TG generates transactions under various traffic patterns and injunction rate. Each transaction consists of a transaction command, a source address, and destination address fields. The transaction length is parameterized. The traffic patterns include stochastic traffic in uniform and non-uniform distributions (complementary traffic, hot spot traffic).

Transaction analyzer: (target module: TA) performs the following functions: When the transaction reaches the destination node, it will be transmitted into the packet target module.

In order to analyze the transmission delay, each transaction carries an attribute “delay” time stamp. The transaction generator and analyzer modules are synchronized in the simulation system with transport function call. The TA takes the time stamp out and calculates the transmission delay when the transaction reaches the destination. The TA also calculates the total transaction number and the total simulation time. These data are saved in a trace file owner to each TA.

Router: The first router type used in the mesh simulation has 5 input-output ports. Each port has two types of sockets, an initiator socket and a target socket. Indeed, each initiator socket is directly linked to a routing function, responsible for the switching of transactions. At the same time, an arbiter is placed

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upstream of each target socket in order to manage competing requests. The routing and arbiters functions, comply with the principle of internal connectivity through the mapping between the initiator sockets of the routing side, and the target sockets for the arbitration side.

Arbitration function: it is able to manage the competing request from initiators, which seek to achieve the same target module. The transport method can indeed be called simultaneously by multiple processes. This implies that a hardware implementation of the routing node must have the computing resources and infinite memory in order to simultaneously process an arbitrary number of transactions. To remedy this problem, a mutual exclusion (mutex) can be exploited in an arbitration module to manage the flow of data. The Queues can be used for the purpose of synchronization. This allows having a model with contention, which describes a realistic operation ready for synthesis.

Figure 10. Type of Network routers

In our case, the arbitration module encapsulates the functionality of a mutual exclusion from the class library SystemC scx_mutex_w_policy and a queue. These arbitrations are modeled following the approach first-come first-served. In this arbiter architecture, any request relating to a transaction, activates the verification operation to access to the shared resource. The access is permitted if the resource is free. The arbiter selects the socket initiator for the process requesting access and lock by calling the lock () function. However, any requests from other, their transactions will be temporarily buffered in the queue. Once the task of the current process is completed, the arbiter releases the access by calling the unlocked () function. This allows the arbiter to get the first transaction from queue and then notify it in order to be eligible. We note that the used arbitration has a generic parameter in terms the target number of sockets. Indeed, each arbiter has a target socket array in input and a single output socket.

Routing function: The routing functions are inherited from sc_module, and each of them has a specific function. Each function performs a comparison between the source address of the router where it is located and the destination address encapsulated in the transactions from the input ports. The difference between the properties of all modules routing is the decode_address method implementation. The Decode_address function is taken as a parameter; the destination address procures the extension of transaction and returns the index of the socket initiator initiator_socket from the table.

Figure 11. Network components

However, the index is returned, acheminemnt of the transaction is carried out by blocking transport interfaces b_transport.

IV. PERFORMANCE EVALUATION

The evaluation of interconnection networks requires the

definition of representative workload models. Our evaluation metric for analyzing the proposed TLM NoC are latency and throughput. Transport latency is defined as the time (in clock cycles) that elapses between the occurrence of a message header injection into the network at the source node and the occurrence of a tail flit reception at the destination node [26]. In order to reach the destination node from some starting source node, flits must travel through a path consisting of a set of switches and interconnect which are called stages. Depending on the source/destination pair and the routing algorithm, each message may have a different latency. Therefore, for a given packet Pi, the latency Li is defined as:

Li = receiving time (tail flit of Pi) (1)

– Sending time (header flit of Pi).

The average packet latency is used as a performance metric in our evaluation. Let F be the total number of packets reaching their destination and let Li be the latency of packet Pi, where i ranges from 1 to F. The average packet latency, Lavg, is then calculated according to the following equation:

FLLF

i iavg /1∑ =

= (2)

The throughput packet tells the rate that traffic packet can be sent across the network. For packet passing system, the throughput packet, TP, is defined as follows [24]:

( )*( )

( )*( )

Total messages completed Message lengthTP

Number of IP blocks Total time=

(3)

where Total packets completed refers to the number of whole packets that successfully arrive at their destination PCs, length Packet is measured in flits, Number of IP blocks is the number of functional IP blocks involved in the communication, and the total time is the time (in clock cycles) that elapses between the occurrence of the first packet generation and the last packet reception. Thus, throughput is measured as the fraction of the maximum load that the network is capable of physically handling. An overall throughput of TP = 1 corresponds to all end nodes receiving one flit every cycle.

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Accordingly, throughput is measured in flits/cycle/PC. Throughput signifies the maximum value of the accepted traffic and it is related to the peak data rate sustainable by the system [27].

The workload or traffic model is basically defined by three parameters: distribution of destinations, injection rate, and message length. The traffic pattern indicates the destination for the next message at each node. We use the most frequently used traffic pattern; the uniform distribution [28]. In this distribution, the probability of node i sending a message to node j is the same for all i and j, i ≠ j [29]. The case of nodes sending packets to themselves is excluded because we are interested in the packet transfers that use the network [28].

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1125

130

135

140

145

150

uniform traffic

Latency (flit/cycle/IP)

Injection rate (flits/cycle)

STAR-RIN

Mesh2D

Figure 12. Average transaction latency under Uniform traffic

Figure 12 and 13 depict the average packet latency and the throughput packet versus normalized accepted traffic for the 3 x 3 mesh 2D network sizes using the XY dimension-order routing, and STAR RING topology with a valence equal to 8 using the proposed routing algorithm, with a uniform distribution of message destinations.

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.01

0.02

0.03

0.04

0.05

0.06

0.07

Uniform traffic

Injection rate(flits/cycle)

throughput (flit/cycle/IP)

STAR-RING

mesh2D

Figure 13. Throughput under Uniform traffic

Figure 12 clearly indicates that 3 x 3 mesh network saturates at 90 %, the START RING network saturates at 80%. The STAR RING provides a better result in terms of latency than the mesh network. Figure 13 shows the variation of throughput under different injection rates. The mesh

throughput is better than the START RING network starting from 80% of injection rate because it has the lowest sensitivity to the packet drops. For injection rate greater than 80%, the latency and throughput of the mesh network is better than STAR RING network.

The second traffic pattern used is the hot spot traffic. In this type of traffic, each traffic generator sends a set of packets to other traffic analyzer with an equal probability except for a specific node (Called Hotspot) which receives packets with a greater probability. The percentage of additional packets that a hotspot node receives compared to other nodes is indicated after a hotspot name (Hotspot 100%).

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

200

400

600

800

1000

1200

Hot spot traffic

Latency (flit/cycle/IP)


STAR-RING

mesh2D

Figure 14. Average transaction latency under hotspot traffic

Figure 14 and 15 show the average packet latency and the throughput packet versus normalized accepted traffic for the 3 x 3 mesh 2D network sizes using the XY dimension-order routing, and STAR RING topology with a valence equal to 8 using proposed routing algorithm, with hot spot distribution of message destinations. The STAR router is the specific router for STAR RING network and the router (11) is the specific router for 3x3 mesh 2D network.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Hot spot traffic


throughput (flit/cycle/IP)

STAR-RING

mesh2D

Figure 15. Throughput under hotspot traffic

The mesh network outperforms STAR RING network in terms of latency and throughput the period of injection rate variation.

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V. CONCLUSION

A library of generic TLM models of router components

has been constructed. Two different topologies were

selected and analyzed using specific routing and switching

methods with systemC TLM2.0. A comparison study

aimed at exploring different topologies of networks-on-

chip has been conducted at transactional level modeling.

Simulations have been carried out to compare the metrics

of performance such as latency, throughput and network

load. The mesh 2D topology has a little increase of

throughput when compared to STAR RING network

topology in uniform traffic pattern but has a higher latency

in the same pattern of traffic. Mesh 2D network

outperforms STAR RING topology in the most of the

injection rate variation in hot spot traffic pattern because

of its regular and stable behavior. STAR RING topology

generally performs badly in most of the considered

parameters.

Other architectures will be studied and simulated for

different parameters using our library components.

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