A High Gain Flatness High Linearity Down Conversion Mixer for Ku Band Application Ro-Min Weng, Ming-Jhe Zeng, and Chun-Yu Liu

Department of Electrical Engineering National Dong Hwa University

Hualien, Taiwan romin@mail.ndhu.edu.tw

Abstract — A high linearity down-conversion mixer for

12-18GHz Ku band application is presented in this paper. The proposed mixer based on Gilbert cell obtains high gain flatness. Bias current decoupling technique is adopted to suppress noise at the output. Current-injection circuit and resonating inductors at the source of switching stage are added to improve the gain flatness and linearity. The proposed mixer is simulated with TSMC 0.18μm 1P6M CMOS process. The conversion gain of 7.32±0.8dB is achieved over the entire bandwidth. The minimum double-sideband noise figure is 17.26dB. The maximum input third-order intercept point (IIP3) is 3.5dBm at 14.5GHz. The power consumption is 6.36mW at 1.2V supply voltage. The chip size including pads for further measurement is 0.9×0.983mm2.

Index Terms —CMOS, Ku band, mixer, gain flatness, linearity.

I. INTRODUCTION

Ku band (Kurtz-under band) standard as defined by the International Telecommunication Union (ITU) is operated within 12~18GHz. Systems with Ku band standards are used for satellite communications such as broadcasting satellite televisions. Ku band downlink frequencies are from 11.7 to 12.7GHz and uplink frequencies are from 14 to 14.5GHz. Mixer is an important sub-circuit in wireless transceiver for up/down conversion of the radio/intermediate frequency signals. The main challenge in mixer design is to optimize the performance of conversion gain, linearity, noise, and isolation simultaneously. Several topologies of mixers have been proposed for CMOS radio frequency (RF) wide-band operation. One of the concepts was the bulk-injection switching which can achieve wide-band matching [1][2]. However, this technique suffers from low conversion gain and poor noise performance. The traditional Gilbert cell can also achieve wide-band operation. But the mixer has the disadvantage of low linearity [3]. In this paper, a mixer using resonating inductors and current injection techniques is provided with high conversion gain, high gain flatness and high linearity.

II. PROPOSED HIGH GAIN FLATNESS MIXER

The proposed mixer is shown in Fig. 1. The structure is derived basically from the Gilbert cell double balance mixer which has benefits of good port-to-port isolation and low even-order distortion. The circuit consists of a transconductance stage (M1 - M4), a LO switching stage (M7 -

Fig. 1 The proposed high gain flatness high linearity mixer. M10), a resistor load stage (RL1 - RL2), and an output stage (M11

- M12). The input differential RF signals are amplified by the

transconductance stage that is composed of the stacked NMOS-PMOS transistors. Large LO signals are operated as an ideal switch function to mix differential signals from RF and LO input ports.

The current injection circuit (M5 - M6) is added to improve the conversion gain and linearity [4]. M11 - M12 are common-source stages to match the output characteristic impedance of 50Ω. C1 and C3 are acted as a decoupling technique of bias current which can lower the noise figure. The parasitic capacitance at the source node of switching quads (M7 - M10) affects the mixer performance significantly. Inductors (L1-L2) are applied to resonate with the parasitic capacitance in order to improve the performance.

A. Stacked NMOS-POMS Transistors Analysis

The noise contribution of the RF input stage and the switching stage are investigated to reveals further problems. The white noise is dominated by the RF input stage. Fig.2 is the noise analysis of the stacked NMOS-PMOS transistors. In1

2 and In3

2 are the noise source of transistors M1 and M3, respectively. Vn,out2 is the noise output voltage which can be expressed as [5]

978-1-4244-9474-3/11/$26.00 ©2011 IEEE 2749

vin M1

M3

VDD

Vbvout

vin M1

M3

VDD

Vb

ro1||ro3

In32

In12

Vn,out2

Fig. 2 Noise analysis of the stacked NMOS-PMOS transistors.

23o1o3m1m

2out,n )r||r)(g

32

+g32

(KT4=V , (1)

where K=1.38×10-23J/K is the Boltzmann constant. T is the absolute temperature. As obtained from equation (1), optimizing the transconductances of M1 and M3 can reduce the noise from the RF input stage. Furthermore, stacked NMOS-PMOS topology is an efficient way to maximize the transconductance gmRF=gmn+gmp by a fixed dc voltage which improves the conversion gain and linearity. Hence, the noise can be reduced by increasing the bias current and transconductance of transistor.

B. Current Injection Analysis

Less noise is generated at the output with less current flowing through the switching stage. However, if the current from the tail current source is reduced, it contributed more noise. Current injection technique is adopted to maintain the total current of the mixer and to reduce the switching stage flicker noise. The conversion gain (CG) and the input third-order intercept point (IIP3) of the mixer are denoted as

RF,DL KIR2CGπ

≈ , (2)

K3I2

43IIP RF,D≈ , (3)

where RL is the load resistor. ID,RF is bias current of the RF input stage. These equations suggest that increasing the current of the RF input stage can improve both conversion gain and linearity simultaneously. Two PMOS transistors M5-M6 are used to provide dc current into the RF input stage.

C. Resonated Inductors Design

The parasitic capacitance at the source of the switching stage becomes larger while using the current injection technique. But the performance of the mixer is degraded in the same time. Two series inductors are placed between the RF input stage and the switching stage. Fig.3 shows the analysis of the resonated inductors. When one of the switches is on, the mixer can be approximated by a voltage-control current source. CP is the total parasitic capacitance at the source of the switching stage. The RLC network changes the rising time and falling time of the parasitic capacitance. The operation bandwidth can therefore be extended. Furthermore, the series resonated inductors provide high impedance so as

to improve the conversion gain with good gain flatness and linearity.

Fig. 3 Resonated inductors network analysis.

Fig. 4 Conversion gain from 12 to 18GHz.

Fig. 5 Conversion gain with resonating inductors L1-L2.

Fig. 6 RF input return loss (S11) from 12 to 18GHz.

2750

Fig. 7 LO input return loss (S22) from 12 to 18GHz.

Fig. 8 IF output return loss (S33) at 100MHz

III. SIMULATION RESULTS

The presented mixer is fabricated with 0.18μm TSMC CMOS RF process and is simulated by an Agilent Advanced Design System (ADS) tool. The proposed mixer is operated within 12-18GHz for Ku band application. The circuit is biased at 1.2V supply voltage.

As shown in Fig.4, with an RF power of -40dBm and an LO power of -5dBm, IF frequency of 100MHz, the conversion gain is 7.32±0.8dB. The results shows good gain flatness within full band. Fig.5 shows the conversion gain is increased by 5dB and more gain flatness when the resonated inductors are adopted.

The RF input return loss (S11), LO input return loss (S22), and IF output return loss (S33) are depicted in Fig.6, Fig.7, and Fig.8, respectively. The pre-simulation S11 is less than -9.2dB for 12 to 8GHz. The post-simulation S11 is less than -8.1dB for full-band. The pre-simulation S22 is less than -9.8dB and the post-simulation result S22 is under -9dB. The pre-simulation S33 is -11dB and the post-simulation -12dB when the IF frequency is kept at 100MHz.

IIP3 and input referred 1 dB compression point (P1dB) represent the linearity of the mixer which is illustrated in

Fig.9. The post-simulation IIP3 is around 2.05 to 3.5dB and the post-simulation P1dB is around -8.8 to -6.7dB. The linearity of the proposed mixer is improved by resonated inductors and current injection circuit.

The noise figure of the propose mixer is shown in Fig.10. The pre-simulation results of double-side band and single-side band noise figures are 18.08 to 19.06dB, 21.04 to 22.04dB, respectively. The post-simulation results of double-side band and single-side band noise figures are 17.26 to 19.65dB, 20.26 to 22.59dB, respectively. The isolations of LO-IF, LO-RF, and RF-IF are less than -30dB.

The layout of the proposed mixer is shown in Fig11. The pads on the layout are placed according on-wafer measurement. The RF and LO stages use G-S-G-S-G dual probes. The dc bias uses P-G-P-P-G-P probe. The total chip area is 0.9×0.98 mm2 including the pads. The implemented mixer consumes only 6.36mW. The performance of the proposed mixer compared to other wide band mixers is shown in Table I. It can be observed that this work has good gain flatness and high linearity.

Fig. 9 Linearity ( IIP3& P1dB) from 12 to 18GHz.

Fig.10 Noise figure (NF) from 12 to 18GHz.

2751

Fig. 11 Chip layout of the proposed mixer.

IV. CONCLUSION

In this paper, a down conversion mixer with high gain flatness and high linearity for Ku band application is presented. The proposed mixer using TSMC 0.18μm CMOS technology can be operated from 12 to 18GHz. Both bias current decoupling circuit and stacked NMOS-PMOS transistors technique are used to improve the noise figure and conversion gain. Resonated inductors are adopted to achieve good gain flatness, wide bandwidth, and high linearity. Current injection technique is adopted to maintain the total current of the mixer and to reduce the switching stage flicker noise. The simulated conversion gain is 7.32±0.8dB. The P1dB is -8.8 to -6.7dB for full band. The maximum IIP3 of 3.5dBm is achieved. The mixer demonstrates both high gain flatness and high linearity which shows that it is suitable for Ku band application.

ACKNOWLEDGEMENT

The authors wish to thank the Chip Implementation Center (CIC) of the National Applied Research Laboratories, Taiwan, R.O.C., for supporting the TSMC CMOS process, the chip implementation, and further measurement.

REFERENCES

[1] K.-H. Liang, H.-Y. Chang, and Y.-J. Chan, “A 0.5-7.5GHz Ultra Low-Voltage Low-Power Mixer Using Bulk-Injection Method by 0.18μm CMOS technology,” IEEE Microwave and Wireless Component Letters, Vol. 17, No. 7, pp.531–533, Jul. 2007.

[2] O. Schmitz., S. Hample, C. Orlob, M. Tiebout, and I. Rolfes, “Low-Voltage Bulk-Driven Mixers in 45nm CMOS for Ultra-wide-band TX and RX,” in proc. NORCHIP, pp.119–122, Nov .2008.

[3] M. Krcmar., V. Subramanian, M. Jamal Deen, and G. Boeck, “High Gain Low Noise Folded CMOS Mixer,” in proc. of the 1st European Wireless Technology Conference, pp.13-16, Oct. 2008.

[4] J. Park., C-H. Lee, B-S. Kim, and J. Laskar, “Design and Analysis of Low Flicker-Noise CMOS Mixer for Direct-Conversion Receivers,“ IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 12, pp.4372–4380, Dec. 2006.

[5] Behzad Razavie., “Design of Analog CMOS Integrated Circuits,” Mc Graw Hill.

[6] M. Lei, H. Zhang, and C. Ma, “A 6~9GHz Bi-quadrature Folded-Switching Down-Conversion Mixer for MB-OFDM UWB Application in 0.18μm CMOS Technology,” in proc. IEEE Conderence on Solid-State and Intergrated-Circuit Technology, pp.1496–1499, Oct. 2008.

[7] C.-H. Kuo, B.-H. Huang, C.-C. Kuo, K.-Y. Lin, and H. Wang, ”A 10-35GHz Low Power Bulk-Driven Mixer Using 0.13μm CMOS Process,“ IEEE Microwave and Wireless Component Letters, Vol. 18, No. 7, pp.455–457, Jun. 2008.

[8] H.-W. Chung, J.-F. Yeh, P.-H. Lien, H.-C. Kuo, and H.-R. Chuang, “Design of a 6-10GHz Low LO-Power CMOS Folded-Mirror Mixer with Link-Budget Consideration For DS-UWB Receivers,” in proc. European Conference on Radar, pp.379–376, Oct. 2008.

[9] M. M. Reja, K. Kambiz, and I. Filanovsky, “A Novel 0.6V CMOS Folded Gilbert-Cell Mixer for UWB Application,” in proc. IEEE International Conference on SOC, pp.169–172, Sept. 2008.

[10] S.-C.Tseng, C.-C. Meng, and C.-K. Wu, “GaInP/GaAs HBT Wideband Transformer Gilbert Downconverter With Low Voltage Supply,” IEEE Microwave and Wireless Component Letters, Vol7. 18, No. 7, pp.127–128, Jan. 2008.

[11] P.-Z. Rao, T.-Y. Chang, C.-P. Liang, and S.-J. Chung, “An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns ,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 9, pp.2184–2192, Sept. 2009.

[12] M. Jouri., A. Golmakani, M. Yahyabadi, and H. Khosrowjerdi, “Design and Simulation of a Down-Conversion CMOS Mixer for UWB Application,“in proc. IEEE International Conference on Telecommunication and Information Trchnology, pp.937-940, Jun. 2010.

TABLE I PERFORMANCE SUMMARY AND COMPARISOMS OF WIDE-BAND MIXERS

This work 2008[6] 2008[7] 2008[8] 2008[9] 2009[10] 2009[11] 2010[12]Technology 0.18μm 0.18μm 0.13μm 0.18μm 0.18μm GaAs HBT 0.18μm 0.18μm BW(GHz) 12-18 6-9 10-35 6-10 3.6-6.5 1.5-14 2-11 3-11 CG(dB) 7.32±0.8 14.4±0.4 -1±2 8 8.35±2.85 20 6.9±1.5 7.170.±0.65

IIP3,max(dBm) 3.5 -13.9 -4 1.5@19GHz N/A -3 6.5 4 NF,min(dB) 17.26 15.1 N/A 13.5 8 23 15.5 11 PDC(mw) 6.36 17.4 6 10.5 3.75 16.32 25.7 8.5

Area(mm2) 0.9x0.98 0.6x1.1 0.6x0.4 0.727x0.744 0.825x0.85 1x1 0.85x0.57 N/A

2752