Abstract— This paper presents a CMOS latched

comparator designed for low power analog to digital conversion application. The circuit consists of a rail-to-rail operational transconductance amplifier followed by a dynamic latch to achieve a fast, high resolution performance at low power. The regenerative latch efficiently reduces the number of gain stage needed and consumes negligibly small static power. The amplifier acts as a preamplifier providing sufficient gain to overcome dynamic offset of dynamic latch. Simulation across process and temperature variation shows the circuit has reliable operation as low as 2.7V in a standard CMOS 0.18μm mixed signal process. The circuit consumes maximum of 111μA typical current. Average delay is 2.25ns and easily operates at 10MHz. Keywords: Folded Cascode, Latched Comparator, Low Power, Rail to Rail

I. INTRODUCTION

N the recent advent of portable, battery operated devices, low power is becoming a key performance in circuit design. It enables longer battery life and minimum number of

battery cells to reduce the volume and weight of the device, thus becoming the driving factor for low power performance. In comparison with other ADC topologies, Successive Approximation ADC (SA-ADC) is the least power consuming ADC that offers high resolution at medium speed. The main analog block in SA-ADC is a comparator; which determines the performance of an ADC. Comparator easily become the main power consuming block in an ADC. This makes a power efficient comparator circuit highly desirable.

Realizing a high performance analog circuit with limitation of power is a challenge. A device’s figure of merit is illustrated by the gain-bandwidth product which states that at higher frequencies, the gain decreases. To have good gain at high frequency, higher bias current is needed. This shows that in general a fast circuit consumes high power. This inherent property prompts for specific techniques that can reduce power while maintaining performance.

A widely used approach to reduce power consumption is by using lower supply voltage, although lower supply voltage not

necessarily means reduced power dissipation for analog circuits [1]. Furthermore, process dependant parameters such as threshold voltage place limitation to low voltage circuit design. Weak inversion provides low current operation but also has high current mismatch, higher output noise, and considerably slower speed [2]. An alternative way to attain low power without subjecting to the above limitations is through power efficient topology. In the case of the comparator, possibly the most efficient topology is achieved by combining a high bandwidth (low gain) stage with a regenerative latch. This combines the high resolution, low offset properties of linear circuit with the low power, fast latching properties of the latch. Further optimization of the power performance is obtained through the relaxed amplifier requirement and optimized device design.

This paper presents the design of a latched comparator suitable for a 12-bit SA-ADC. The design uses a combination of a fully differential folded cascode amplifier followed by a dynamic latch to achieve a power-efficient operation. The comparator works at 10MHz with minimum power supply of 2.7V, with power dissipation of 111μA in a standard CMOS 0.18μm mixed signal process.

We begin this paper in section II by introducing the architecture of the proposed comparator. Simulation and results will be discussed in section III. Section IV concludes the paper.

II. LOW POWER COMPARATOR

A. Comparator Architecture For all the reasons above, a comparator based on the

architecture shown in figure 1 was designed. It consists of three functional blocks: a rail-to-rail preamplifier, a dynamic latch and a biasing circuit.

Fig. 1 Block diagram of a latched comparator.

Analysis of CMOS Differential Input to Increase ICMR of Folded Cascode Operational

Amplifier Wan Irfaan Wan Fuad and Abdul Halim Ali

University Kuala Lumpur British Malaysian Institute

I

2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), October 3-5, 2010, Penang, Malaysia

978-1-4244-7647-3/10/$26.00 ©2010 IEEE 711

The main aim for the design is to dissipate minimal current while maintaining the operation requirement. The latched topology relaxes the amplifier’s requirement; thus requiring less current. Further power reduction was achieved through optimized amplifier design. The dynamic latch design is fast and does not consume any static power. But its regenerative operation has inherent dynamic offsets and common mode noises that impair the dynamic range. The preamplifier was designed specifically to overcome this limitation. To optimize performance, a low gain and high bandwidth preamplifier was used; with power performance as its main criteria. The preamplifier senses analog input signal, VIP and VIN. It is important for the stage to have high bandwidth and high input common mode range (ICMR). The amplified signal creates sufficient overdrive INP and INN to overcome dynamic offsets and noise at latch input. The latch will then output a decision. Details of each stage are discussed in the following sections.

B. Fully Differential Rail-to-Rail Preamplifier Figure 3 shows the configuration of the input stage

preamplifier; a folded cascode OTA with rail-to-rail and fully differential configuration. The main reason folded cascode was favored is its good gain-bandwidth performance in one stage; effectively avoiding the additional power and compensation requirement of additional stages. The transconductance (gm) and output impedance (RO) are dominated by different transistors, thereby allowing gain to be increased without lowering gm that affects bandwidth. This offers optimization in the area of speed and gain.

Fig. 2 Fully differential folded cascode with complimentary differential

inputs. To achieve rail-to-rail operation, the input was configured

to the well known complimentary input pairs. Two NMOS (MN1, MN2) and PMOS (MP1, MP2) differential pairs are connected in parallel to realize the operation. When the common mode input signal is close to the rail, one of the pairs is cut off leaving only one pair to operate; while at the mid range both input pairs operate. This results to a non-constant gm. In ordinary amplifier, this effect requires additional conditioning structures such as the constant-gm structure; but for this application it was not critical [3] since the preamplifier

operates in open loop and no special linearity requirement is needed; and therefore not used. This avoids additional power requirement.

Fully differential topology used provides number of benefits especially in increasing comparator dynamic range. The larger output swing can result to higher signal-to-noise ratio. More significant improvement is cancellation to the first order of common mode noises and clocking errors; which are widespread in digital circuitry specifically in latch and ADC. The balanced circuit structure cancels systematic offset, as shown in section 3. The drawback of the topology is that it requires common mode feedback (CMFB) structure; which results to non-trivial design. A triode transistor CMFB scheme [4] was used, consisting of transistors M12 & M13. When the transistors detect common mode variations at the output nodes, they automatically adjust bias current of M10 & M11, setting the common mode back to near middle range. This solution does not need additional current requirement, though small output capacitance was imposed.

Another important consideration in the preamplifier design is the offset. Preamplifier offset determines the offset for the comparator circuit; but it is hard to be accurately characterized. Various parameters, including random variables contribute to the offset value. However through the designed topology, effective offsets are greatly reduced to random offsets. The preamplifier designed hence focused on overcoming the random offsets. Offset performance is discussed further in section 3.

C. Biasing Most of the transistors in a fully differential folded cascode

circuit require active biasing, therefore a dedicated biasing circuit usually designed. A biasing circuit shown in figure 3 was designed for the preamplifier. It takes advantage of the current source I1 supplied by the ADC. A straight forward current mirror scheme was opted. Devices are sized for overdrive voltage that optimizes cascode stage for higher speed. The minimal number of branch dissipates less current.

Fig. 3 Biasing Circuit

D. Dynamic Latch Various latch has been reported for use as comparator

712

[5][6][7]. The regenerative latch used in this work is a dynamic latch shown in Figure 4. Essentially it is formed by pair of feedback inverters (M6-M9), whose supply current is driven by pair of resistive divider (M1-M4). Clocked transistors M5 and M10 control the operation of the circuit.

Fig. 4 Dynamic Latch

The latch operates in two phases: reset and latch. When

CLK is low, the circuit enters reset phase. It is disconnected from GND by M5, effectively shutting the supply current. M10 shorts all the inverter transistor gates to their drain, forming active resistor configuration. Input signal at INP and INN biases transistors M1 and M2, creating a mismatch between resistors R1 and R2. This mismatch is characterized by:

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When CLK goes high, the circuit enters latch phase. M5 is

turned on; creating current path to GND that goes through the difference resistance at R1 and R2. Regenerative process happens when the differential current creates differential voltage at drains of M1-M4, which is being feedback to each other forcing each other into on or off state. At the same instance, M10 turned off by CLK forming cross coupled latch out of M6-M9. The differential voltage created earlier serves as the inputs of the latch and eventually VO+ and VO- will each latches to VDD or GND.

Propagation delay (tP) characterizes the speed of the latch and is very much like RC delay in digital inverters. Width and length of transistors M6-M9 is sized small to maintain low parasitic capacitance at the inverter pairs. PMOS and NMOS transistors should have ratio that give balanced push and pull between the transistors. M5 controls the current sourced. Larger current would provide slightly lower tP but also increases power consumption.

Main advantage of this circuit from other variation of latch [8] is that supply current only flows during regeneration period. Input signal path that is isolated from regenerative nodes at M1 and M4 provide lower kickback noise property compared to drain input dynamic latch [9]. Static and dynamic random offsets estimated as the main source of offset voltage and also the limiting factor for the comparator. To overcome the limitation, a preceding preamplifier is used.

III. PERFORMANCE

The targeted design performance is high accuracy, low power and high speed. Through the designed topology, the desired speed and power performance was obtained. However the accuracy criteria can only be characterized to a certain extent due to various random variables. In the designed comparator, accuracy is dominated by offset performance. In general, offset is classified into two: systematic and random offsets. Effective systematic offset which exists from finite design size was rendered zero in the fully differential circuit (figure 5 and 6). For random offsets, static mismatch occurring from variation in μCox and threshold voltage can be greatly reduced by physical layout techniques such as common centroid. Random offset involving dynamic mismatch which caused by internal node parasitic imbalance however can not be easily canceled [10]. Occurring only in transient process, normal simulation is unable to characterize the offset. Thus to overcome the limitation, a sufficiently large overdrive is generated by using preceding preamplifier. Based on previous works [5], a preamplifier with sufficient gain (64 V/V) was used.

Fig. 5 Systematic offset probed at each preamplifier output INP and INN.

Fig. 6 Effective differential output INP-INN cancels the offset.

R1 R2

Systematic offset

713

Simulation Result The proposed circuit has been simulated with Smartspice

using BSIM3 0.18μm mixed signal technology. In this technology, the threshold voltage levels are approximately 0.76V and -0.79V for NMOS and PMOS transistors respectively. Figure 7 shows the simulated transient response of the comparator for a small signal input at common mode close to GND (VIN = 0.66mV, VIP = ±0.66mV). A 10MHz, 50% duty cycle clock was used to control the dynamic latch. Preamplifier output INP and INN build up the differential signal up to 90mV in 100ns. When the clock is high, the latch enters the LATCH mode and outputs corresponding value. A delay around 3ns can be observed. The simulated circuit consumes maximum of 111μA current in normal operation.

Fig. 7 Comparator response for a differential voltage of 0.66mV (VIP =

0.66mV, VIN = 0.66mV). Across process, voltage and temperature variations,

simulation shows varying delay from 1.8ns to 6.7ns. Without constant gm and linearity, the delay was maintained minimal. Figure 8 shows current dissipation under variations. In worst process, temperature and common mode voltage variation the circuit dissipates maximum of 149μA.

Figure 8 Current dissipation at different common mode, temperature and

process variations.

IV. CONCLUSION A latched comparator suitable for low power successive

approximation ADC has been designed in a standard 0.18μm mixed signal CMOS process. The circuit combines dynamic latch preceded by a rail-to-rail fully differential preamplifier providing low offset and common mode noise performance. The circuit operates at 2.7V and consumes 111uA current. Simulation done with small signal input (0.66mV) at different

common mode, process and temperature variation shows reliable performance achieved at 10MHz. Propagation delay ranging from 1.8 to 6.7 ns has been recorded.

TABLE I

SIMULATED COMPARATOR PERFORMANCE Specifications Performance

Supply Voltage 2.7 V vIN (min) 0.66 mV

Operating Speed 10 MHz Response Time 2.3 ns

ICMR 0-2.7 V (rail-to-rail) Output Voltage Range 0-2.7 V

Supply Current 111μA Power Consumption 300μW

TABLE II

PERFORMANCE COMPARISON WITH REPORTED COMPARATOR. Chu

[11] Rang [12]

Rivoir [13]

This work

Technology (μm) 2 0.6 0.5 0.18 Supply Voltage (V) 3 5 3.3 2.7 Speed (MHz) - 3.6 10 10 Supply Current (μA) <1300 - <500 <111 Power Consumption (mW) - 6.8 - 0.3 ICMR (rail-to-rail) yes yes yes yes

REFERENCE [1] A. L. Coban, P. E. Allen, X. Shi, “Low-Voltage Analog IC

Design in CMOS Technology,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, pp 955-958, 1995.

[2] Baschirotto, A; D’Amico, S; Malcovati, P; “Low-Voltage, Low Power Basic Circuits”, Analog Circuits Design, Springer, 2006.

[3] R. Rivoir, F. Maloberti, “1mV Resolution, 10MS/s Rail-to-Rail Comparator in 0.5-um Low Voltage CMOS Digital Process,” IEEE International Symposium on Circuits and Systems, 1997.

[4] B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill Higher Education, 2001,(Chapter 9).

[5] P. Uthaichana, E. Leelarasmee, “Low Power CMOS Dynamic Latch Comparators,” Conference on Convergent Technologies for Asia-Pacific Region, 2003.

[6] L. Sumanen, M. Waltari, V. Hakkarainen, K. Halonen, “CMOS Dynamic Comparators For Pipeline A/D Converters,” IEEE International Symposium on Circuits and Systems, 2002.

[7] V. Katyal, R. L. Geiger, D. J. Chen, “A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs,” IEEE Asia Pacific Conference on Circuits and Systems, 2006.

[8] P. M. Figueiredo, J. C. Vital, “Kickback Noise Reduction Techniques for CMOS Latched Comparators”, IEEE, 2006.

[9] R.J. Baker, “CMOS Circuit Design, Layout and Simulation,” New Jersey: IEEE Press, 1998.

[10] J. He, S. Zhan, D. Chen, R. L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 911-919, 2009.

[11] W-S. Chu, K. W. Current, “A Rail-to-Rail Input Range CMOS Voltage Comparator,” Proceedings of the 40th Midwest Symposium on Circuits and Systems, 1997.

[12] Wu Rang; Wu Xiaobo; Yan Xiaolang; 2004, A dynamic CMOS comparator with high precision and resolution, Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology. Volume 2, 18-21

714

[13] R. Rivoir, F. Maloberti, “1mV Resolution, 10MS/s Rail-to-Rail Comparator in 0.5-um Low Voltage CMOS Digital Process,” IEEE International Symposium on Circuits and Systems, 1997.

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