Non-Hysteretic Ferroelectric Tunnel FET with Improved Conductance at Curie Temperature

Livio Lattanzio, Giovanni Antonio Salvatore, Adrian Mihai Ionescu Nanoelectronic Devices Laboratory (Nanolab), Ecole Poly technique Federale de Lausanne, Switzerland

livio.lattanzio@epfl.ch, adrianjonescu@epfl.ch, phone: +41 21 693 69 72 Tunnel FETs (TFETs) have attracted much interest in the last decade for their potential to be used as small slope switches

[1,2], suitable for future logic circuits operating with a supply voltage smaller than 0.5 V and for reduced IOff levels. It has

been shown that these devices highly benefit from a high gate dielectric constant, as the gate-channel capacitive coupling

is improved, positively impacting the band-to-band tunneling at low voltages [3]. Temperature-dependent performances

have also been studied: models and experiments show a slight degradation of TFET subthreshold slope and an increase in

the Ion with temperature, due to energy bandgap narrowing [4,5]. In parallel, the integration of ferroelectric materials in

MOSFET gate stacks is being considered for enhancing their subthreshold swing [6]. Furthermore, ferroelectric materials

show a unique temperature behavior. According to Landau's theory, at the Curie temperature (Tc) the relative dielectric

permittivity SF. ideally diverges [7] (Fig. 1).

In this paper we report a Tunnel FETs with a ferroelectric layer integrated in its gate stack, used as a technological

booster of the device drain current and (trans)conductance at high temperature. This is proposed and explained by the

ideal divergence of the ferroelectric permittivity around T e. P-type ferroelectric Tunnel FETs (Fe-TFETs) have been

fabricated on silicon-on-insulator (SOl) substrates with silicon film thickness of 60 nrn. The gate stack is formed by 2 nrn

thermal Si02, 5 nrn Ah03 (formed by ALD) and 30 nrn P(VDF-TrFE) 70%-30%, with an equivalent oxide thickness

(EOT) of about 14 nrn . Dimensions of the characterized device are L = 5 JUll and W = 20 JUll. Experimental Id-Vg characteristics of the Fe-TFET are presented in Fig. 2 for three different temperatures, selected

among a series of measurements from 25°C to 100°C with a step �T = 5°C, showing that hysteresis closes at 80°C. This

experiment suggests a Curie temperature, Te, of the PVDF/AhOiSi02 stack close to 80°C, where the ferroelectric

polymer loses its spontaneous polarization. This trend is confirmed in Fig. 3: the memory window (MW) of the Id-Vg is

quasi-constant till 60°C and decreases to zero for 80°C. In order to extract the MW, a threshold voltage, Vth, value is

extracted for the sweep up of the room temperature curve using the derivative method reported in [8] and the current

value corresponding to this physical Vth (where the saturation of energy barrier thinning with Vg occurs) is then used as

reference to extract the V th based at constant current for all the other curves (V th values are shown on the same plot).

Transconductance, gm, characteristics are shown from 25°C to 100°C in Fig. 4. An anomalous transconductance

improvement with the temperature is observed in Fe-TFET, in contrast with any non-ferroelectric gate stack [4,5]. The

transconductance values increase up to around 65°C and then slowly degrade, due to the combined effect of the P(VDF­

TrFE) temperature-dependent capacitance and the semiconductor bandgap narrowing. Moreover, near and beyond Te the

Fe-TFET loses his hysteretic behavior and behaves as a non-hysteretic TFET with improved gate capacitance.

The temperature dependence of device output characteristics (Fig. 5-6) confirm the same behavior observed in the

transfer characteristics, with a maximum of the drain current, �, and the output conductance, gds = dIdl dV d, in the range of

65-70°C. The Id-Vd curves show some typical behavior of a silicon-based band-to-band tunneling device: a quasi­

exponential dependence of Id on V d precedes the quasi-linear increase and the saturation region, and, also in agreement

with other reports [9], a threshold voltage is visible in the output characteristics. Decreasing current values at high

negative V d could be explained by the drain influence on the gate polarization: for high V d the gate to drain voltage, V gd,

is decreasing to zero because V g = V d = -4 V. Transfer (gmmax) and output (�max) maximum conductance values for

different temperatures are plotted in Fig. 7: the graph highlights the region where these values are larger.

Finally, in Fig. 8 the Fe-TFET point subthreshold slope (SS) values are plotted as a function of (Vg-Vth(T)) for the plots

measured by sweeping-up the gate voltage: the smallest SS values are found between 60°C and 80°C (see inset).

In conclusion, we have demonstrated for the first time that a ferroelectric gate stack can boost the current and

transconductance of a Tunnel FET at high temperatures, with maximum values near the Curie temperature of the

ferroelectric gate stack. The future engineering of the Curie temperature value of gate-integrated ferroelectric films [10]

could serve as a performance booster for integrated circuits based on Tunnel FETs operated at high temperature.

References: [I] T. Krishnamohan, IEDM 2008 [2] W. Y. Choi, IEEE EDL 2007

[3] M. Schlosser, IEEE TED 2009

[4] M. Born, MIEL 2006

[5] M. Fulde, INEC 2006

978-1-4244-7870-5/101$26.00 ©2010 IEEE 67

[6] S. Salahuddin, Nano Lett., 2007

[7] V. L. Ginzburg, Physics-Uspekhi 44 (10), 2001

[8] K. Boucart, ESSDERC 2007

[9] K. Boucart, SSE 2008

[10] V. O. Sherman, J. App. Ph., 2006

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T; Temperature [a.u.)

Fig. 1: 8-T curve for a ferroelectric layer. For T = T c

the pennittivity diverges in an ideal material, whereas

it gets large for a real material. Inset: dipoles

orientation in the P(VDF-TrFE) molecule.

10.5 -.="-.-��---.-----r�---'��"---"r-'--�,,

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Gate Voltage, Vg [V]

Fig. 2: Experimental Id-Vg measured at 25°C, 50°C

and 80°C. At T=80°C the hysteresis closes and the

Fe-TFET behaves as a non-hysteretic switch. The

inset shows the cross section of the device. 5 .£250 � :2: 200 i .g 150 c:

� 100 � � 50 Q) :2: 0

-3.2 �

ai '" -3.62 � -3.8 "0 (5 J::

-4.0 � .c I-

20 30 40 50 60 70 80 Temperature, T [0C]

Fig. 3: Memory window and threshold voltage

(sweep up and down) as a function of temperature.

The hysteresis has the same width for T < 60°C and

disappears at 80°C (VthUP = VthDOWN).

(j) -5

�· �--'-----r----r---�--m ---'25- 'C�

-' 2 -4

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�.O 4.5 4.0 �.5 �.O �.5 �.o Gate Voltage, Vg [V]

Fig. 4: Transconductance characteristics measured at

different temperatures. A maximum value of gm is

found around 65-70°C.

978-1-4244-7870-5/101$26.00 ©2010 IEEE 68

-3.S m 25'e

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Fig. 5: Experimental output characteristics measured

up to 100°C. Negative slope at high negative V d values is due to depolarization for decreasing V gd.

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Fig. 6: Output conductance (gds) characteristics

measured at different temperatures. As for gm, a

maximum value of � is found around 65-70°C.

�-4+·'···'·'····!···_··i.'·'·'·'������···.'··�········Qt·········;· ····, E '" § -3 +·,·······,··········<···········1����··········r:�:::::=1

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Fig. 7: Maximum conductance plots (gmmax and gdsmax) versus temperature for transfer and output curves. A

visible maximum is reached between 50°C and 70°C. �1000�--��---'--��������

� 950

oS 900

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(f) Gate Voltage, Vg-Vth [V] Fig. 8: Point subthreshold slope (88) versus the gate

voltage at different temperatures. The inset shows the

88 around threshold as a function of temperature, and

the range where it is minimum.