High Voltage Tolerant Integrated Buck Converter in 65nm 2.5V CMOS

Ahmed Emira1,3, Frank Carr2, Hassan Elwan2, Rania H. Mekky1

Newport Media Inc.- Cairo, Egypt1

Newport Media Inc.- Lake Forest, CA2 Faculty of Engineering, Cairo University, Cairo, Egypt3

Abstract— In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter accepts input voltage in the range 2.7-5.5V while using 2.5V devices. A low drop-out (LDO) regulator is used to limit the maximum input voltage to the DC-DC switches to protect it against overvoltage breakdown. 5MHz switching frequency is used to allow using smaller external inductors. The Buck converter is implemented in TSMC 65nm CMOS technology and it occupies 0.15mm2 while the LDO regulator, bandgap, clock generator and bias circuits occupy 0.19mm2. Up to 88% and 77% efficiency is achieved at 2.5V and 1.2V output, respectively, using 3.6V input. If the input voltage is limited to 3.3V, the LDO regulator is bypassed, and the peak efficiency becomes 92% for 2.5V and 85% for 1.2V output.

I. INTRODUCTION Small form factor and low BOM are the two most

important parameters in many of the modern highly integrated systems, such as cell phones, USB devices, etc. Standalone power management units (PMU) and even discrete regulators are still seen in most of these applications. Standalone PMU chips that integrate all regulators are becoming more popular today [1-3]. These PMU chips help reduce the PCB area compared to discrete regulator design. However, this solution is still suboptimal compared to a fully integrated design where the PMU is integrated together with the analog and digital cores in modern technologies [4]. The main obstacle to this level of integration is the PMU input voltage range. In cell phone applications, the battery voltage may range from 2.7V to 5.5V. HV devices in modern technologies such as 130nm and 65nm can sustain gate-drain or gate-source voltages up to 2.5V only. Protecting these devices when operating from 5.5V battery is a serious challenge. LiIon batteries are the most common and it’s charged at 4.2V and discharged down to 2.7V. The less common NiCd and NiMH batteries have an average voltage of 3.6V (for a three-cell battery pack with 1.2V/cell) during discharge. However, these batteries are sometimes charged using the fast pulse chargers at 5.5V peak voltage. Therefore, the Buck converter must be able to accept an input voltage as high as 5.5V to be able to operate with a wide range of battery types. Efficiency of the converter is

critical only when the battery is being discharged. While charging the battery, the input power to the DC-DC converter is drawn from the battery charger. Therefore, we aim to maximize the regulator efficiency at input voltages less than 4.2V. At higher input voltages, protection of the MOS transistors from gate-oxide voltage stress is the main concern. An overvoltage protection technique is used in the literature [4-5] by employing cascode transistors in the output switches. This technique helps raising the maximum input voltage to the Buck switches, but is not enough to protect the switches at 5.5V. Therefore, another level of protection is needed. The proposed technique in this paper is to use an LDO regulator to limit the input of the Buck converter (patent filed) to 4.2V. Lowering the maximum input voltage to the Buck converter relaxes but does not eliminate the stress on the Buck switches.

Integrating the PMU in a modern LV technology also allows using higher switching frequency. As a result, smaller off-chip reactive components can be used leading to more savings on the bill-of-material (BOM). The BOM can be even further reduced if off-chip reactive components are eventually integrated.

The architecture of the proposed DC-DC converter is presented in section II. The sub-blocks circuits are described in section III. Section IV presents the measurement results from the 65nm TSMC test chip. Finally, section V concludes the paper.

II. ARCHITECTURE Block diagram of the proposed DC-DC converter is shown

in Fig. 1. The battery voltage is directly applied to the LDO regulator to generate the regulated voltage VLDO. A 1μF external capacitor is used to stabilize the LDO output. If VBatt is less than 4.2V, the power transistor M5 in the LDO regulator operates as a switch and therefore VLDO ≅ VBatt and the LDO regulator efficiency is high. When VBatt > 4.2V, then the LDO regulator output VLDO is regulated to 4.2V. In this case, the LDO regulator power efficiency is limited by the ratio 4.2V/VBatt.

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The cascode transistors M2 and M3 are used to protect the gate-oxide of the main switches M1 and M4. The protection is achieved by biasing M2 at Vregn which is 2.5V above ground, and M3 at Vregp which is 2.5V below VLDO. M1 is driven by the pulse width modulation (PWM) signal whose peak is 2.5V. To drive the PMOS switch M4, the PWM signal low level is shifted from ground to Vregp and the high level is shifted from 2.5V to VLDO. When the NMOS switch path is ON and PMOS switch path is OFF, VSW = 0V (ignoring resistive drop across the NMOS switches). In this case, the gate-drain voltage of M1 and M2 equals Vregn. On the other hand, the gate-drain voltage of M3 is Vregp = VLDO – 2.5V. For a maximum VLDO of 4.2V, the maximum Vregp = 1.7V. Similar analysis applies when PMOS path is ON and NMOS path is OFF.

Fig. 1: DC-DC block diagram

Although the NMOS switch M1 is driven by the same voltage levels and the input PWM signal. The same level shifter is used to match the signal delay to the NMOS and PMOS switches. Excessive delay mismatch leads to high shoot-through current on one edge and long dead time on the other edge. Both effects result in more power losses.

It should be mentioned that in some cases, the input voltage to the PMU is not coming directly from the battery but from another regulator, on the PCB, which does not exceed 3.3V in most applications. Therefore, there is no need for the LDO regulator to protect the Buck switches and the input can be fed directly to the Buck converter input which is already connected to a pin. In such case the DC-DC converter efficiency improves by a few percent.

III. BLOCK DESIGN

A. LDO The LDO regulator is used to protect the DC-DC by

limiting the DC-DC supply by 4.2V if VBatt > 4.2V. For lower battery voltages, the LDO regulator acts as a switch so the regulator output follows VBatt.

Fig. 2 shows the design of the LDO regulator. M1-M4 constitute the error amplifier, M4 and M5 constitute the current mirror. M6 is the power transistor which that supplies current to the DC-DC. Bipolar biasing transistors Q1-Q4, are used because they tolerate three to four times higher voltage than NMOS transistors. The CMOS technology used in this design supports only lateral NPN transistors. As the current gain β of these NPN transistors is low (β≈5), M7 is added to cancel β-related errors in the bipolar current mirrors. The resistors R1-R4 are added for the thermal degeneration of Q1-Q4. The resistors R5-R6 are added to limit the drain-gate voltage of M1-M2 to 2.5V.

If Vbatt = 5.5V, then the drain-gate voltage of M1 is equal to 5.5V – VSG3 – VR5 – Vref. If the source-gate voltage of M3 is about 0.6V, then the voltage drop across R5 must be more than 0.4V. The gain of the LDO regulator equals two when R7 = R8. Therefore the bandgap referenced voltage Vref equals 2.1V.

The PMOS current mirror M4-M5 is used to increase the voltage swing at the gate of M6 to be able to operate at battery voltages from 2.7V to 5.5V. When Vbatt < 4.2V, Q3 pulls VG towards ground. In this case, the diodes D1-D3 turn on to limit the source-gate voltage of M6 within three diodes drop (2.1∼2.4V) for protection. The LDO regulator output is used to supply most other DC-DC blocks such as, power switches, Vregp and Vregn buffers, and level shifters.

Fig. 2: LDO B. Level Shifter

Level shifters are needed to drive the NMOS and PMOS switches as shown in Fig. 1. The level shifter to the PMOS switch shifts the PWM signal low level from ground to Vregp and the high level from Vregn to VLDO. A high voltage tolerant level shifter is reported in [5] in which the level shifting is implemented in two stages. The first stage operates in the full input supply but uses cascode devices to protect the main devices. The cascode devices limit the minimum supply voltage that can be used. A simpler but more efficient way to implement the level shifter is shown in Fig. 3 (patent filed). The input to the level shifter is the PWM signal with levels at ground/Vregn.

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The circuit consists of a cascade of CMOS inverters whose supply and ground are tapped from the resistors strings shown. The output of the first inverter is shifted to levels dV/Vregn+dV. The second inverter output is shifted to 2dV/Vregn+2dV, and so on. To ensure zero static power dissipation in the inverters, dV must be less than the minimum of VTn and |VTp|. So if dV = 0.3V, Vregn = 2.5V, and VLDO = 4.2V, then the minimum number if inverters is six. Minimum size transistors are used in the inverters, so the input capacitance of each inverter is about 1fF. If 5MHz PWM signal is used, the average dc current in each inverter is about 12.5nA. The total average dynamic current flowing into Vregn due to the eight inverters is 0.1µA. If the dc current flowing through the supply resistors is designed to be 1µA, dynamic current of the switching inverters will have a negligible effect.

C. PWM Generator The PWM generator circuit is shown in Fig. 4. The input

clock is generated from a replica circuit and has narrow pulse width. The clock pulses are used to discharge the capacitor which is then charged with a current proportional to VLDO. It can be shown that the average of the output PWM signal is expressed as:

regLDOout VT

RCDVV == (1)

where T is the clock period which is proportional to RC. Therefore the average of the PWM signal is independent of the value of VLDO. This feed-forward technique helps stabilizing the Buck regulated output in the presence of sudden changes on the battery voltage (due to turning on and off of other circuits or regulators connected to the battery) [6-7]. Frequency of the reference oscillator and PWM generator is inversely proportional to RC. Process and temperature variation result in about ±20% frequency tolerances. Measurements results shown in the next section prove that such frequency variations have less than 1% degradation on overall efficiency.

VDDout

Vregn+dVVregn+2dV

dV2dV

PWM

2.5V

0 V

RR R

R

RR R

R

GNDout

VDDin

GNDin

Fig. 3: Level shifter

Vdd/R

Vdd

Vout

M1

C

Fig. 4: PWM generation

IV. MEASUREMENT RESULTS The proposed Buck converter has been fabricated in

TSMC 65nm CMOS technology. The die photo is shown in Fig.5. The LDO regulator and power switches are placed close to the pads to minimize resistive losses due to wiring resistance. A single Buck converter with programmable output voltage is implemented. However, multiple Buck converters can be integrated by sharing the same bias circuits (e.g. LDO, bandgap reference, Vregp, and Vregn buffers). The area of the bias circuits and single Buck converters is 0.19mm2 and 0.15mm2, respectively.

Efficiency of the Buck converter for output voltages 1.2V and 2.5V is shown in Fig. 6 with and without bypassing the LDO regulator. When the battery voltage is at 4.2V and the LDO is enabled, the peak efficiencies are 88% and 77% for 2.5V and 1.2V outputs, respectively. On the other hand, when the input to the PMU is at 3.3V and LDO regulator is bypassed, the peak efficiency increases to 92% for 2.5V and 85% for 1.2V. At low load currents, current in the shared bias circuits dominate the converter losses. Therefore, the overall power efficiency improves significantly at light loads when multiple Buck converters share the bias circuits.

Fig. 7 shows the efficiency versus switching frequency at 1.2V output. Resistive losses dominate at low frequency while capacitive losses are dominant at high switching frequencies. The curve peaks at 5MHz and is reasonably flat. The high switching frequency allows using small external inductor as low as 2.2μH. The startup curve of the 1.2V regulator for 10μF load capacitor is plotted in Fig. 8 which shows no overshoot and about 25μs startup time. The feedback voltage of the Buck converter is set to 0.65V.

Fig. 5: Die photo

Bandgap

Vregn,Vregp buffers

Bias Circuits

Power

Switches

Loop Filter PWM generator

Level Shifters

LDO regulator

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The output regulated voltage can then be programmed using external resistors from 0.65V to VLDO. The Buck converter can reliably supply currents up to 250mA. The summary of measurement results is listed in Table I.

V. CONCLUSION A high-voltage tolerant, high switching frequency Buck

converter has been demonstrated. The Buck converter is integrated in TSMC 65nm CMOS process and can tolerate up to 5.5V input using 2.5V tolerant devices. The peak efficiency for 3.6V input supply is 88% and 77% at output voltages of 2.5V and 1.2V, respectively.

ACKNOWLEDGMENT The authors would like to thank Robert Perez and Justine

Lau for their help in PCB design and measurements. The authors also thank the RF team at Newport Media Inc. for their technical feedback.

0 10 20 30 40 50 60 70 80 90 1000

10

20

30

40

50

60

70

80

90

100

Load Current (mA)

Eff

icie

ncy

%

Vout=2.5V, Vbatt=4.2V, ldo enabled

Vout=1.2V, Vbatt=4.2V, ldo enabled

Vout=2.5, Vldo=3.3, ldo bypassed

Vout=1.2, Vldo=3.3, ldo bypassed

Fig. 6: Efficiency versus the load current

1 2 3 4 5 6 7 840

45

50

55

60

65

70

75

80

Frequency (MHz)

Eff

icie

ncy

%

Fig. 7: Efficiency versus the switching frequency

Fig. 8: Startup curve for the at Vout =1.2V

TABLE I PERFORMANCE SUMMARY

Technology 65nm Input range 2.7 to 5.5V Output control range 0.65 to VLDO Output current 250mA BG, LDO area 0.19mm2 Buck area 0.15mm2 Peak efficiency (Vbatt=3.6V)

88% at Vout=2.5V 77% at Vout=1.2V

Peak efficiency (LDO bypassed, VLDO =3.3V)

92% at Vout = 2.5V 85% at Vout = 1.2V

Switching frequency 5MHz

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[2] C. Shi, B. C. Walker, E. Zeisel, B. Hu, and G. McAllister, “A Higly Integrated Power Management IC for Advanced Mobile Applications,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1723-1731, Aug. 2007.

[3] M. Belloni, E. Bonizzoni, F. Maloberti, “On the Design of Single-Inductor Multiple-Output DC-DC Buck Converters,” IEEE International Symp. on Circuit and Systems, pp. 3049-3052, May 2008.

[4] O. Hazucha, S. T. Moon, S. T. Moon, G. Schrom, F. Paillet, D. Gardner, S. Rajapandian, T. Karnik, “High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters,” IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 66-73, Jan. 2007.

[5] J. Rocha, M. Santos, J. M. D. Costa, F. Lima, “High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies,” IEEE Int. Symp. on Industrial Electronics, pp. 775-780, June 2007.

[6] K. M. Smith, Z. Lai, K. M. Smedley, “A New PWM Controller with One Cycle Response,” Applied Power Electronics Conference and Exposition, vol. 2, pp. 970-976, Feb. 1997.

[7] E. Alarcon, G. Villar, E. Vidal, H. Martinez, A. Poveda, “General-Purpose One-Cycle Controller for Switching Power Converters: A High-Speed Current-Mode CMOS VLSI Implementation,” Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, vol. 1, pp. 290-293, Aug. 2001.

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