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Integrated One-Cycle Control for Three-Leg Universal Active Power Filter

Aluisio A. M. Bento, Edison R. C. da Silva* and Paulo Peixoto Praça **

* Unidade Acadêmica de Engenharia Elétrica/CEEI, Universidade Federal de Campina Grande C.P. 10.105, Campina Grande, PB, 58109-970 Brasil

Tel.: +55(83) 3310-1407, Fax: +55(83) 33101418 e-mail: aluisio@ee.ufcg.edu.br, edison@dee.ufcg.edu.br

** Departamento de Engenharia Elétrica, Universidade Federal do Ceará C.P. 6001, Fortaleza, CE, 60455-760 Brasil

Tel.: +55(85) 33669586 e-mail: paulopp@dee.ufc.br

Abstract—The power quality in grid is being deteriorated by the proliferation of nonlinear loads such as static power converters. The single-phase four-leg universal active power filter uses matching transformer, bulky and inadequate for commercial and household applications. This paper deals with a single-phase three-leg universal active power filter, without any transformer, which is controlled by OCC strategy. Besides a reduced count of components with reduced switch voltage stress, the proposed controller has fast response, stability, low cost, and operates near unity power factor.

I. INTRODUCTION

The utility ac mains suffer from increased harmonic pollution due to the increased number of nonlinear loads such as the traditional diode or thyristor rectifiers, which draw pulsate current from utility lines. On the other hand, inductive loads produce very low power factor. Besides nonlinear and inductive loads, the growing of the distributed power sources connected to the grid such as grid connected inverters, and electronic appliances generate harmonic and reactive current, which leads to low power factor, low energy efficiency, low power capacity, and harmful disturbance to other appliances. Due to this scenario international standards such as IEE519 and EN61000-3-2/4 imposed hard harmonic restrictions for ac mains utilization, which results in a focused research effort on the topic of unity power factor.

Several power quality correction techniques are available and include passive power filters, active power filters (APF) [1][2] and hybrid power filters (active plus passive). The unified power quality conditioner (also known as universal APF, UAPF), is a combination of active shunt and active series APFs that share the dc-link storage element between two voltage-source-inverters [3][4], as shown in Fig.1. In this case, the series APF part performs voltage regulation and voltage flicker/imbalance compensation at the point of common coupling, while the shunt APF part performs the harmonic current and/or negative-sequence current compensation, and dc link voltage regulation. In addition such filter can control the grid power factor near unity [2][4]. However, the use of a matching transformer at the fundamental frequency makes the system bulky and inadequate for commercial and

household applications. In the search for low cost, small size and high

efficiency, the conventional single-phase four-leg topology (Fig.1) has been replaced by an UAPF three-leg structure [5]-[12] but they use transformers.

On the other hand, there are two principal control solution types, the digital and the analog realizations. The digital technique will certainly be the preferred in future controllers due to its unlimited versatility, a number of available software tools, and decreasing cost [13]. However, during last years the analog solution has been more attractive for cost sensitive low power applications.

Figure 1. Conventional single-phase four-leg UAPF.

Figure 2. Single-phase three-leg UAPF.

978-1-4244-1668-4/08/$25.00 ©2008 IEEE

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Among the analog control techniques, the strategies based on the one-cycle control (OCC) technique produce good performance, simplicity and robustness for different power converters [14][15]. Although such technique has been successfully employed with three-phase and single-phase active and series APFs [16][17], none application has been developed for universal APF.

This paper deals with a single-phase three-leg UAPF structure without any matching transformer (Fig.2), which is controlled with a strategy conceived from OCC technique. Besides a reduced count of components with reduced voltage stress is applied to the switches, the proposed controller has nearly unity power factor, fast response, stability, and a low cost scheme. Simulated and experimental results verify the feasibility of the proposed converter.

TOPOLOGYII.

A.

This section presents some basic characteristics of a three-leg UAPF. The analysis is made for each individual structure depicted in fig. 3. Then the control strategy for the shared-leg is conceived. First the full-bridge quasi-steady transfer function is obtained, and then the control law is defined including the transfer functions for both the shunt and the series APF.

Full-bridge Transfer Function The quasi-steady-state transfer function for the full-

bridge leads to a bidirectional power flow converter. It means that the transfer function obtained is a reversible one, which can be evaluated from the inductor current variation (see Fig. 4) during a switching period. During the on-time and the off-time intervals the magnetization and demagnetization inductor current variations are given by

ONLON

Lmg tL

vI (1)

and

OFFLOFF

Ldmg tL

vI , (2)

respectively.For a switching frequency fS much greater than the

mains frequency fG, that is ,GS ff (3)

the total input current variation inside a switching period TS can be assumed to be null. By considering iLmg equal to iLdmg in (1) and (2) and because

ACDCLON vvv (4)

DCACLOFF vvv , (5)

the transfer function is computed as

)21(1

dvv

AC

DC . (6)

where

SON Ttd (7)

is the full-bridge effective duty cycle. The transfer function of the series APF is evaluated by

considering the inverse transfer function of (6), given by

Figure 3. Shared leg integrated topology.

Figure 4. Inductor current inside a switching period.

)21( dEvS . (8).

where, vS is the imposed grid serial voltage, and E is the dc-link capacitor voltage.

The pole voltages of the full bridge operating as a series APF can be symmetrically imposed by

2)21(

2

2)21(

2

42

21

Edv

v

Ed

vv

SO

SO . (9)

and the transfer function of the shunt APF is obtained by substituting vDC by E, and vAC by vO in (6). As a result

)21( dv

E O , (10)

where vO is the before regulated load voltage, given by tsenVv GOO . (11)

The pole voltages of the full bridge operating as a shunt APF can be symmetrically imposed by

2)21(

2

2)21(

2

63

42

Edv

v

Edv

v

OO

OO . (12)

B. Integrated Topology UAPF The integrated topology pole voltages are achieved in

such a way that the resulting pole-to-pole voltages v21 and v32 are equal to vS and vO, respectively. Application of this principle to (9) and (12), results in the integrated control law, given by

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2)21(

22

2)21(

22

2)21(

22

630

420

210

Edvvv

Edvvv

Edvv

v

S

I

O

SO

SO

. (13)

This distribution produces symmetrical and maximum dc-link utilization. In this case, the individual series and shunt APF controllers remain the same, but the PWM control inputs are the linear combination of the control variables.

In order to avoid over modulation, i.e. PWM saturation, the dc-link voltage E must satisfy

222

222

222

3

2

1

EVVVv

EVVVv

EVVVv

GOOO

GOOO

GOOO

, (14)

Poles 01 and 03 follow the restriction, . (15) GVE

Assuming the input-output voltage relationship given by , (16) GO nVV

equation (15) becomes

nV

E O , (17)

where n 0. Pole 02 must to be modulated in such way that,

222EVVV GOO . (18)

Substituting (16) in (18) results in

)21( nn

VE O . (19)

Since the output voltage is constant, the maximum up and down grid voltage deviations define n minimum and nmaximum, respectively.

CONTROLIII.

A.

This section analises the two control structures used in this paper.

Series APF Control Strategy Since the goal of the control is to generate a controlled

load voltage vO, the series voltage vS will be added to the grid voltage vG in order to compose the compensated sinusoidal load voltage. Because the output voltage vO is sensed, the imposed reference is obtained indirectly by *

Sv

. (20) GOS vvv **

Substitution of (20) in (9) results in the series APF open loop control law.

2)21(

2

2)21(

2

4

*

2

2

*

1

Ed

vvv

Ed

vvv

GOO

GOO . (21)

For linear loads, the open loop gives an adequate response. However, when operating with non-linear loads, mainly with the conventional diode-capacitor rectifiers, events as the LC filter oscillations creates control difficulties. Simulated waveforms in Fig. 5 (PSpice), obtained for open loop operation with a load power of 770 W, clarifies this problem. In Fig. 5(a) the linear load causes no control difficulties. On the other hand, the non-linear load in Fig. 5(b) causes a hard oscillation in the capacitor voltage vS. In the case of a combined load, no significant improvement in the output voltage THD was verified, as shown in Fig. 5(c).

Since the series APF is followed by the shunt APF, the current seen by the output voltage vO is nearly sinusoidal. So, the operational conditions for the proposed UAPF lead to the behavior in Fig. 5(a) and the LC filter design is an easy task.

Therefore, due to both LC filter harmonic effects and the conduction voltage drops on the transistors and diodes, it is necessary to introduce closed loop voltage control

(a)

((b)

(c)

Figure 5. VSI output voltage (larger, 20 V/div) and load current (smaller amplitude, 5 A/div) for open loop operation with different types of load. (a) Linear with 45 degree load angle - output voltage

THD=0.33%; (b) Nonlinear load - output voltage THD=15.5%; and (c) Combination of linear and nonlinear load - output voltage THD=11.2 %.

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In order to produce a finer correction. In this sense, the series APF voltage error signal is given by

. (22)SSS vve *

Considering vG as constant into the switching period, the combination of (10) and (12) results in

. (23)OOOS evve *

For closed loop operation, the output reference voltage in (21) is replaced by the output voltage regulator

signal, named v

*Ov

C2, that is,

2)21(

2

2)21(

2

42

2

22

1

Edvvv

Edvvv

GCO

GCO . (24)

Considering AO as a regulator option, signal vC2 is given by

. (25) OOOOOC eAvvAv )( *2

The controller design in (25) must take into account the series APF L1CS second order transfer function (see Fig. 2) given by

22

2

21 2 nn

nO

ssvv , (26)

with

Snn CL

f1

12 , (27)

SeS CL

R1

21 , (28)

where is the damping factor and ReS is the equivalent load resistance seen from the series APF output,

G

SeS I

VR . (29)

Then, the LC filter design can be based on

eSfS Rf

C4

1 (30)

Sf CfL 21 2

1 (31)

A simple proportional control is used here for the output voltage AO, where, for nonlinear control systems, the disturbance model in Fig. 6 is an appropriate solution. In this scheme, the steady-state error, due to the proportional compensation gain kP, is related to the imposed serial voltage vS. Because, in practice, this voltage is, at least, 10% of the nominal grid voltage, the steady-state output voltage error converges quickly to zero.The closed loop transfer is then given by

)1(2)1(

22

2

21*

Pnn

nP

O

O

kssk

vv , (32)

for which the poles are evaluated by,

)1(( 22,1 Pn ks , (33)

Figure 6. Disturbance model for nonlinear control systems.

After specifying the grid fundamental frequency fG and the switching frequency fS, the compromise between the output current ripple and the phase delay introduced by the filter must be satisfied by the closed loop filter cutoff frequency fn . The damping factor, , must to be large enough to avoid oscillations. On the other hand, the proportional gain kP must be smaller then to avoid an oscillatory response.

12

B. Shunt APF Control Strategy In order to obtain a near unity PF, the input current iG

must to be nearly sinusoidal and in phase with the grid voltage vG, as well as with the output voltage vO, so that

, (34)GeoO iRv *

where is the imposed equivalent resistance, in such a way that the voltage source formed by v

*eoR

S plus vG sees this “pure” resistive load, produced by the composition of the load in parallel with the shunt APF. Substituting (34) in (12), it comes,

2)21(

2

2)21(

2

6

*

3

4

*

2

EdIR

v

EdIR

v

GeoO

GeoO . (35)

Because the shunt APF works as a current source inverter, maintaining the sinusoidal waveform of the current needs a closed loop control. Classical control theory easily deals with this task. Therefore, the focus of this paper is the use of the OCC technique to produce a low cost analog controller.

The principle of the OCC technique, when applied to the shunt APF, allows emulating an equivalent pure resistance produced by the shunt APF in parallel with a linear or non linear load, in order to achieve near unity power factor and low input current THD.

The current is represented sensor voltage signal given by

GSI iRv , (36)

RS being the output sensor resistance. Then, considering (37) SeOm RRv /**

and substituting (36) and (37) in (35), it comes

. (38) EdvvEdvv

Im

Im

)21()21(

6*

4*

The control law in (38) is sufficient for emulating a pure resistance and near unity power factor, and does not employ neither current loop compensator nor current template generator. Therefore, to keep constant the dc-link voltage E, is replaced by the output voltage of the dc-link regulator A

*mv

E, named vC1,

3978

. (39) EdvvEdvv

IC

IC

)21()21(

61

41IV.

A.

where(40) EFFC AEEv )( *

1

AE being a proportional-integral regulator. OCC stability was demonstrated in [18] for general

cases and, for specific shunt APF, in [16]. The limit of global and local stability is governed by a minimal inductance which depends of the carrier slop.

O

GrmsS P

vTL

2

21 . (41)

where is the converter efficiency. Equation (41) is referred to the asymmetrical PWM

scheme used in all preceding OCC strategies. Considering the symmetrical PWM operation, for which the carrier slop is twice that in asymmetrical PWM, (41) can be rewritten as

O

GrmsS P

vTL

2

41 . (42)

C. Integrated APF One-Cycle Control Strategy For closed loop operation, two controllers are

employed: one for the output voltage vO and the other for the dc-link voltage E. Combining (29) and (34) yields

. (43)

FGFCIC

FGFCIC

FGFCIC

EdvvvvEdvvvvEdvvvv

)21()()21()()21()(

621

421

221

where,(44) EFFC AEEv )( *

1

and, (45)OOFOFC Avvv )( *

2

Index F in different variables means feedback sampled voltages, staggered in order to reduce the variables magnitude order. This is made by applying the voltage sensor feedback gain k in the realization of the analog controller, so that , and .GGF kvv OOF kvv kEEF

The output and the grid voltages must to stay in phase. So, the grid voltage phase and level must to be sensed in order to produces the output voltage reference and the reference series voltage , respectively.

*Ov

**OGS vvv

The functional block diagram for the proposed integrated OCC (36) is shown in Fig. 7. The pulse widths tP1, tP2 and tP3, for the digital controller are determined by

FOFGFICSp

FOFICGFSp

FGFICCSp

EvvvvTt

EvvvvTt

EvvvvTt

21)(

21

21)(

21

21)(

21

*16

*14

122

(46)

HARDWARE REALIZATION OF THE PROPOSED UAPF CONTROL STRATEGY

The adopted OCC control law for the three-leg UAPF in (13) is now realized via common analog devices. The simplified control scheme for the proposed integrated OCC strategy is depicted in Fig. 8.

The PLL is implemented via the ICL8038 waveform generator, which is a monolithic integrated circuit capable of producing high accuracy sine waveforms with a minimum of external components. The analog multiplier is realized with the integrated circuit MC1495, which is designed for use where the output is a linear product of two input voltages.

The Triangular Carrier Generator The (1-2d) ramp carrier generator, used in all existent

OCC strategies, presents a limitation due the operational amplifier slew rate and the on-resistance of the reset switch. Such drawback becomes unacceptable for higher switching frequencies. Besides slew rate limitations, the asymmetric PWM increases the inductor current ripple.

The key to produce centered command pulses is to employ an equivalent (1-2d) triangular carrier instead the sawtooth carrier. The carrier generator depicted in Fig. 8 is very simple and robust. Operational amplifier A1 may operate inverting, or not, the unitary gain depending on the comparator C4 output switch state (open collector type). The state decision depends on the sum of the carrier signal vC (A2 output) and the square signal vm1 (A1 output). The carrier amplitude is controlled by vm which emulates an input resistance by the OCC control. Main waveforms are also depicted in Fig. 9.

The current sensor is carried out with a LEM (active current transform) and its very simple scheme is depicted in Fig. 10.

Figure 7. Integrated OCC strategy block diagram.

Figure 8. Scheme for the proposed integrated OCC strategy.

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Figure 9. (1-2d) equivalent triangular carrier generator

Figure 10.

Figure 11. Current sensor scheme.

This paper considers a maximum grid voltage deviation of ±20%, which means nmax=1.2, and nmin=0.8. Due to nmaxthe dc link voltage restriction in pole 02 (19) is

. (47) OVE 16.1

The restriction in the poles 01 and 03 (17), is given by . (48) OVE 25.1

From these it can be concluded that the dc-link voltage is given by (48). Then, for a nominal output voltage of 110 Vrms, i.e. VO = 155 V, the dc-link voltage is given by

. (49) VE 193A reasonable value to be adopted is 250V. So, this will be the case. As a result, the minimum input voltage varies from 87 Vrms, VG =126 V, to 132 Vrms, VG = 186 V.

V. SIMULATION AND EXPERIMENTAL RESULTS

Simulation of operation under disturbances in the grid voltage and for a mixed nonlinear and RL loads (50% and 50%) was made in order to verify the disturbance rejection capability and the power factor correction. A maximum grid voltage deviation of ±20% was produced. The relevant specifications are:

Grid voltage, VG = 87 to 132 Vrms; Grid frequency, fG = 60 Hz; Linear load: inductance of 20 mH in series with a

resistor of 14.2 ohms. Nonlinear load: line inductance of 200 uH followed by

a diode bridge, a 4400uF capacitor and a resistor of 47 ohms.

Output voltage, VO = 110 Vrms; Output power, PO = 770 W (IG = 8 to 12 A); Dc-link voltage, E = 250 V; Switching frequency, fS = 10 kHz. Shunt APF inductance L2 = 0.5 mH; Series APF inductance L1 = 0.7 mH; Series APF capacitance CS = 25 uF; Figure 11 depicts the simulation results in the case of a

combined load. Figure 11(a) depicts the input and output variables of interest. The top curves are the grid voltage (larger amplitude) and the grid current (smaller amplitude). The significant current waveforms are shown in Fig. 11(b), from the top to the bottom: the load current, with a THD of 57%, but with a low power factor, mainly due the RL load; the series APF compensation current; the

grid current with a TDH of 4.2 % and in phase with the grid voltage, which gives a high power factor; the series APF inductor current, which is the same as the grid current, but filtered by capacitor CS (bottom curve).

The output voltage THD obtained was of 0.4%, input the voltage transition disturbance included.

(a)

(b)

Figure 12. Simulation results under disturbances operation of the combined load. (a) Grid voltage vG (top bigger: 50V/div), grid current iG

(top smaller: 25 A/div) and grid voltage vG (bottom: 50V/div). (b) Significant current waveforms, from top to the bottom: load current, the

series APF compensation current; the grid current, the series APF inductor current; the capacitor CS current (10A/div). Hor.: 2ms/div.

Experimental results were acquired for the triangular carrier generator (see Fig. 12), and for the power variables in the non linear load (Fig. 13). A reduction from 93% (bottom curve) to 14% (top curve with smaller amplitude) was obtained in the grid current THD, for a distorted grid voltage with a THD of 7% (top curve with larger amplitude). Low switch voltage stress, minimal current in the dc capacitor, and 100% in dc-bus utilization was achieved.

Figure 13. Carrier generator waveforms. From the top to the bottom: oscillator; T type flip-flop output; reset pulse; and carrier.

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Figure 14. Experimental waveforms for nonlinear RCL load: grid voltage (larger: 50 V/div); grid current (top: 5 A/div); load current

(bottom: 10 A/div). Hor.: 10ms/div.

VI. CONCLUSION

The analysis of a three-leg universal APF without any transformer was made out in this paper. The inherent equations of APF topology investigated were obtained and an integrated one-cycle control strategy was synthesized. With this strategy it was possible to obtain a reduction from 93% to 14% in the THD of the grid current for the highly distorted grid voltage and highly nonlinear loads considered. Low switch voltage stress, minimal current in the dc capacitor, and 100% in dc-bus use was achieved. Due to the reduced component ratings and low voltage stress a converter with reduced cost and power losses was obtained. Also, the control simplicity leads to robust and reliable behavior. Simulation and experimental results indicates a good performance for the proposed control strategy.

ACKNOWLEDGMENTS

Authors would like to aknowledge CNPq (Conselho Nacional de Pesquisa e Desenvolvimento) and FAPESQ (Fundação de Amparo à Pesquisa – Paraíba) for their financial support.

REFERENCES

[1] H. Akagi, “Trends in active power line conditioners,” IEEE Trans. Power Electron., vol. 9, no. 3, May 1994, pp. 263–268.

[2] B. Singh, K. Al-Haddad, and A. Chandra, “A review of active filters for power quality improvement,” IEEE Trans. Ind. Electron., vol. 46, no. 5, Oct. 1999, pp. 960–971.

[3] M. Aredes, K. Heumann, and E. H. Watanabe, “An universal active power line conditioner,” IEEE Trans. Power Delivery, vol.

13, no. 2, Apr. 1998, pp. 545–551. [4] H. Fujita and H. Akagi, “The unified power quality conditioner:

the integration of series and shunt -active filters,” IEEE Trans. Power Electron., vol. 13, no. 2, March 1998, pp. 315–322.

[5] H. Pinheiro, R. Blume, and P. Jain. Comparison of SV modulation methods for single phase on-line threeleg ups. In Proc. IEEE IECON, volume 2, pp. 1328–1333, 2000.

[6] N. Hirao, T. Satonaga, T. Uematsu, T. Kohama, T. Ninomiya, and M. Shoyama. Analytical considerations on power loss in a three-arm type uninterruptible power supply. In Proc. IEEE PESC,volume 2, pp. 1886–1891, 1998.

[7] H. Uematsu, T. Ikeda, N. Hirao, S. Totsuka, T. Ninomiya, and H. Kawamoto. A study of high performance single phase ups. In Proc. IEEE PESC, volume 2, pp. 1872–1878, 1998.

[8] K. Hirachi, M. Sakane, S. Niwa, and T. C. Matsui. Development of ups using new type of circuits. In Proc. IEEE INTELEC,volume 1, p. 635–642, 1994.

[9] H. W. Park, S. J. Park, J. G. Park, and C. U. Kim. A novel high-performance voltage regulator for single-phase ac sources. IEEE Trans. Ind. Electron., 48(3), June 2001, pp. 554–562.

[10] E. B. Shen. Alternative topological approaches to the electronic ballast. PhD thesis, Electrical Engeneering and Computer Science, Massachusetts Institute of Technology, Massachusetts - USA, 1997.

[11] S. J. Chiang, T. S. Lee, and J. M. Chang. Design and implementation of a single phase three-arms rectifier inverter. IEE Proc. Electric Power Applicat., 145(5):379–374, Sep. 2000.

[12] S. J. Park, H. W. Park, J. I. Bae, M. H. Lee, and C. U. Kim. Development of a high performance single-phase voltage regulator composed of 3 arms bridge. In Proc. IEEE ISIE, volume 2, pp. 700–705, 1999.

[13] Ben-Yaakov, S., Zeltser, I., Katz, A., and Golembo, G., NGPower Ltd. The best of two worlds:a mixed-mode front-end controller IC. Power Electronics Technology, PET06, Long Beach, 2006.

[14] Keyue Ma Smedley; C. Slobodan, “One cycle control of switching converters,” IEEE Transactions on Power Electronics, Vol. 10, N.8, Nov. 1995, pp. 625-633.

[15] Z. Lai, K. M. Smedley, and Y. Ma, “Time quantity one-cycle control for power factor correctors,” IEEE Transaction on Power Electronics, vol. 12, no. 2, Mar 1997, pp. 369-375.

[16] Chongming Qiao, Keyue Ma Smedley, Franco Maddaleno. “A single-phase active power filter with one-cycle control under bipolar operation,” IEEE Transaction on circuits and systems-regular papers, vol. 51, no 8, , May 2004, pp.1623-1630.

[17] Guozhu Chen, Yang Chen, Luis Felipe Sanchez, and Keyue M. Smedley, “A Unified Voltage Quality Conditioner Without Reference Calculation,” In Proc. IEEE PESC 2004, pp. 4251-4256.

[18] K. M. Smedley, “Tricks of the Trade: Poincare stability analysis of switching converters with nonlinear control,” IEEE Power Electronic Society New Letters, vol. 14, no. 1, Jan. 2002a, pp. 5-6.