The State-of-the-Art Mobility Enhancing Schemes forHigh-Performance Logic CMOS Technologies

Steve S. ChungEmerging Device and Technology Lab., Department ofElectronics Engineering,

National Chiao Tung University, Hsinchu, Taiwan, TEL: 886-3-573 1830 FAX: 886-3-573 4608 email: schung@cc.nctu.edu.tw

AbstractIn this talk, an overview of the mobility enhancing

techniques for high performance/low power CMOS tech­nologies will be introduced first. Three categories ofmobility enhancing schemes with global strain, localstrain, and hybrid-substrate engineering, will be discussednext. Either nMOSET or pMOSFET has theirrespective strategies for achieving the best deviceperformance. However, the strain technique has indeedraised reliability issues. Different reliability issues havebeen observed for different strain technologies. In thepast several years, we have paid much more attention onthe current performance of these technologies, the devicereliability study has not been sufficient in the previousstudies. As a consequence, this talk will also address theimportance of these mobility enhancing schemes andtheir impact on the device reliability for advanced CMOStechnologies which utilize strain schemes for currentenhancement.

1. Introduction

In more recent years, In order to extend thescalability of the sub-IOOnm CMOS technology, mobilityenhancing schemes have aroused much interest. Amongthese schemes, strained-Si devices [1-2], substrateengineering, and hybrid substrate technology [3-5] havebeen attractive for high speed and low power logicCMOS technologies. For the strained Si/SiGe devices, itprovides a factor of 50% to 100% mobility enhancementover that of bulk devices. The typical mobilityenhancement of n-type strained-Si is much larger thanthat of p-type devices. Therefore, several techniques havebeen proposed to enhance the pMOSFET reliability, i.e.,SiGe SID [6], the hybrid technology with differentsubstrate orientations for nMOSFET and pMOSFETrespectively [5].

In this paper, this talk will address several examplesof these mobility enhancing schemes, as well as thechallenges of these devices reliability, and the designguidelines for manufacturable CMOS technologies for65nm and beyond.

2. The Strain-Engineering for Mobility Enhancement

The interest in the strain engineering has beenspeed-up in recent years as a need in further scaling ofCMOS device for high speed and low power applications.In ITRS report 2007[7], it was pointed out that the strainsilicon technology has to enhance the driving current ofCMOS devices to 180% ultimately. A typical 3D strainengineering is illustrated in Fig. 1 [8], in which stress canbe achieved by channel [2] or substrate engineering[3].Uniaxial strain can be achieved by trench isolation,silicide, nitride cap layer, and recessed SID etc [6].Depending on process types and device structures, thesedevices exhibit different degrees of mobility enhance­ment comparing to conventional process/device structures.Table 1 lists various schemes which can be categorizedinto global, local, and hybrid strains. The Global strainis almost biaxial strain, and made by epi-growth strainlayer on the substrate. It involves SiGe in most of thecases, and therefore, Ge out-diffusion becomes inevitable[9]. Also, significant dislocation issues are emerged dueto a large area strain.

Moreover, this technique has an inherentdisadvantage of high manufacturing cost. The local strainis usually unaxial strain which is induced through theprocess. There are many stressors to implement localstrain, such as SiGe eS/D, SiC eS/D [10], and cappinglayer. The most typical process- induced strain is shownin Fig. 2 with a Contact Etch stopped SiN Layer (CSEL)[11, 14], [15] which will greatly enhance the channelmobility. Different from global strain [16], dislocationissues are prevented in the local strain. Finally, it is lowcost for manufacturing simplicity. The last one is hybridstrain [17]. Hybrid strain involves a combination ofnMOSFET and pMOSFET with different mobilityenhancement schemes. But it faces the big challenge ofcomplex manufacturing.

3. The Channel Engineering

A most typical example of using Si/SiGe structure is

978-1-4244-2186-2/08/$25.00 ©2008 IEEE

shown in Fig. 3 with relaxed SiGe layer grown on Siliconsubstrate, from which examples of the I-V characteristicsare shown in Fig. 5.

The MOSFET with a strained-Si/SiGe channel hasbeen the prime initiative for mobility enhancementschemes. As a result of the lattice mismatch shown in Fig.4, a Si layer on relaxed SiGe layer is under a tensile strain,which modifies the band structure and enhances carriertransport since this induces a lower effective mass of thecarriers. Figs. 5 and 6 show the n-MOSFET andp-MOSFET drain current and mobility, respectively [5].It shows that Si/SiGe n-MOSFET mobility has beenincreased 70% over that of bulk device. However, there isone disadvantage of the SiGe strained devices in thatp-MOSFET does not get much gain.

Here comes another idea on developing p-MOSFETon (110) substrate [3]. A typical result shown in Fig. 7reveals that p-MOSFET mobility has been enhancedwhile we receive a loss of mobility in n-MOSFET [9].Similar results in their driving currents, Fig. 8. As a result,an idea of the so-called hybrid substrate CMOStechnology becomes a more promising technology, Fig. 9,as will be explained in latter section.

For the state-of-the-art design in nMOSFETs, thereare some guidelines from our experiences. Fig. 10 showsthe Ion-lofT characteristics of nMOSFETs with variousstrains. We may categorize all the splits into two groups.The first group is SiGe on substrate devices and CESLcapping layer devices with excellent performance up to34% and 30%, respectively, in comparison of that of bulkdevices at the same value of lofT for each device. Theother group is SiC on SID devices and SSOI devices,which exhibit good performance around 15% bycomparing to bulk devices at the same value of lofT foreach device.

For the design of pMOSFET, comparisons betweenthe bulk, SiGe on channel (biaxial,) and SiGe onS/D( uniaxail) devices, Fig. 11, have been compared. TheIon-lOfT characteristics of both the splits and control sampleare given in Fig. 12 . We can find SiGe on SID devicesexhibit high driving current enhancement comparing toSiGe on the channel with the same value of lofT, which isbecause the stressor of SiGe on SID devices is closer tochannel than that of SiGe on channel devices. The closerthe stressor is to the channel, the higher the effect of the

strain becomes. Hence, SiGe on SID devices have higherperformance than that of SiGe on channel devices.

4. The Hybrid-Substrate Engineering

In order to maintain a simultaneous current gain in aCMOS technology, we can take advantage of then-MOSFET on (100) substrate while p-MOSFET is madeon (110) substrate. This constitutes the hybrid substratetechnology[3] as shown in Fig. 9. Here, p-MOSFETmobility can be more than doubled on (110) Si-substratewith current flow on the (110) direction comparing to thatalong the (100) direction (Fig. 7). Also, electron mobilityis the largest along the (100) direction.

On the contrary, for the substrate engineering withorientations different from (100) substrate, for example,for devices made on (110) substrate, it provides a muchlarger hole mobility enhancement in pMOSFET, whilereceives a loss of mobility in nMOSFET [4-5]. Therefore,a hybrid substrate technology is evolved for a need withpMOSFET on (110) substrate and nMOSFET on (100)substrate.

Figs. 7 and 8 show the drain currents and mobilitiesfor both nMOSFET and pMOSFET on (100) and (110)substrates. It reveals that pMOSFET has a 50%enhancement in its mobility using (110) substrate, whilenMOSFET mobility is reduced. The result is just theopposite to that of strained-Si devices.

5. The Challenges on Designing Reliable StrainedDevices

A. Enhanced Degradations in Strained SVSiGe Devices

As reported in [8] that a larger enhancement of mobility

may adversely degrade the device reliability. As a consequence,

it is important to understand the various strain-induced stress

effect incurred by different strained techniques. To investigatethe degradation effect, the first set of tested devices is the

strained-Si/SiGe nMOSFETs in Fig. 13. Figs. 14(a) and (b)

show the drain current degradations after FN and He stress

respectively. As we reported in [5], the origin of the drain

current degradation is related to the mobility enhancement. And,

to further differentiate its degradation mechanisms, the vertical

and lateral field effects have been evaluated. Fig. 15 shows the

measured ~Icp for studying the vertical field effect using FN

stress. Since ~Icp is proportional to the generated Nib we do not

see a major difference. However, the comparison for bulk and

strained devices under VG=Vo HC stress (Fig. 16), we have

seen a huge difference of ~Icp, in which lateral field becomes

dominant. In other words, the huge degradation in Fig. 14 and

the much higher ~Icp in Fig. 16 are caused by a large impact

ionization rate (Ia!lo) of the strained devices.

In comparison, a second set of nMOSFET devices with

tensile-cap, shown in Fig. 17, has a comparable mobility for

long channel while an enhanced mobility by the tensile-strain.

Similarly, device 10 degradation under FN and HC stress has

been compared in Figs. 18 and 19 for the ~Icp after FN and HC

stress respectively. It is noted that the ~Icp for tensile-Si does

not increase as much comparing to the strained-Si/SiGe device

(Fig. 16). The reason is attributed to a higher impact ionization

rate in tensile-Si devices. Therefore, we see that the tensile-Si

shows high drain current enhancement while it shows even

smaller HC degradation. This can be explained that a large 10

degradation in strained-Si/SiGe device is attributed to the large

mobility enhancement and hence induces large Ia/Io.

B. Reliability of SiGe-channel and SiGe SIDpMOSFETs

To investigate different strained effect for pMOSFETs,

similar experiments have been conducted. Fig. 11 shows a set of

devices with SiGe-channel(biaxial) and SiGe SID(uniaxial). Fig.

12 is lon-Ioff characteristics of these devices. Figs. 20-22 show

that all three devices have about the same ~Icp after FN stress.

Also, results from Figs. 21 to 22 show a comparable ~Icp for

biaxial or uniaxial device after the HC stress. SiGe SID device

shows a little larger 10 degradation. While, as a result of misfit

[8] in a biaxial strain, SiGe-channel device generates much

larger Nit than the SiGe SID ones.

c. NBTI Improvement for SiGe SID pMOSFETs

One other issue which is critically important to pMOSFET

is the NBTI. As demonstrated in [18], the NBTI effect in a SiGe

SID and SiGe-channel pMOSFET is serious. Also, SiGe SID

uniaxial strain (uniaxial) shows much better NBTI

characteristics comparing to SiGe-channel (biaxial) ones. To

further improve this SID strained technology, a recent approach

with embedded-diffusion barrier (EDB) SiGe SID [6], Fig. 23,

has been demonstrated with even better NBTI improvement.

Results are shown in Fig. 24, in which a large lifetime

improvement can be achieved with this EDB structure in SiGe

SID. This is attributed to the prevention of boron diffusion

toward the channel through this barrier, such that the embedded

SiGe SID is successful for short channel effect control and high

reliability design.

To summarize, although various mobility enhancingschemes have been shown with very good performance interms of its ION, IoFF, we still face challenges for asuccessful applications in terms of the process control,manufacturability, and in particular their reliabilities. Foreither strained channel or substrate engineering withcombination of mobility enhancing schemes, it tends togive a worse reliability for the advanced CMOS devices.Therefore, much effort needs to be done for theunderstanding of their reliabilities before these strainedtechniques can be used for manufacturing in high- endCMOS logic applications.

Acknowledgments The author would like to thank the

Central R&D Division of UMC for supporting the author's

work such that quality research can be published in IEDM and

VLSI. This work was supported in part by the National Science

Council, under contracts NSC-94-2215-E009-067, NSC-95­

2215-E009-273, and NSC-96- 2215- E009-185.

References[I] C. H. Ge et aI., in Tech. Dig.IEDM, p. 73,2003.[2] J. Hoyt et aI., in Tech. Dig. IEDM, p. 23, 2002.[3] M. Yang et aI., in Tech. Dig. IEDM, p. 453, 2003.[4] T. Ghani et aI., in Tech. Dig. IEDM, p. 978,2003[5] S. S. Chung et aI., Symp. on VLSI Tech., p. 86,2005.[6] C. H. Tsai et aI., Symp. on VLSI Tech., p. 188,2006.(7] Process Integration, Devices, and Structures, in ITRS,

p. 15,2007.[8] H. C.H. Wang et aI., in Tech. Dig. IEDM, p. 61,2003.[9] S. S. Chung et aI., in Tech. Dig. IEDM, p. 567, 2005.[10] S. Pidin et aI., in Tech. Dig. IEDM, p. 209,2004.[II] F. Ootsuka et aI., in Tech. Dig.IEDM, p. 575, 2000.[12] K. Rim et aI., in Symp. on VLSI Tech., p. 98,2002.[13] F Andrieu et aI., Symp. on VLSI Tech., p. 50,2007.[14] W. oS. Liao et aI., EDL, p. 86,2008.[15] K. -M. Tan et aI., Symp. on VLSI Tech., p. 127,2007.[16] 1. W. Pan et aI., in Tech. Dig.IEDM, p. 461, 2006.[17] S. Pidino et aI., in Tech. Dig. IEDM, p. 213,2004.[18] S. S. Chung et aI., Tech. Dig. IEDM, p. 325,2006.

~ nMOSFET pMOSFET Hybrid

Strain Uniaxial Biaxial Uniaxial Biaxial~Direction

SiC on Relaxed SiGe onDiamond SiGe-

Strain CESL SID SiGeSSOI

SID CESL-like

channelT-CESL for nFET

scheme subcarbon C-CESL for pFETFinFET +EDB + capeap

.1100(%) +12 +30 +13 +18 +25 +14 +69 +80 nFET· 60%pFET· 65%

Lg(nm) 37 25 60 25 45 60 70 ~ 40

EOT(AO) 18.8 20 2217.5~ 14 ~~~(TiN/HfO,)

Ref. [11] [10] [12] [13] [6J [14] [15] [16] [17]

Table I Summary of various typical strain techniques and the device performance.

o Bulke SSOIb. SiC• Capo SiGc

nMOSFET

900 1200 1500 1800 2100

I (uAlum)on

Fig. 9 The concept of hybrid substrateengineering with pMOSFET on (110) substratewhile nMOSFET is on (100) substrate. [3]

IE-5 F'"""------r"''7'I7--,''"'''''----,

Drain Voltage,VD(V)Fig. 8 Comparison of the ID current for (110) and(100) substrate p-MOSFET (left) n-MOSFET (right).

,----------, 500CiJ>Strained-Si

Fig. 5 Comparison of the ID current for strained-Siand bulk-Si devices, (left) p-MOSFET (right) n­MOSFET.

00.-----------.

Fig. 6 Comparison of the mobility for strained-Siand bulk-Si devices, (left) p-MOSFET, (right) 1

MOSFET.

6 ~PM~0~S~F::-:E::T,......"T,....0-x=....,1..,..6A.,.........."N.,.,M.,.,0..,S,..,F,..E,.,T--=To-x-=""1""'6"""""'" 6W/L.,= 10/0.09~m W/L., = 10/0.11~'m

-0- strained-Si-a-bulk Si

,..-- --T:-::-:c:-:==------, 12PMOSFET NMOSFET

.-.. ~8 W/L.,= 10/01~,m W/L.,= 10/0.1~m 10~E5 « E Tox= 14A Tox= 14A

-e-strained-Si E -- -0-(110) ••• '0-o-bulkS:;.i...__" 4 ~ _°6 0~O-(100) (loo~,.:ioOO 8:

3 c ~ 4 ~Oo~IIO) l p' 6 ~~ ~ ••L·o • P( I 10) ~~ U:J •• '0 /P 4B

2 <3 .•. \ .0C 2 (100) .,.0\ 1/ C

C "" '.0 ° -0- (100) 2 'ro1 ·;;:; 'V '-\ o~ 0 (110) •~ ~ .'~y -o 0 0 L........----'-~---'-~~.,_.........J~___L~...J 0 0

o ....................L-.....L-.&..::;;/lI-.....L-.....L-.....L-.>.-.J 0 -1.2 ~.8 ~.4 0.0 OA 0.8 1.2-1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2

Drain Voltage, VD(V)

~1IlCfl

> @~

~ 70 : EE 00 I ~l..UJJ:Il'h. ~ •••••II.'-5=ri~!il i 9 Bulk-Si 300 .£~40 .0 :0:0 ° 200

0

o :xl ./PWOSFET Tox= 1M 22 0W/L =10/10pm CQl Zl I 100 e- ~ -e- strained-Si tl~ 10 1/ -O-bulkSi 0 WkSi Ql

o 0 iIi0.0 0.5 1.0 1.5 0.0 0.5 1.0 1.5

Effective Reld, ~FF (MV/cm) Effective Field, ~FF (MV/cm)

o 000 05 1~ 1~00 05 1~ 1~

Effective Field, EEF,(MV/em) Effective Field, E",(M/em)

~5E04

buried SiO,

(b)

gate

Si substrate

strained Si

n· H ...·~eia;e(r....· n·Si,.~Gex

(a)

Si02,----,/

gate A'

Si substrate

SiGe graded bufferGe: 0% to x%

Fig. I Several different approaches toenhance the mobility of CMOS devices. [I]

200ox= NMOSFET til

W/L=10/10"m W/L=10/1"", Tox= 14A 400 >til -0-(110) -0-(100) N- -> 150 0- (100) -0-(110) E E

NE u,. •(~

300~ ~ IE-6sa~ <~ 100 :0

200 0 -II::0

r~E 0

0 -2 c

0OJ 100 .;:; IE-7(5 UI Ql •iIi 600

Fig. 2 Several different approaches to enhance themobility of CMOS devices. [11]

Fig. 3 (a) The strained Si/SiGe structure on bulk-Sisubstrate and (b) the strained Si/SiGe on SOlsubstrate.

Fig.4 A strained-Si layer on top of SiGeshowing the biaxial strain.

Fig. 7 Comparison of the mobility for (II Oland (100)substrate devices, p-MOSFET (left) and n-MOSFET (right).

Fig. 10 Comparison of the lon-Ioffcurrent enhance­ments for nMOSFETs with various strains.

1.0

-o-SiGe SID-0- Bulk-Si

SiGe SID

PMOSFET Tox=14A (100)/<110>W/Leff=10/0.06f'IT!

Slress@VG=VO= -2.2V, 300s

PMOSFET Tox=14A (100)/<110>W/Left10/0.061!m

Stress@VG=vo= ·2.2V, 300s

-<>- Slrained-Si/SiGe__-Bulk-Si

Strained-Si/SiGe

If''~n-~'''I~"''~~'';~'')l'':'~O

PMOSFETTox= 14A (100)/<110>W/Leff=10/0.06f'IT!Slress@VG= 2V, 300s

-0- Bulk-Si_6_ Strained-Si/SiGe-o-SiGe SID

~-

·1.0

E:::J

::( 4

2-a.u

<i- 2

C~:::J ~

~ °l.L-~_J...-~-=~~~~~J-1.0 -11.5 0.0 0.5 1.0

Gate Voltage, V g1 (V)

10'

"- 60u<ii" 40

~:; 20U0...U

10' r---------------.,PMOSFET NBTI

SiGe SID (100)/<110>... Temp= 125°C

._._.~, I ._._._._._._._._0_._., 'oj, ,...., ,'", ,, ,, ,, ,

° W/p E~B, Fig. 23(a)oW: EpB, Fig. 23(b)

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Gate Voltage, VG (V)

Fig. 20 Comparison of the Mcp after FN stress.Note that the enhancement of 6Icp is about thesame for three devices given in Fig. 11.

E 100:::J::( 802-~ 60

<i"i 40

~

~ 20 L=B~U~lk~-S~i:~~~~~~~~lIl::J-1.0 -ll.5 0.0 0.5 1.0

Gate Voltage, V g1 (V)

Fig. 21 Comparison of the 61cp after HC stress,for SiGe SID device in Fig. II, where 61cp is alittle smaller than SiGe-channel device in Fig. 22.

~ 100,..--------------,E:::J::( 80

2-

Fig. 24 Comparison of the NBTI degradations forthe devices given in Fig. 23. The lifetimemeasurement based on NBTI for devices in Fig. 23,the SiGe SID with embedded barrier shows a muchbetter NBTI improvement.

(al SiGe SID w/o EOB (b) SiGe SID wlEDB

Fig. 23 The cross-sectional view of (a) SiGe-S/D and (b)SiGe SID with embedded barrier for SID region[6].

-0.5 0.0 0.5Gate Voltage, V g1 (V)

Fig. 22 Comparison of the 6Icp after HC stress. Note the61cp for SiGe-channel device in Fig. 11, the enhanced IDdegradation is caused by a large impact ionization rate.

(b) Si-channel wfTensile-cap

- -n n

Tensile-~i

Bulk-Si ~ \

(c) SiGe SID

SiGe SiGe

Ca) Control-Si

Fig. 17 The cross-sectional view of (a) bulk-Si deviceand (b) bulk-Si channel with tensile-cap layer.

'E 2~:;U0...U

E6r-------------.:::J NMOSFETTox= 14A (100)/<110>

::( W/Leff=10/0.0S,""2. 4 Slress@VG= 2V, 300s

~ __-Bulk-Si<i -0- Tensile-Si

·1.0 -ll.5 0.0 0.5 1.0Gate Voltage, V gh (V)

Fig. 19 Comparison of the 61cp after HC stress,note the 61cp for tensile-Si is enhanced, but is notso huge, comparing to Fig. 6, in the case ofstrained-Si/SiGe devices.

~.,-1.0 -ll.5 0.0 0.5 1.0

Gate Voltage, V h (V)Fig. 18 Comparison of the 61cp affer FN stress.Note that the enhancement of 6lcp is about thesame for tensile-Si and bulk-Si ofnMOSFETdevices.

-1.0 -ll.5 0.0 0.5 1.0Gate Voltage, V

ghoVo

Fig. 16 Comparison of the Mcp after HC stress forthe devices in Fig. 3. Note the 61cp for strained­Si/SiGe is greatly enhanced comparing to FN stressin Fig. 5.

E 200 "'-N-M-OS-F-E-T-T-O-X=-16-?-(-1-00-)/-<-10-0->----.:::J::( 160 W/LeWl0/0.07p/11

:::J Slress@VG=VO= 2V, 300s

~ 120 -o-SiGe-Ch SiGe-Chan el

<i ...... Bulk-Sl f1:c- 80

~~ 40 J Bulk-SI

U

o

9;;(E-

(b) SiGe-channel

Silicon Substrate (100)

Bulk-Si

Si (100) substrate

(b) Bulk strained-Si/SiGe

Strained-Si/SiGeBiaxial Strain

6 -­c~.....:::J

3UC.~

L...................L...'--'--.................Jl~L..o... ..........J.......-'-....J 0 00.2 0.4 0.6 0.8 0.0 0.2 0.4 0.6 0.8 1.0

(a) Control

Si (100) substrate

(a) control-Si

5.0E 4.5 NMOSFET Tox= 16A (100)1< 100>

~ 120:::J E NMOSFETTox= 14A (100)/<110>::c 4.0 :::J

W/Leff=10/0.07pll1 ::( W/LeWl0/0.06,,,,,2- 3.5

~ 3.0Slress@VG= 2V, 300s 2. 80 Slress@VG=Vo=2V, 300s-o-Bulk-Si "-

<i 2.5 -0- Slrained-Si/SiGe_u -<>- Tensile-Si<1 -e-Bulk-Si Tensile-Si

C 2.0 SiGe-Channel i"Q)

.\40

"- 1.5 ~"-:::J 1.0 Bulk-Si_ :;U U Bulk-Si

0.50... --- 0...U 0.0 U

o

-1.0 -0.5 0.0 0.5 1.0

Gate Voltage, Vgh

(V)

....;- 6CQ)..........:::JUC

~o

lE-6.-------..................-----,

Fig. IS Comparison of the Mcp after FN stress. Notethat the enhancement of 61cp is very close forstrained-Si/SiGe and bulk-Si ofn-MOSFET devices.

E:l~ lE-7:l~

.J

Source ---/------- Drain

Si Channel

Fig. 13 The cross-sectional view of the experimentalbulk-Si and biaxial strained-Si/SiGe devices.

Drain Voltage, V D (V)

Fig. 14 The drain current degradation for devices in Fig.13 under FN(left) and Hqright) stresses. Strained­Si/SiGe device exhibits a larger [D degradation after HCstress.

1E-8 L.~....IJ.""""~ __~_.J-~--JL.-~....Jo 200 400 600 BOO 1000

lon(uAlum)

Fig. 12 Comparison of the lon-Ioffcurrentenhancements for pMOSFETs shown in Fig. 14.Note that SiGe SID structure (uniaxial) exhibits alargest Ion current enhancement.

Fig. 11 The cross-sectional view of (a) bulk-Si device and (b) SiGe-channel, and (c) SiGe Source/draincompressively strained pMOSFETs.