Copy Smart Technology Transfer ISSM Paper: MS-P-166

David Tucker National Semiconductor S. Portland, ME, USA

David.Tucker@nsc.com

Paul Fearon National Semiconductor S. Portland, ME, USA Paul.Fearon@nsc.com

Marc Landry National Semiconductor S. Portland, ME, USA Marc.Landry@nsc.com

Jerald Rock National Semiconductor S. Portland, ME, USA Jerald.Rock@nsc.com

Abstract- Transferring technologies among factories is a com-mon practice. Numerous factors which drive this include: adding a second source, consolidating technologies, purchas-ing processes, and adding capacity for new processes. Trans-ferring facilities can be company to company; site to site within a manufacturer; from old to new tool sets; small to larger wafer sizes and include other complicating scenarios. At National Semiconductor, recent transfers involved existing technologies among three fabrication sites. In this paper the evolved transfer process is reviewed along with a discussion of obstacles, methods to counter these issues and best practice techniques.

INTRODUCTION In an effort to acquire second sources for key technologies, balance loads, and more importantly costs, for three wafer fabs, National Semiconductor recently embarked on an aggressive multi-site transfer project (Figure 1). This in-cluded general complications such as converting from six to eight inch wafers; porting older, 1.5 micron technology into a 0.25 micron facility; and introducing finely tuned, temperamental analog technologies into hitherto smooth running, easily manufactured logic facilities. Financial considerations made a ‘copy exact’ methodology prohibi-tive due the number of tools that would need to be pur-chased. Thus, a ‘copy smart’ method was employed, where every effort was made to match process technology and engineering judgment was used in areas where changes were necessary.

Figure 1: Number of product transferred from site to site. These include nine different processes to transfer.

TECHNOLOGY TRANSFER PROCESS At National Semiconductor, a system has developed to organize and track process transfers. This includes a for-mal site visit to the existing technology, or sending site, by the multidisciplinary receiving site team. This is dubbed the PDA, or Process Difference Analysis, team meeting. At the meeting, a charter is completed which includes de-tails on sending and receiving site equipment and proc-esses. Notably, a careful review of the risk associated with each process step is rigorously completed (Figure 2). This review includes statistical analysis of fault occurrence, de-tection and mitigation probabilities, along with engineering judgment when exact numbers are not possible. The cul-mination of this was a risk assessment number for each process step which provided subsequent prioritization for follow up evaluation. The PDA process also produces guidelines for matching processes. This includes cross section analysis, SIMs, electrical matching criteria and OLPM, or On Line Process Monitors such as gate oxide thickness and poly linewidth.

Figure 2: Example of risk assessment from PDA meeting.

Golden wafers The results of the PDA meeting, usually a three day gather-ing, gives the project team a significant amount of pre-work to accomplish before running the initial production material. This includes rudiments of matching work for numerous critical processes. An important means for this is the creation of Golden Wafers. For this, a lot is started at

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the sending site and wafers are pulled at various steps, measured, and sent to the receiving site. These are now the ‘gold standard’ for measurements, since metrology tools may be of identical brand, but different calibration. Criti-cal gate oxide thicknesses have been mismatched, such that the sending site has given a 120A standard and the receiv-ing site measures 123A, which now becomes the receiving site target. Gold wafers are also used to run cross sections to look at intricacies of metal, poly, deep trench and field oxide profiles.

Implant process matching SIMs are run to match implant steps. These are accom-plished, not with the Golden Wafers, but using flat, bare silicon standards to avoid process variability. The results of these SIMs are doping profiles which may receive sev-eral iterations to exactly match dose and energy. Oddities such as matching a singly charged implant with a double charged species could result in imperfect matching (Figure 3).

Figure 3: Implant profile matching traces showing difference between Boron +2 and Boron +1 implant recipes.

Etch process matching We have found that etch processes require output matching which includes cross sections, electrical testing and yield verification. For our factories, etch tool types, along with wafer size differences dictate that ‘copy exact’ recipe work is not enough, or often impossible. For example, different types of poly etch tools have been matched with completely different recipes by matching the etched poly linewidth, profile, and resulting electrical response such as N and PMOS saturation current.

Photolithography process matching Defining photo layers is done in a rigorous layer by layer approach. Layers designated as non-critical such as well implants are somewhat easier since the wafer is flat at that point and the dimensional tolerances are manageable. Critical layers such as gate poly or metal layers require a full photolighography setup which includes focus exposure matrices (FEMs) and may include obtaining electrical data from wafers run with FEM conditions.

Diffusion process matching Most diffusion processes recipes were set up first to match thermal profiles, then adjusted for time based upon test wafer output. The oxide thickness grown during these processes was deemed a suitable measure of the complete thermal cycle. In measuring this oxide wafer, it was essen-tial to have wafers from the sending site measured on re-ceiving site metrology tools to assure accuracy.

Electrical test (parametric) matching Initial parametric work involves setting up equivalent pro-grams and correlating test data between sites. Typically this involves testing the same wafers and same test sites at each location, then performing a statistical analysis to en-sure matching. It is preferred to use wafers from multiple wafer lots when performing this exercise. During the transfer process, the same methodology applies to ET matching as to the process matching. Critical parameters must obviously initially all be in spec. Those that are not in spec are targeted for adjustment first. Once all ET pa-rameters are in spec, it is important that targeting work focuses on tests that are deemed a priority by both the sending site and receiving site. (If the matching criteria are not carefully defined, this could mean many extra months of process tuning). It is also important to note that it is helpful to group unmatched parameters together. This will assist in understanding the process to ET relationships, and to minimize overlap with process adjustments. To accom-plish this, we use a quadrant chart (Figure 4) where electri-cal parameters are grouped in boxes; box 1 is most desir-able – good match and no action needed; box 4 is least de-sirable – poor match and immediate action required.

Figure 4: Electrical test matching matrix.

CHALLENGES We have encountered innumerable challenges with recent transfers. Broad categories included attempting to run the new fab with a proven, but different architecture and matching processes on completely different tool types. The differences in tool types proved to be the most odious, with the older generation tool defining the specifications to which the associated technology would conform. Thus, certain apparent undesirable tool responses must be de-signed in to the newer process in an effort to exactly match the final product datasheet, which was set among the at-tributes, good or bad, of the originating tool configuration.

Differences in architecture Recent transfers have met innumerable challenges such matching different backend architecture (Figure 5). For this challenge, our approach was to avoid copying aspects of the sending site in preference to duplicating a proven receiving site backend architecture. Mottivations included reduced capital cost since no new tools were needed as well as minimization of process development work for the receiving site. Often, only linewidth and thickness changes were necessary.

Figure 5: Cross-sectional analysis of Site A contacts from first metal layer (top) and Site B contacts (bottom).

Another ‘copy smart’ decision was to avoid a troublesome POCl doping process which soused gate poly with phos-phorus. It was decided that the cleaner implant doping process was a more desirable method. Implant was more controllable, but ultimately gave a device issue, since the POCl doped Poly was effectively thicker and a better im-plant screen. Adjustments were necessary to the implant poly scheme to match the POCl architecture.

Matching processes using different tool types A major unavoidable difference was in running a technol-ogy which was set up on g-line photo with i-line equip-ment. This, combined with differences in metrology neces-sitated use of golden wafer to match linewidths and spaces. Our key finding was that the advanced techniques for i-line, such as overlay, turned out to be largely unnecessary with the older technology. G-line equipment did nto rely on in-product overlay. A curious finding was that the lar-ger, 1.5um round g-line vias printed as rough squares on the i-line tools which had better resolution; this was not an issue.

Perhaps the most profound challenge was in converting from an 8-wafer barrel EPI reactor to a single wafer tool (Figures 6 and 7). This manifested as a true apple/orange affair, as the tools were incapable of matching. Although the single wafer tool was capable of much better thermal across wafer uniformity, is was not capable of the lengthy bake out step where buried layers (preEPI implant layers) would outgas in a unique product specific manner. This had to be matched with considerable finesse by EPI engi-

neering and ultimately matches with SRP profiles (Figure 6). A specific structure which was affected by EPI doping profile is shown in Figure 7 with the SIMs plots inserted into the center of the picture.

Figure 6: SRP Profile of Site A and Site B showing differences in doping profiles with different EPI processes.

Differences between six and eight inch wafers Issues arose when implementing 8-inch wafer processing with process methods which became obsolete, or at least uncommon, when 8-inch became a standard. One example was high pressure oxidation which was used to form rather thick, recess LOCOS oxide isolation. Once a suitable tool and skilled maintenance personnel were identified, this process was easy to implement.

CONCLUSION Many factors were needed for a successful process transfer. Most notable include the PDA process, allowing three cy-cles of learning, and giving appropriate goals for process and parametric matching which were adequate to assure quality products, but not stringent enough to require adding many more months of analysis and tuning. Critical issues arose when it was undesirable to match exactly, but these were overcome by appropriate upfront decisions as well as innovative engineering improvements. It has also been beneficial to yield investigations to allow parts to be run between sites, for example, run only the EPI process at the receiving site, all other steps at the sending site. This gave early view of differences to resolve.

Figure 7: Result of subtle EPI differences on product per-formance. Solution was revealed through extensive SIMs analysis.