A 5.4-GHz Low-Power Swallow-Conterless Frequency Synthesizer with a Nonliear PFD

Yue-Fang Kuo, Ro-Min Weng, and Chun-Yu Liu Dept. of Electrical Engineering, National Dong Hwa University,

Hualien 97401, Taiwan, Republic of China romin@mail.ndhu.edu.tw

Abstract—A 5.4-GHz swallow-counterless CMOS frequency synthesizer with a nonlinear phase frequency detector (PFD) is presented. With the same total division ratio, the proposed divider can effectively decrease the gate-counts so as to consume less power than that of the traditional ones. The designed fast-locked nonlinear PFD can enhance the switching speed while remaining the loop stability unchanged. The phase noise of the frequency synthesizer is -135dBc/Hz at 10 MHz offset in a 0.18µm CMOS process. The switching time is within 5µs. The power consumption is only 7mW with 1.5V supply voltage. The implemented frequency synthesizer occupies a small chip area of 0.78mm2.

I. INTRODUCTION Due to the rapid evolution of the wireless communication

market, many applications such as cellular phones, personal communication systems (PCS) and wireless local networks (WLAN) have increased the demand for low-cost RF circuits operating at the microwave frequencies. The single-chip integration using low-cost CMOS technology has become a major tendency. A frequency synthesizer, usually implemented by a phase-locked-loop (PLL), is utilized for an RF local oscillator of a wireless transceiver. It is one of the critical blocks in terms of the power consumption since it operates extensively during transmitting and receiving signals. The goal of low-voltage and low-power still remains a challenge in designing a frequency synthesizer.

Most of the common high-speed frequency dividers were based on a dual-modulus prescaler (DMP) architecture for the low power requirement [1]. However, such DMP would require two counters and numbers of controlled bits which occupy large chip area. For high transmission rates and lower output phase noise, there are trade-offs between the settling time and the loop bandwidth. In order to minimize the output phase noise, the loop bandwidth should be made as narrow as possible. On the other hand, to obtain better tracking and acquisition properties, the loop bandwidth should be made wider. A dual-slope PFD with a charge-pump (CP) was proposed to achieve a fast locking synthesizer while maintaining the better noise bandwidth [2]. Otherwise, the complex architecture causes the extra power dissipation.

fref

NonlinearPFD

Charge Pump

3rd-order LPFVCO

UP, DN icp fout = 2(NP+S)fref

ffd R1

C1

C2

R3

C3

+ ip

+ 4ip

UPE, DNE

Input Buffer Buffer

Frequency Divider (536~544)

2/3TSPC

ControlQualifier

2SCL

(CML)

Differential toFull SwingConverter

4TSPC

2

P-CounterTSPC

P-CounterDetector

5

S-CounterDetector

5J

K

Q

S[4:0]Channel Selection

DMP (8/9)

Mode Controlled1/0 = N/N+1

VC

Prescaler

Figure 1. Block diagram of the proposed synthesizer.

This paper proposed a new frequency divider having the same performance as a conventional one without employing a sallower counter which takes extra power and unnecessary chip area. Also a nonlinear PFD is implemented to achieve a fast-locking synthesizer

II. SYNTHESIZER ARCHITECTURE The proposed frequency synthesizer as shown in Fig.1 is

designed for WLAN 802.11a transceiver systems which has a carrier frequency around 5.4 GHz and covers 5 channels with a channel spacing of 20 MHz. The synthesizer comprises a nonlinear PFD with a CP, a swallow-counterless DMP frequency divider, a VCO, and a third-order loop filter.

The proposed frequency divider in the feedback branch employs the pulse-swallow architecture. The most critical block of the frequency divider is the DMP. In order to relax the speed constraints of the DMP, its input frequency is first halved by a divide-by-2 prescaler with a differential source-coupled logic (SCL). This solution forces to reduce the reference frequency to half of the channel spacing, i.e., 10 MHz. The divide-by-8/9 DMP is realized in the true-single-phase-clock (TSPC) logic. The DMP is followed by a divider-by-32 programmable counter, while a 12 to 16 S-counter detector allows changing the overall division ratio between 268 and 272. The output frequency can be sweep between 5.36 and 5.44 GHz in 20 MHz steps.

3-901882-19-7 2006 IFIP 357

The dual-slop nonlinear PFD and CP effectively reduce the pull-time and enhance the channel switching speed. For fast phase and frequency locking, a coarse-tuning current is activated to track the large phase difference. On the other hand, a fine-tuning current is initiated to complete the fine adjustment near the small phase difference.

VCO is designed with a small gain (KVCO) to ensure the low phase noise and good spur performance under a low supply voltage. On the basis of the small VCO gain and the fine-tuning current, the on-chip capacitors in LPF can also be reduced to minimize the chip area. The resistors in LPF are scaled up accordingly to maintain the same loop bandwidth and stability.

III. SYNTHESIZER BUILDING BLOCKS

A. Nonlinear PFD, CP, and Loop Filter The proposed nonlinear PFD shown in Fig. 2 consists of

two dynamic TSPC circuits, four NAND gates, and two delay cells. A PFD is a sequential circuit which can both detect the phase error and provide a frequency sensitive signal to aid acquisition when the loop is out of lock. The fine-tuning current and the coarse-tuning current are controlled by the signals UP and UPE, respectively. When the phase difference ∆τ is large than τe, the coarse-tuning current is activated. On the other hand, a fine-tuning current is initiated to adjust a small phase difference (∆τ < τe) as depicted in Fig. 3. The characteristics shown in Fig. 4 can be divided into two regions. It has the same characteristics within the lock-in region as that of the linear PFD with fine-tuning current, but the acquisition time is decreased with the characteristics outside the lock-in region.

The loop filter is a third-order passive filter consisting of two resistors and three capacitors. The resulting PLL is then a type-2 fourth-order loop filter which provides great noise suppression for the switching activities to the output spurious level. Assuming KVCO to be 230MHz/V, the CP current icp is taken as 40 µA , and the constraints of the phase margin is 65°, which leads to the value of the passive element R1, R2, C1, C2, and C3 are 52kΩ, 170kΩ, 37.5pF, 1.4pF, and 140fF, respectively.

B. Voltage Controlled Oscillator While featuring the double cross-coupled structure, the

VCO avoids the bias current source in the conventional circuits. The bias current source often contributes to both 1/f 3 and 1/f 2 phase noise which affects the performance of a PLL [3]. The complementary cross-coupled structure is used for the low power and low phase noise design. The oscillation frequency of the complementary cross-coupled VCO is tuned through two inversion-mode pMOS capacitors and a 2.4nH spiral inductor. The implemented VCO has the tuning range of 5.19-5.53GHz. The phase noise is -135dBc/Hz at 10MHz offset. The average tuning sensitivity is 230MHz/V. The power consumption of the VCO with 1.5V supply is only 5mW.

UP

τeUPE

DNE

DN

fref

ffd

τe

MUR

MDR

MU1

MU2

MU3

MU5

MU6

MU4

MD1

MD2

MD3

MD5

MD6

MD4

Figure 2. Schematic of the nonlinear PFD.

t

fref

ffd

UP

UPE

icp

fref

ffd

UP

UPE

icp

∆τ < τet∆τ > τe

τe

∆τ∆τ

Figure 3. Timing diagram of the nonlinear PFD.

Figure 4. Characteristics of the linear PFD with fine-tuning current (dashed-line ) and coarse-tuning current (long dashed-line), and nonlinear

PFD (solid line).

C. Divide-by-8/9 Dual-Modulus Prescaler Fig.5 shows the divide-by-8/9 DMP. The DMP consists

of a divide-by-2/3 synchronous divider, a divide-by-4 asynchronous divider, and a control qualifier which controls the division of the DMP. To achieve faster operation of the high-speed divide-by-2/3 used in DMP, a TSPC D-flip-flop with an embedded NAND gate is used as shown in Fig. 6.

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D. Differential to Full Swing Converter The differential to full swing converter which is used at

the output of a divide-by-2 prescaler is shown in Fig. 7. The converter consists of an opamp which converts the differential input into a single-ended output. An inverter with feedback resistor amplifies the single-end output to a full swing level and decrease the dc gain.

E. Programmable Counter and Counter Detector The frequency divider employs two counter detectors and

a JK flip-flop (JK-FF) as shown in Fig. 8. The swallow counter in typical frequency divider is eliminated so as to simplify the circuit. The divide-by-32 programmable counter is directly connected to both the P-counter and S-counter detectors and their outputs are connected to both J and K inputs of the JK-FF, respectively. The DMP initially divides the frequency input by N+1 with the signal Mode being low. After the P-counter counts S output pulses from the DMP, it changes the signal Mode to high and the DMP starts to count by N. Since S is smaller than P, the P-counter always counts S first. It is noticed that the S-counter detector can detect S by the P-counter without employing another S-counter.

The method of determining the count values is explained in Fig. 9. Initially, the signal Mode is set to low and the division ratio of DMP is N+1 until the P-counter counts S. When the P-counter counts S, it is seen that PD is low and SD is high. Hence, the JK-FF turns to high and the division ratio of the DMP turns to N. When the P-counter counts S+1, both the input signals of the JK-FF are low and hold the state of the JK-FF. This state will be kept until the P-counter counts P. When the P-counter counts P, PD is high and SD is low. So the JK-FF sets to low and the division ratio of the DMP turns to N+1. At this moment, the P-counter becomes reset and the dividing cycle repeats. The total division ratio is given by following

( ) SNPSPNSNM +=−++= )(1 , (1)

where M is an integer of the total division ratio. In the proposed architecture, the synthesized output is given by

Mff refout ××= 2 , (2)

where fref is the reference frequency and fout is the output frequency. The factor of 2 in the equation accounts for the fact that a fixed-ratio divide-by-2 prescaler.

In the IEEE 802.11a systems, the radio frequency is from 5.725GHz to 5.825GHz. The intermediate frequency is 375MHz which results in a local oscillation frequency of 5.36GHz to 5.44GHz. The final synthesizer reference frequency is set to 10MHz. The DMP is divde-by-8/9. P is set to be 32, while S is set to be 12 to 16. The total division ratio is from 268 to 272.

F2

Control Qualifier

D Q

CLK Q

D Q

CLK Q

D

CLK Q

Q D

CLK Q

Q

Divide-by-2/3 Synchronous Divider

Mode

F8

Divide-by-4Asynchronous Divider

ToP-Counter

From the outputof JK-FF

From the outputof divide-by-2Prescaler

Figure 5. Dual-modulus divide-by-8/9 prescaler.

CLK

D1

D2

Q+

Q-

MP1

MN2

MN3

MP4

MN5

MN6

MP7

MN8

MN9

NANDGate

Figure 6. Schematic of D-flip-flop with embedded NAND gate.

IN- IN+ RfOUT

MP1 MP2 MP3 MP4

MN5 MN6

MN7 MN8

MPB

MNB

Figure 7. Differential to full swing converter.

2From

8/9 DMPOutput

2

Mode J

K

Q

2 2 2

Divide-by-32 Program Counter

S0 S1 S2 S3 S4

PD

SD

P CounterDetector

S CounterDetector

F8 F16 F32 F64 F128 Ffd

To PFD

To 8/9 DMP

Figure 8. Architecture of the proposed frequency divider.

IV. SIMULATION RESULTS The proposed frequency synthesizer with the nonlinear

PFD and the swallow-counterless divider is simulated using CMOS 0.18µm process parameters with 1.5V power supply. The simulated phase noise at 5.4GHz is shown in Fig. 10. At 10 MHz offset, the phase noise is -135dBc/Hz. The locking time (i.e. within 20ppm) is within 8µs as shown in Fig. 11.

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The switching time is below 5µs when M is switched from 268 to 272, which corresponds to the frequency switching from 5.36GHz to 5.44GHz for the synthesizer output. The chip consumes 7mW at 1.5V and occupies 0.98mmx0.8mm. The chip layout is shown in Fig. 12. The performance of proposed synthesizer is summarized in Table I with those of the same process synthesizers for comparison.

V. CONCLUSION A 5.4 GHz low power and fast switching synthesizer has

been demonstrated in a standard 0.18µm CMOS technology. The dual-slope characteristic of the nonlinear PFD and the CP can effectively reduce the acquisition time and enhance the switching speed. The proposed simple frequency divider is designed without a swallow counter. The synthesizer frequencies between 5.36GHz and 5.44GHz in steps of 20MHz from a reference signal at 10MHz. The phase noise is -135dBc/Hz at 10MHz offset. The switching time of the proposed circuit is below 5µs. The synthesizer consumes 7mW and occupies a chip area of 0.78mm2. The simulation results show the advantages in both the power consumption and the chip area.

REFERENCES [1] S. Khadanga, ‘Synchronous programmable divider design for PLL

Using 0.18 µm cmos technology’, The 3rd IEEE International Workshop on System-on-chip for Real-Time Applications, pp. 281-286, 2003.

[2] C. Y. Yang and S. I. Liu, “Fast-Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1445-1452, Oct. 2000.

[3] S. Levantino, C. Samori, and A. Bonfanti, “Frequency Dependence on Bais Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1003-1011, Aug. 2002.

[4] G. C. T. Leung and H. C. Luong, “A 1-V 5.2-GHz CMOS Synthesizer for WLAN Applications,” IEEE Journal of Solid-State Circuits, vol. 39, No. 11, pp.1873- 1882, Nov. 2004..

[5] A. Marsolais, M. N. El-Gamal and M. Sawan, “A CMOS Frequency Synthesizer Covering the Lower and Upper Bands of 5GHz WLANs,” Proceeding of the 46th IEEE International Midwest Symposium on Circuits and systems, vol. 3, pp.1146-39, Dec. 200.

Figure 9. Output waveform of the frequency divider (S = 14).

10.0 100. 1.00k 10.0k 100.k 1.00M1.00 10.0M

-120

-100

-80

-60

-140

-40

Offset Frequency (Hz)

Pha

se N

oise

(dB

c/H

z)

Figure 10. Simulated phase noise (carrier frequency 5.4 GHz).

Figure 11. Transient response of the frequency synthesizer.

Figure 12. Chip Layout.

TABLE I. SUMMARY AND COMPARISON TABLE Design [4] [5] This Work Process

Technology 0.18 µm CMOS

0.18 µm CMOS

0.18 µm CMOS

Supply 1V 1.8V 1.5V Freq.(GHz) 5.45~5.65 5.15~5.825 5.36~5.44

Reference Freq. 11MHz 19MHz 10MHz Bandwidth 100kHz 65kHz 275KHz VCO Gain 100MHz/V 667MHz/V 230MHz/V

Phase Noise -136dBc/Hz @20MHz

-107dBc/Hz @10MHz

-135dBc/Hz @10MHz

Settling Time < 51 µs 520µs < 8 µs

Power (mW) 27.5 7.2 (Excluding VCO) 7

Size (mm2) 1.03 0.72 0.78

F8

PD

SD

Mode

Time (µsec)

ffd

Time (µsec)

Freq

uenc

y (M

Hz)

360