Wafer Scale Integration of 2003

8/8/2019 Wafer Scale Integration of 2003

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Wa f e r - s c a l e I n t e g r a t i o nO f

A n a l o g N e u r a l N e t w o rk

Presented By- Manjunath B


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ABSTRACT

INTRODUCTION

THE BIOLOGICAL MODEL

THE MATHEMATICAL MODEL

OVERVIEW OF THE FACETS HARDWARE THE HICANN CHIP

ANNCORE circuits

NEURON-TO-NEURON COMMUNICATION

V. SUMMARY REFERENCES


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This paper introduces a novel designof an artificial neural networktailored for wafer-scale integration

This paper includes continuous-time

analog neurons with up to 16kinputs.

A novel interconnection and routingscheme allows the mapping of amultitude of network models

A single 20 cm wafer contains about60 million synapses. A novel asynchronous low-voltage

signaling scheme is presented.


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A key aspect of neuroscience is the modeling

of neural systems

the statistical nature of the neural code often

requires several repetitions of a simulation

In this paper, a novel concept for themodeling of large networks is presented

In contrast to most other VLSI

implementations the presented neural

network is targeted at large-scale network

models which are currently limited by theavailable computing resources

The maximum number of pre-synaptic signals

a neuron can receive changed from 256 to 16k


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The Biological Model


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The Mathematical Model


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the FACETS hardware model consists of a large

number of ASICs containing the analog neuron and

synapse circuits.

Flip-Chip technology leads to complicated andexpensive printed-circuit boards and high packaging

costs hence a different approach is used in FACETS:

wafer-scale integration.

A biological neural network is inherently fault tolerantagainst random neuron loss.

The power consumption is the major issue in realizing

wafer-scale integration for the presented analog

neural network.


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Fig. 1. A FACETS-wafer with motherboard and mounting bracket.

From top to bottom: top mounting bracket, motherboard

containing digital network chips, FPGAs and passive

components, elastomeric connectors, silicon wafer with analog

network chips, seal ring, bottom mounting bracket.


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A FACETS-Wafer containing 56 complete reticles. The dashed arrows depict

one bundle of horizontal respectively vertical inter-neuron connections.A single

reticle is enlarged showing the arrangement of the analog neural network chips

(ANC). The number of wires is given for each type of connection created by

wafer post-processing.


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The initial version of the ANC is called HICANN (High

Input Count Analog Neural Network).

It contains the mixed-signal neuron and synapse

circuits as well as the necessary support circuits andthe host interface logic


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Fig. 3. Block diagram of a HICANN chip


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Fig. 4. Block diagram of the analog

network core


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The synapse drivers are theinterface between theserialized event data and thesynapse array

The received 6 bit pre-synaptic neuron address issplit in two parts

Each synapse driver canaddress all 256 membranecircuits in its ANNCORE half

As illustrated in Fig. abovethere are always twosynapses connected to thesame membrane circuitsharing a synapse driver


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the synaptic weight is stored in a4 bit static RAM cell.

A 4 bit digital-to-analog

converter (DAC) translates the

stored weight into an output

current. The major change is the

inclusion of a four bit address

decoder replacing the single

pre-synaptic signal used

previously.

Each synapse has a fixed

connection to one of the strobe

signals from the synapse driver

and a programmable four bit

address

Fig: artificial synapse

320 x 275 - 21k


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A neuron is formed by connecting together anarbitrary number of dendrite membrane circuits,called denmem.

Each denmem contains a set of ion-channelemulation circuits connected to the membranecapacitance.

The synapses are connected to the denmemcircuits by two lines running orthogonal to thepre-synaptic inputs.

The denmem circuit converts these currents intotime-varying conductances emulating twodifferent groups of synaptic ion channel


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Operational amplifier OP1,

together with capacitor C and

tunable resistor R, forms a leakyintegrator for the synapse

output current.

Operational trans conductance

amplifier OTA1 co nverts the

output voltage of OP1 which

corresponds to the integrated

synapse current to a

proportional output current.

The neuron builder is a switch

matrix connecting groups of

denmem circuits together.

Eight asynchronous priority

encoders with 64 inputs each

determine which action

potential is transmitted back

into the network.


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The length of a wire traversing a HICANN dieis about 10 mm.

Depending on separating distances this wire

will see a total capacitance to its surrounding

of about 2pF13.

power consumption pwire can be calculatedas follows:

pwire = CV 2 Events/s [W]


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The timing parameters for the typical process corner are:

tframe=4 ns, tbit=500 ps and the differential DC amplitude Vl1=150 mV.


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B. Serial L1 Components

1)NeuronL1 Interface


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2) Repeaters:


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At each intersection of a horizontal and a vertical L1segment a crossbar switch is located which allowsconnections between the horizontal and vertical L1 buslanes.

The vertical lanes run in parallel to the synapse drivercolumns located at both sides of the ANNCORE.

A sparse switch matrix allows the coupling of any L1 lane toa synapse driver.

To control the capacitive loading of the vertical L1 bussesonly a certain number of switches and activated connectionsto the synapse drivers is allowed.

Space considerations permit a fully connected crossbar butthe capacitance of the de-selected transistors increases theRC-time constant too much. Therefore a sparse matrix isused for all cross-over points.


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The synapse driver uses the same receiver

and DLL as the repeater.

The receiver DLL provides the necessary

timing information to reliably control the

strobe pulse length STDF which controls

the synapse output current. To limit the power consumption and

crosstalk of the parallel L1 data a reduced

voltage swing of 1/2 Vdd (0.9 V) is used

inside the synapse array.


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There are two possible sources for an L1 bus:a neuron from ANNCORE or an external

event arriving at a DNCL1 converter.

The DNCL1 converter translates the

synchronous event packet into an L1 frame.

The digital controller of the HICANN uses aclock frequency of 1/tframe generated by an

internal PLL from the external reference

clock transmitted via the DNCHICANN

link.


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When using the maximum number ofinputs by connecting large numbers of

denmem circuits through the neuronbuilder, the total neuron numberbecomes quite low.

a single HICANN implements eightneurons with 16k synapses each

With eight neurons a 6 bit L1 bus can notbe fully utilized.

To overcome this problem, each HICANNcontains a special L1 repeater that is ableto merge the output of a local neuron into

a partially filled horizontal L1 bus lane


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This paper gives an overview of thecircuit techniques necessary to

implement a wafer-scale analog neural

network with a programmable topology


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1. power consumption.

2. fault tolerance3. The transferability of biological

networks.


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[1] W. Gerstner and W. Kistler, Spiking Neuron Model s: Single

Neurons,

Populations,Plasticity.Cambridge University Press, 2002.

[2] S. Renaud, J. Tomas, Y. Bornat, A. Daouzli, and S. Sa ghi,

Neuromimetic

ICs with analog cores: an alternative for simulating spiking neural

networks, in ISCAS, 2007, pp. 33553358.

[3] M. Lundqvist, M. Rehn, M. Djurfeldt, and A. Lansner, Attractor

dynamics in a modular network model of neocortex. Network, vol.

17, no. 3, pp. 25376, 2006.


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