A System to Simulate the Behavior of

Distribution Systems Voltage Regulators withEmbedded Software IP Core Control

Manoel Firmino de Medeiros Junior, Ivan Saraiva Silva, Max Chianca Pimentel Filho, Jose AlbertoNicolau de Oliveira, and Janio Mendonca Junior.

Abstract-This paper proposes a system to simulate the be-havior of distribution systems voltage regulators with embeddedsoftware IP core control, in MatLab Simulink with Altera DSPbuilder blocks. This system can be applied for real unbalancedthree-phase systems containing three-phase banks of singlephase regulators connected in Delta or Open-delta configura-tions. For the output voltage adjustment, the signal received fromthe network will be the output voltage of the PTs and the outputsignals to the equipment will be the control signals that will actin the tap change motor of each one of the single regulators.

Index Terms - IP core, Platform-based Design, PowerDistribution Systems, Sensitivity Parameters, Simulation System,Voltage Regulators.

I. INTRODUCTION

IN order to ensure voltage quality, electric energy companiesuse to include voltage regulators along of distribution

feeders. However, the localization of these equipments isstrongly dependent on network topology and until now, it hasbeen guided by exhausting load flow analyses, consideringforecasted loading curves with daily and seasonal changes [1].The industry of regulation equipments presents solutionsbased on control modules with proprietary protocols toperform voltage regulation on a local or on a remote node, bytransformer tap changes and a network equivalent impedancemodel, using voltage measures provided by a PT (PotentialTransformer) and, simulating a Line Drop Compensator-LDC, as shown in Fig. 1, using still current measures

supplied by a CT (Current Transformer).Many load flow calculations carried out in real feeders

showed that, by constant loads, the relationship betweenvoltages of all downstream nodes and the output voltage of the

This work was supported in part by the CAPES - Coordenacao deAperfeicoamento de Pessoal de Nivel Superior.

M. F. de Medeiros Jr is with Departamento de Engenharia daComputacao, UFRN, BR (e-mail: firmino dca.ufrn.br).

I. S. Silva is with Departamento de Informatica e Matematica Aplicada,UFRN, BR (e-mail: ivangdimap.ufrn.br).

M. C. P. Filho. is with the Programa de P&s-graduafao em EngenhariaEletrica, UFRN, BR (e-mail: maxchianca hotmail.com).

J. A. N. de Oliveira is with the Departamento de Engenharia Eletrica,UFRN, BR (e-mail: nicolau&frnetbr)

J. M. Juinior is with the Programa de P&s-graduafao em EngenhariaEletrica, UFRN, BR (e-mail: janiomjunior(digizap.com.br).1-4244-0288-3/06/$20.00 (©2006 IEEE

regulator can be approximated by a linear function.Similarly, for fixed tap conditions voltages of all

downstream nodes change linearly for usual daily loadexcursions. These results suggest that it is possible to providevoltage regulation in real time using the embedded functioncoefficients and the voltage measures provided by a PT,eliminating necessity ofLDC and CT [2][3].

sri Tc L ~~~~~~~~~rx

S TCC LV igtc1. Vr

TP

I ~~~~V/tp vsc

A software IP core and a first platform embedded in singlephase voltage regulators were proposed [3], as shown inFig. 2. The IP core is aimed to control adaptableparameters of the regulator, in real time. It was described inVHDL, implemented and validated at a FPGA[4].

This system can be applied in real unbalanced three-phasesystems, which use three-phase regulators banks, built fromsingle phase regulators in delta or open-delta configurations[5].

Besides costs reduction, the main advantage of this newembedded technology is the quickness that regulation settingscan be implemented.A system for simulations and tests of the IP Block for

voltage adjustment is proposed as MATLABW embeddedfunctional blocks for use in Simulink with AlteraR DSPbuilder blocks.

II. THEORETICAL BACKGROUND

A. DevelopmentplatformThe monitoring and control of power equipments used in

electric energy distribution systems demand a circuit modelconsisting of a power module and of a control module. Thepower module is responsible for the interface of analogicalsignals of sensors and actuators of the high voltage equipment

2

with digitals input and output signals of control module.Whereas the control module is responsible for the informationprocessing, according to a specified control algorithm, and forthe generation of control signals necessaries for the powermodule. Considering the above description, a developmentplatform was proposed [4], totally configurable in FPGA, thatpermits the implementation and simulation of embeddedmechanisms for voltage regulators. By the block diagram ofthe proposed platform, shown in Fig. 2, the communicationof the power module with the control module is done using aDA converter, a microcontroller that already annexed an ADconverter and a wrapper microcontroller/main bus [6].

From many load flow calculations, carried out in sixteenreal feeders, was concluded that, the voltages of alldownstream nodes change linearly with the output voltage ofthe regulator, considering constant loads, as shown in Fig.4, for nodes 7, 1 1 and 21 of the feeder of Fig. 3, used in oneof the simulations [3][4]. Similarly for a fixed tap condition,the voltages at all downstream nodes change linearly forloading excursion at usual intervals of daily load curve, assuggested in Fig. 5 [3][4]. From those observations wasconcluded that it is possible to control, in real time, theregulation voltage, at any downstream node, having thefunction coefficients embedded. The function defines, foreach node, this linearization. The voltage variation at theregulation point can be calculated by (1).

22 23 24 25

RAM FlashRA RAMIP Blocks

Fig. 2. Block diagram of the proposed platform.

By defining the control module two fast prototypingplatforms were used: the Nios® II Development Kit,Cyclone.TM II Edition and the DSP Development Kit,Cyclone.TM II Edition, both by Altera®.

In respect to the control module, it must be emphasized theincorporation of the real time operational system [tCOS2 [1]in the Central Core and the inclusion of a Software IP Corefor the adjustment of output voltages in three-phase regulatorsbanks.

For the output voltage adjustment, the signal received fromthe network by the power module will be the output voltage ofthe PTs. The output signals to the equipment will be thecontrol signals that will act in the tap change motor of eachone of the single regulators.

B. Algorithm for adjustment ofthe regulation voltageAs can be observed in Fig. 1, the output regulation

voltage of the regulator or of a remote node is adjusted fromsample voltage, obtained by a PT, and from drop linecompensation, proportional to the current provided by a CT.This takes into account a simplified model (r + jx), for thefeeder portion downstream of equipment, such as a loadmodel regularly distributed. This behavior, naturally, does nothappen.

I I I I I 142 41 40 39 38

37 36ll

Fig. 3. Feeder used in one of the simulations.

With coefficients stored, at all nodes downstream of theregulator a voltage variation on the regulator node (output ofthe equipment) will produce a voltage in the regulated nodeshowed by (2). Furthermore, a load variation Afc will causevoltages in the regulator and regulated nodes as show (3) e(4). A relationship between both voltage changes is given by(5).

This way, it will be possible to obtain the output voltage( med ) and estimate the voltage in the regulation node (Vjt )

in accordance with (6).

av. av.AV,=1 XAV + X Afcav, afc

V1Vant ±v Vant)avj

Vj = Vj a+ Afcafc

(1)

(2)

(3)

=aint aVj ANf

avjv_ V ant ± afc (v,~ant)

d (avafc

est Van (med eantV=

I-

Vi

3 - Verify how many steps, relatively to the present(4) position of the tap, should be raised or lowered to get this

objective, assuming a whole step for calculated values in therange (50%; 100%), and no steps elsewhere.

4 - Analyze the impacts of these tap changes at voltageprofile.

(5) 5 - Sends the signal for a tap changing if no restriction isviolated; otherwise reevaluate the tap change according to theprocedure of previous step.

6 - Return to step one.

(6)

Where V. is the regulation voltage at node j, Vi is theI

output voltage of the regulator, V1 ant is the regulation

voltage at node j before the variation, Viant is the outputmewdvoltage of the regulator before the variation, Vi is the

output voltage of the regulator after the variation, and f, isthe Loading factor at node j.

Node 7Node 1 1Node 21

0,2

00,942029 0,971014 1 1,028986 1,057971

Regulator Voltage(pu)Fig. 4. Voltage behavior at nodes 7, 1 1 and 21 for different output voltages ofthe regulator.

Node 7

Node 11

Node 21

0,4

0,2

0O0.5 0.75 1.0 1.25 1.5

Loading

Fig. 5. Voltage behavior at nodes 7, 1 1 and 21 for different loading factors.

The control algorithm of the regulation voltage consists on

the following steps, which are done in real time operation:1 - Monitor the output voltage of the regulator until a

voltage variation higher or lower to a voltage step caused by a

tap is registered.2 - Estimate the output voltage of the regulator to obtain

the condition previous to the variation.

III. SYSTEM TO SIMULATE THE BEHAVIOR OF DISTRIBUTIONSYSTEMS VOLTAGE REGULATORS

In order to validate the voltage control algorithm presentedand to simulate the behavior of distribution systems voltageregulators, a system for simulations and tests of the IP Blockfor voltage adjustment is proposed as MATLABW embeddedfunctional blocks for use in Simulink with AlteraR DSPbuilder blocks. This system, shown in the diagram of blocks inFig. 6, it allows to:

- visualize the behavior of distribution systems voltageregulators;

- characterize feeders, regulators parameters and regulationrestrictions;

- visualize regulations adjustment values;- simulate load and voltage variations.

lutRAMp NTC Retapictontro

lutRAMc (Voltage nbhcarespectivel, the volAdjustment Cfondfitienos

Reset u l/ TCU N ~Tap Control

tTaao SignalsMeasure e m e ADConra

positioin ofteoa,nbaie tromtelCU(acotl

uit). Sampler Unit)

Fig. 6. Block diagram of the proposed model.

In the block diagram shown in Fig. 6, the units,lutRAMp and lutRAMc, are look-up tables that store,respectively, the voltage profile and the voltage coefficients ofall nodes of the feeder. The Sampler unit allows to simulatethe behavior of the circuit based on a signal effectivelymeasured, obtained from the ADC or a value of currentpositioning of the Tap, obtained from the TCU (tap controlunit).

All timing is carried out by the State Machine (StM block),allowing to control through the InLoad signal if in presentsimulation a new voltage profile and new voltage coefficientsshould be loaded. The initial conditions and the restrictions,supplied for its respective blocks, always they are evaluated.

The main units of the model are the Voltage AdjustmentUnit (VAU) and the Tap Control Unit (TCU). The VAU isresponsible for the necessary analyses to estimate the output

3

1,2

a,) 1

' 0,8

2 0,60E" 0,4

10-

m 0,8m

> 0,6-

4

voltage in the regulating node which, that will guarantee thedesired voltage in regulated node. The TCU is responsible forthe tap changes, for the update of regulator output voltage andfor monitoring voltages measured. The implementations of theVAU and the TCU are shown in Fig. 9 and 10,respectively.

The full implementation in Simulink of the IP Core foradjustment of voltage of a single-phase regulator is shown, insimulation time, in Fig. 7 and 8. Fig. 7 characterizes asimulation in the feeder of Fig. 3 which includes aregulating bank at node 7. The node with regulated voltage isnode 10. The regulated voltage is approximately 0,97 p.u. Inthe instant of the capture of the figure, the estimated outputvoltage for the regulator was 1.02286767 p.u., the initialvoltage was of 1.0007681157 p.u, that tap was in position 3,and for this situation, the output voltage is 1.0195181146 p.u.The tap will be kept in this position until the end of thissimulation.

Figure 8 shows a simulation for the same feeder, regulatingnode 10 in 0.88 p.u. In the instant of the capture of the figure,the estimated output voltage for the regulator is 0.932311264p.u, which initial its voltage was of 1.0007681157 p.u, that tapis in position -3, resulting in an output voltage of0.9820181141 p.u., still far away of the estimated voltage byVAU. The final tap value is -6.

At the top of Fig. 7 and 8, one observes the presence ofthree components constituent of the DSPBuilder tool ofAltera®. The left one is the SignalCompiler Altera Cyclone II,the middle one is EP2C35 DSP Development Board and theright one is the SignalTap II Analysis.

circuit recorded and is analyzed during a simulation in anoperation, in real time, with EP2C35 DSP DevelopmentBoard. In this stage, the IP Core of adjustment of voltage wasimplement in fast prototyping platform DSP Development Kit,Cyclone.TM II Edition.

Fig. 8. Model of the voltage control algorithm simulation for the feeder with aregulator at node 7, regulating the node 10 in 0.88 p.u.

Blooo de 1Inid.i.izO.3

Fig. 7. Model of the voltage control algorithm simulation for the feeder with a

regulator at node 7, regulating the node 10 in 0.97 p.u.

Through SignalCompiler Altera Cyclone lI the constructedmodel in Simulink could be compiled, described in VHDL,synthesized and programmed in FPGA. Additionally, some

archives can be generated that allow the system simulation inModelSimT or Quartus hIM of Altera®.

The inclusion of the SignalTap II Analysis in the modelallows that timings of the signals presents in the buses of the

Fig. 9. Voltage Adjustment Unit

IV. CONCLUSIONS

In summary, the main advantages of this new embeddedtechnology are the quickness with that the regulations settingsat the regulator will be implemented and the eliminations ofthe LDC and the CT. These factors allow that the voltageregulator design can be simplified, and its costs can bereduced.

With this simulator circuit, the task of excellentlocalization of the regulating bank of a feeder is extremelyfacilitated. Beyond the one that, a feeder change requires asimple recharge of the two look-up tables, ltuRAMp andltuRAMc.

As sequence of this work, this simulation circuit could be

M. ..",-4rQ

6q6,"Uo-----Ww,m[4rM"pj [..

D,Pvil NAPM ."Pvi ..,LD..

5

expanded to show the behavior and the caused effect in theinter-relationship of a regulation bank with two regulators, inopen-Delta configuration, or with three regulators, in Deltaconfiguration.

S.bsist... de controle de tap

joined Computer Science Department of the Federal University of Rio Grandedo Norte State, Brazil, where he started to work with design coarse-grainedreconfigurable architecture, reconfigurable instruction Set processors,platform-based design, reuse-based design and MP-SoC. His current projectsare mainly applied to Interactive Digital Television and System on Chipintegration.

M. Chianca Pimentel Filho was born in Recife-RN/Brazil. He received hisEngineer Degree at UFCG-Campina Grande in 1994, and his M Sc. Degree atUFRN- Natal in 1997. The Dr Sc Degree he obtained in Natal UFRN in 2005.Nowadays he works in load flow calculation and optimization of electricaldistribution power systems.

Jose Alberto Nicolau de Oliveira obtained his degree in electricalengineering at Federal University of Rio Grande do Norte, Brazil, in 1977 andthe M.Sc. degree in electrical engineering from the Federal University ofParaiba State, Brazil, in 1981. He has worked in the Electrical EngineeringDepartment of the Federal University of Rio Grande do Norte, Brazil, wherehe work with digital systems, microcontrollers, platform-based design andreuse-based design.

Fig. Tap Control Unit

V. ACKNOWLEDGMENT

The authors wish to thank Coordena,co deAperfei,oamento de Pessoal de Nivel Superior- CAPES forthe financial support.

VI. REFERENCES[1] M. F. de Medieros Jr and M. C. P. Filho, "Localizacao Otima de Bancos

Trifasicos de Reguladores de Tensao em Alimentadores Radiais deDistribuicao", presented at the IV CBA, Natal, Brazil, 2002.

[2] M. C. P. Filho, M. F. de Medeiros Jr, J. A. N. de Oliveira, M. A. deAlmeida, "Linearizacao dos Parametros de Sensibilidade Tensao XTensao e Tensao X Carregamento para Regulacao Remota em

Alimentadores de Media Tensao", presented at the VII INDUSCON,Recife, Brazil, 2006.

[3] J. A. N. de Oliveira, M. F. de Medeiros Jr, M. C. P. Filho and I. S. Silva,"Embedded Platform And Ip Core for Adjustment ff Regulation Voltagein Electric Energy Distribution Systems", presented at the VIIINDUSCON, Recife, Brazil, 2006.

[4] J. A. N. de Oliveira, M. F. de Medeiros Jr, M. C. P. Filho and I. S. Silva,"IP Core For Regulation Voltage Adjustment In Electric EnergyDistribution Systems", presented at the IP-SOC 2005, Grenoble, France,2005.

[5] M. C. P. Filho, M. F. de MEDEIROS Jr, J. A. N. de Oliveira, "Three-phase Models of Voltage Regulators for the Power Summation LoadFlow", presented at the VI INDUSCON, Joinville. Brazil, 2004.

[6] I. S. Silva, J. A. N. de Oliveira, K. D. N. Ramos, N. Santiago, A. Casillo,"Projeto baseado em Reuso: Implementacao de um IP de processadordidatico em FPGA com Interface OCP", presented at the X IBERCHIP,Cartagena de Indias, Colombia, 2004.

VII. BIOGRAPHIESM. Firmino de Medeiros Jr. was born in Macaiba-RN/Brazil. He recievedhis Engineer Degree at UFRN-Natal in 1977, and his M.Sc. Degree at UFPB-Campina Grande in 1979. The Dr.-Ing. Degree he obtained in Germany, in1987. From 1987 until 1990 he was Engineering Director of the Power SupplyCompany - COSERN in State of Rio Grande do Norte. From 1990 until 1992he was Coordinator of the Electrical Engineering Post-graduate Program atUFRN-Natal, and for the last four years he was Head of the Department ofComputer Engineering at the same University.

Ivan Saraiva Silva received the M.S. degree in electrical engineering fromthe Federal University of Paraiba State, Brazil, in 1990 and the Ph.D. degreefrom the Universitee Pierre et Marie Currie, France, in 1995. In 1996, he

Jainio Mendonsa Junior was born in Parelhas-RN/Brazil. He obtained hisdegree in computer engineering at Potiguar University, Brazil, in 2005. He hasworked in the Electrical Engineering Post-graduate Program of the FederalUniversity of Rio Grande do Norte, Brazil, where he works with digitalsystems.