IEEE 1394 A high-speed computer I/O serial bus CASI / ELEC 98 By Rachad ALAO Ecole Nationale...

IEEE 1394 A high-speed computer I/O serial bus

CASI / ELEC 98

By Rachad ALAO

Ecole Nationale Supérieure des Télécommunications

[email protected]

mailto:[email protected]




PC

Video Camera

DVD -RAM

IEEE 1394, by Rachad ALAO ( [email protected] )

What’s the best way to interconnect these devices ?





PC

Video Camera

DVD -RAM


What’s the best way to interconnect these devices ?

•Why not with USB? Too slow!•Why not with a SCSI bus? Fast enough, but…•What about an IEEE 1394 bus? You’ve got it!

Isochronous Traffic.Bandwidth Requirement : 6Mbit/s

Sporadic traffic.Bandwidth Requirement : 16Mbit/s





IEEE 1394 Lecture Plan


I. How does IEEE 1394 work ?• Overview• Topology• Type of Transaction• Protocol’s Structure• Example of Data Transfer

II. Architecture of a IEEE 1394 Controller.• Project Overview• Functional Block Overview• Block Level Detailed Architecture• Transaction Layer, driver.

III. Conclusion.





How does IEEE 1394 work ? Overview

IEEE 1394, by Rachad ALAO ( [email protected] ) Back to Lecture Plan

• High Speed• Hot plug and play• Isochronous capable• “Memory-bus-like” logical architecture





How does IEEE 1394 work ? Topology


Local Bus i

Bridge 1 Bridge 2

Node A

Node B

Node C Node D

Node E

Node A

Node B Node C

Node D Node E Node F

Local Bus 1 Local Bus 2

CablePortion

port

• Physical topology is a non-cyclic network but Logical Topology is a bus.• Node_ID[ 15 .. 0] = Bus_ID[15 .. 6] || Physical_ID[ 5 .. 0]





How does IEEE 1394 work ? Type of Transaction


Different type of subaction :• Asynchronous subaction• Asynchronous broadcast subaction• Isochronous subaction

Different part of a subaction :• Arbitration sequence• Data packet• Acknowledgment

Typical structure of a data packet





How does IEEE 1394 work ? Protocol’s Structure


Different managers needed :• ROOT ( Arbiter )• CYCLE_MASTER• ISOCHRONOUS MANAGER• BUS MANAGER





How does IEEE 1394 work ? Example of Data Transfer 1


PC

RootIsochronous ManagerBus ManagerCycle MasterNode_ID = 3

Video Camera

Node_ID = 1

DVD -RAM

Node_ID = 2







Cycle_Start Ch. i Ch. j

Isochronous Gap Subaction Gap

Cycle_Start Ch. i Ch. j

Arbitration

Data Packet

TX_DATA_END

Cycle_Start Ch. i Ch. j Data Packet

Acknowledge Gap

Acknowledge Packet

• Step 1 :

• Step 2, 3, 4 :

• Step 5 :

DVD RAM want to perform a write data block transaction to the PC







• Step 1 :

• Step 2, 3, 4 :

Camera sends MPEG2 data to the PC at a 6 Mbit/s fixed rate.

Cycle_Start

Isochronous Gap

Cycle_Start

Arbitration

Ch. K Data Packet

TX_DATA_END

• Prior to all its isochronous transfers, the camera must allocates bandwidth and channel.





Architecture of a IEEE 1394 ControllerProject Overview


CPU

Mem

ory

Chipset

Loc

al B

usP

CI

Bus

IEEE 1394Controller

Generic PC

IEEE 1394Controller

CPU

Mem

ory

Loc

al B

us

Generic Deported App

IEE

E 1

394

Cab

le





Architecture of a IEEE 1394 ControllerFunctional Block Overview


TPA

TPB

Power Phy

Lay

er

Lin

k L

ayer

FIF

O C

ontr

olle

r

Loc

al H

ost B

us A

dapt

er *

ReceiveTransmit_Granted

HoldLink_request

Link_DSR/W

Add[7..0]

Link_Data[7..0]

Clk ( 50 Mhz )Link_On

Power_Down/Reset

Phy_DS

Phy_Data[7..0]

Host_DSR/W

Host_Add[7..0]

Host_Data[31..0]

FIFO_DS

FIFO_Data[31..0]

Clk ( 33 Mhz )

/Reset

INT

* Local Bus Adapter Interface is Bus Dependent! No generic interface can be given.

Clk ( 50 Mhz )

/Reset

FIFO_DS

FIFO_R/W

FIFO_Add[7..0]

FIFO_Data[31..0]

Link_DS

Link_Data[31..0]

Link_Add[2..0]

Link_R/W

Transaction layer and part of the bus management will be software components ( driver )





Architecture of a IEEE 1394 ControllerBlock Level Detailed Architecture - PHY


Phy State Machine &Internal Regs

ReceiveData Decoder

Transmit Data Encoder

CableAnalogInterface


HoldLink_request

Link_DSR/W

Add[7..0]

Link_Data[7..0]


Power_Down/Reset

Phy_DS

Phy_Data[7..0]

TPA

TPB

Power





Architecture of a IEEE 1394 ControllerBlock Level Detailed Architecture - LINK



HoldLink_request

Link_DSR/W

Add[7..0]

Link_Data[7..0]


Power_Down/Reset

Phy_DS

Phy_Data[7..0]

Clk ( 50 Mhz )

/Reset

FIFO_DS

FIFO_R/W

FIFO_Add[7..0]

FIFO_Data[31..0]

Link_DS

Link_Data[31..0]

Link_Add[2..0]

Ph

y In

terf

ace

Transmitter

Receiver

CRC

CRC

Isoch. Manager

Isoch. Monitor

Link State Machine and Registers Link_R/W





Architecture of a IEEE 1394 ControllerBlock Level Detailed Architecture - FIFO


Host AdapterInterface

FIFO Controller &Internal Regs

LinkLayerInterface

General Receive FIFO

Asynch. Transmit FIFO

Isoch. Transmit FIFO

Host_DSR/W

Host_Add[7..0]

Host_Data[31..0]

FIFO_DS

FIFO_Data[31..0]

Clk ( 33 Mhz )

/Reset

INT

Clk ( 50 Mhz )

/Reset

FIFO_DS

FIFO_R/W

FIFO_Add[7..0]

FIFO_Data[31..0]

Link_DS

Link_Data[31..0]

Link_Add[2..0]

Link_R/W





Architecture of a IEEE 1394 ControllerTransaction Layer, driver


• The Transaction layer and part of the bus management functions

must be software components.

• Transaction layer must implement Read, Write and Lock transaction.

• Driver must offer ability to handle isochronous transfer.

• Driver must be IRQ driven and able to initiate DMA transfers.

• Driver model will depend on the target application OS.





Conclusion


Objectives :

• Give a synthesis of the IEEE 1394 Bus standard

• Give a Hardware Specifications of an IEEE 1394 Solution

• Constitute a good starting for the development of an IEEE 1394 Solution

Reached !

+ Gave me a good understanding of the IEEE 1394 Protocol

- Showed me the difficulty to build specifications from a complex standard

- No multicast for asynchronous packets! Surprising for such a complicated

standard.

IEEE 1394 A high-speed computer I/O serial bus CASI / ELEC 98 By Rachad ALAO Ecole Nationale...

Documents

Transcript of IEEE 1394 A high-speed computer I/O serial bus CASI / ELEC 98 By Rachad ALAO Ecole Nationale...