ICC1 200703 IG 01 Basicflow

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Agenda

© 2007 Synopsys, Inc. All Rights ReservedSynopsys 20-I-071-SSG-007

DAYDAY1

Introduction & Overviewi

IC Compiler Basic Flow1

Placement, Power & Test2

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Unit Objectives

After completing this unit, you should be able to:

Create a Milkyway library to hold your design

Read all necessary files required to run IC Compiler, resolving common errors/warnings

Set up timing for analysis and optimizations

Execute the basic flow for placement, CTS and routing in IC Compiler

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Unit Roadmap

Data SetupRead netlist and SDCSetup timing librariesSetup MilkywayApply the floorplan

Basic FlowPlacementClock tree synthesisRoutingAnalysis

Timing Setup and RC ModelingTiming variablesRC and TLU+ modelsDelay calculation

Break

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General IC Compiler Flow

SynthesisSynthesis

Unit 1Unit 1

Unit 2Unit 2

Unit 3Unit 3

Unit 6Unit 6

Unit 7Unit 7

Unit 5Unit 5

Design SetupDesign Setup

Design PlanningDesign Planning

place_optplace_opt

clock_optclock_opt

route_optroute_opt

Chip FinishingChip Finishing

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Placement, CTS, Routing with Optimizations

Placed, Routed & Optimized Designwith Clock Trees

Gate-Level Netlist

Optional: Floorplan

IP

ICCompiler

ICCompiler

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1. Tech File2. TLU +3. IO TDF file4. Netlist5. SDC

1. IO pads placed2. Chip/core boundary3. Cell rows, wire tracks

created4. Macro placement final

Output

place_optclock_optroute_opt

Chip finishing and DFM

Power plan

1. Std cells placed2. Clock tree(s) built3. Clock and signal

routing completed

Output

Floorplan

IC Compiler Data Flow

DEFDEF

MWMW

Design Planning

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Unit Flow: From Setup to Output

Logical Data Setup

Physical Data Setup

place_opt

clock_opt

route_opt

Analysis

Output7

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Logical Data

Gate-Level Netlist(s)

Logical Libraries.db

link

check_timing

create_clock –period 10 ...set_input_delay –max 1.2 ...set_output_delay –max 2.5 ...set_driving_cell .........

Logical (Timing) Constraints

Logical Data Physical Data place_opt clock_opt route_opt Analysis OutputLogical Data

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Reading Gate-Level Netlists from Synthesis

IC Compiler can open a Milkywaydatabase written by Design Compiler

And other formats supported by Design Compiler

You can read one or many files

read_ddc

read_verilog

read_vhdl

…

read_verilog file1.v file2.v …

Milkyway and DDC can also contain design attributes

!

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MY_TOP_DESIGN

No Multiply Instantiated Designs

IC Compiler does not support non-uniquified designs, i.e. designs with multiple instantiations!

When reading in a non-uniquified design, the first commands of your ICC script should be:current_design MY_TOP_DESIGN

uniquify

PARSER

PARSER1

PARSER2

PARSER3

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Logical Libraries

Provide timing and functionality information for all standard cells (and, or, flipflop, …)

Provide timing information for hard macros(IP, ROM, RAM, …)

Define drive/load design rules: Max fanout and transition Max/Min capacitance

Specified as follows:

Logical Libraries.db

set link_library "* gates.db io.db rams.db"

“*” = Search all designs in memory

Make sure the first specified db contains

the correct units

Make sure the first specified db contains

the correct units

!

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CCS Library Support

IC Compiler supports NLDM and CCS (Composite Current Source) libraries Current-based approach more accurately

models Timing, Noise, Power High impedance interconnect Miller effect Dynamic IR-drop Multi-voltage Temperature Inversion

NLDMs are not accurate enough for 90 nm and below Use CCS

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CCS Supported Throughout Galaxy

Tools Timing Noise Power

NanoChar

PrimeTime

IC Compiler

Design Compiler n/a

CCS SupportCCS Support

MilkywayMilkyway

Sig

noff

Sig

noff

Design CompilerDesign

Compiler

IC Compiler

IC Compiler

GalaxyGalaxy

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How does IC Compiler Find Files?

By default, you must specify the unix-path for all files (relative or absolute)

You may specify where to look for files:

The above paths will be used by IC Compiler for reading or accessing files

lappend search_path ./design_data ../scripts

lappend search_path [glob $MW_libs/*/LM]

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Target Libraries

Along with the link_library and search_path variables, you need to specify the logical library that will be used for mapping/optimization:

Typically, the target_library points to your standard cells only

set target_library "gates.db"

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**

Resolving References

Gate-level netlists contain references to standard cells and macros, which are stored in the logical libraries, as well as other hierarchical logic blocks

The link command will ensure that all references can be resolved

link risc_core

nand nor inv ff

sdram_if

Gate-Level Netlist(s)

mem.db

gates.db

ip.dbpci_core

link_library

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Shortcuts…

import_designs orca.v \

-format verilog \

-top ORCA_TOP

Replaces:read_verilog –netlist orca.vcurrent_design ORCA_TOPuniquifylinksave_mw_cel –as ORCA_TOP

Format can be verilog, db, ddc

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Timing Constraints

“Timing Constraints” are required to communicate the design’s timing intentions to IC Compiler

They should be the same ones used for synthesis with Design Compiler (preferably SDC)

create_clock –period 10 [get_ports clk]set_input_delay 4 –clock clk \

[get_ports sd_DQ[*]]set_output_delay 5 –clock clk

[get_ports sd_LD]set_load 0.2 [get_ports pdevsel_n]set_driving_cell –lib_cell buf5 \

[get_ports pdevsel_n]...

read_sdc timing_constraints.sdc

SDC = Synopsys Design Constraints

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Constraint Management

2006.06 and later2006.06 and later

remove_sdc

• Removes all SDC constraints

remove_ideal_network -all

• Removes ideal_network attributes, latencies and transitions

remove_annotations

• Removes all annotated delays, transition, resistance, capacitance, checks

To remove all settings:

reset_design

• Removes all optimization attributes (dont_touch, size_only…) and all constraints.

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Timing Check

Before proceeding, you should ensure that the design is completely constrained

IC Compiler will not optimize paths that are not constrained for timing

No checking for missing external loads or drive characteristics will be performed!

check_timing

!

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check_timing reports all unconstrained paths

False paths are also considered unconstrained!

To verify that unconstrained paths are OK:

Reports false paths set on design Compare these paths to the ones reported

by check_timing

report_timing_requirements

check_timing: False Paths

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Physical Data

check_physical_constraints

Constrained andlinked design Physical

Reference Libraries(Milkyway)

Floorplan

IP

Logical Data Physical Data place_opt clock_opt route_opt Analysis OutputPhysical Data

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Physical Libraries

Contain physical information of standard and macro cells necessary for placement

Define placement unit tile

reference point(typically 0,0)

Dimension“bounding box”

Pins (direction, layer

and shape)

VDD

GND

A B

Y

NAND_1

Blockage

Symmetry(X, Y, or 90º) F

Abstract View

FFBUF

INV

NOR

unit tile(site)

Reference Libraries(Milkyway)

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Milkyway Reference Libraries

Information is stored in so-called “views”, for example:

CEL: The full layout view

FRAM: The abstract view used for P&R

LM: Logic Model with Timing and Power info (optional*)

CEL/ FRAM/

and2a1

and2a2

….

xor3a27

and2a1

and2a2

….

xor3a27

VENDOR_XYZ_std_cell_90nmUsed for

P&R

lib_max.db

lib_min.db

….

LM/

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Technology File (.tf file)

Tech File is unique to each technology

Contains metal layer technology parameters: Number and name designations for each layer/via Dielectric constant for technology Physical and electrical characteristics of each layer/via Design rules for each layer/Via (Minimum wire widths

and wire-to-wire spacing, etc.) Units and precision for electrical units Colors and patterns of layers for display …

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Example of a Technology File

Technology {

dielectric = 3.7

unitTimeName = "ns"

timePrecision = 1000

unitLengthName = "micron"

lengthPrecision = 1000

gridResolution = 5

unitVoltageName = "v"

}

...

Layer "m1" {

layerNumber = 16

maskName = "metal1"

pitch = 0.56

defaultWidth = 0.23

minWidth = 0.23

minSpacing = 0.23

...

abc_6m.tf

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Specifying Reference Libraries

By creating a design library!

How are physical reference libraries and the technology file specified?

create_mw_lib design_lib_orca \

-technology techfile.tf \

-mw_reference_library “sc io ram32” \

-open

Now you are ready to apply the floorplan…

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Applying the Floorplan

RAM

Site ArraysArray of placement sites

ClusterHard Boundary

Keepouts &PG nets

Port LocationsSignal I/O

Fixed CellsExample: RAM placement

read_def my_floorplan.def –allow_physical

Allows physical-only objects like PG nets.

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Copying the Floorplan from another MW Cell

Useful if reading a new netlist of the same design that was floorplanned in IC Compiler or JupiterXT.

Cell_A

Cell_B

copy_floorplan

Existing un-floorplanned cell

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Opening a MW Design from JupiterXT

lappend search_path ../dbset link_library "* gates.db rams.db"set target_library "gates.db"

open_mw_lib my_jxt_lib.mwopen_mw_cel floorplannedset_tlu_plus_files ... ;explained later

remove_sdcread_sdc mydesign.sdc


save_mw_cel -as routed

Apply your timing constraints for P&R.

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Check Physical Constraints

Checks libraries and floorplan: Physical Logical library inconsistencies Insufficient core placement area Warns about narrow placement regions (Chimneys) Reports on number of physical_only_cells, available sites

and overall utilization RC parameters …see man page for more details

check_physical_constraints

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Once setup is complete, save the Milkyway design:

By default, link_library, search_path, target_library and TLU+ settings are stored with the CEL If library files change or move to somewhere else, the

settings have to be re-applied. See notes section below!

When you re-open the CEL, by default the stored settings are not re-applied, unless you set:

set auto_restore_mw_cel_lib_setup true

open_mw_cel orca_init

save_mw_cel –as orca_init

Saving and Loading the Design

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The Design Library

Design Librarydesign_lib_orca

Technology Fileabc_6m.tf

MWStandard

cells

MWMacro cells

MWPadcells

sc.db io.db

orca_initorca.v

orca.sdc

orca.def

Container for all data!

link_librarytarget_library

settings

TLU+ RC models

…more later

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UNIX Structure of a Design Milkyway Database

./design_lib_orca/

CEL/

Database T.O.C,

technology data etc.

….

…

orca_init:1

Saved Cell

MW Design Library

liblib_1lib_bck

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UNIX Manipulation of a Milkyway Database

UNIX% cd CEL

UNIX% rm ORCA_placed

UNIX% cp ~Joes_Lib/ORCA_placed .

STOP

./design_lib_orca/

…CEL/

ORCA_init

ORCA_floorplanned

ORCA_placed

ORCA_cts

ORCA_routed

liblib_1lib_bck

T.O.C. Corrupted!

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Test for Understanding

1. List the 2 variables that need to be set up to successfully read all design files!

2. What is the difference between the link_library and the target_library?

3. IC Compiler requires a chip-level floorplan including IO PADs. True / False

4. A floorplan must always be input to IC Compiler by reading a DEF file. True / False

5. Which of the following is not recommended?

a. lappend search_path my_pathb. set search_path my_pathc. set search_path "$search_path my_path"

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Summary

Gate-Level Netlist

Logical Library.db

Logical Constraints.sdcread_sdc

read_def

check_timingcheck_physical_constraints

read_verilog/vhdl/ddcset link_library "* sc.db"set target_library sc.db

create_mw_lib –technology …–mw_reference_library …

ICCompiler

Physical ConstraintsDEF or MW library

Ready for Place & Route

MW Reference Libraries

+ tech file

Or: import_design

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10 Minute Break

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IC Compiler Recommended Setup

# load common settings & useful procedures

source ../ref/icc_settings.tcllappend search_path ./scripts ../ref/sdb ../ref/dbset symbol_library "sc_icon.sdb io_icon.sdb"set link_library "* sc_max.db io.db ram16x128_max.db"set target_library "sc_max.db"

create_mw_lib design_lib_orca -open \-technology techfile.tf \-mw_reference_library "mw/sc mw/io mw/ram32"

set mw_logic0_net "VSS"set mw_logic1_net "VDD"import_designs design.ddc \

-format ddc \-top ORCA_TOP

read_def –allow_physical design.defsave_mw_cel –overwrite # CEL saved as ORCA_TOP

All setup done first and stored

in .synopsys_dc.setup

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.synopsys_dc.setup

.synopsys_dc.setup .synopsys_dc.setup

$SYNOPSYS/admin/setup~user

ICC startup directoryUser’s Specific Project Setup

User’s General Setup

StandardSetup

IC Compiler Three Initialization Files

Commands in .synopsys_dc.setup are executed upontool startup, in the order shown above.

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3

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Placement stage

Before starting placement & optimization:

Do not over-constrain the design Constraints should match design

specification

Report timing before placement Check for unrealistic or incorrect constraints

set_zero_interconnect_delay_mode true

Warning: Timer is in zero interconnect delay mode. (TIM-177)

report_constraint –all

report_timing

set_zero_interconnect_delay_mode false

Information: Timer is not in zero interconnect delay mode. (TIM-176)

Logical Data Physical Data place_opt clock_opt route_opt Analysis Outputplace_opt

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Placement and Related Optimizations

place_opt

Performs iterative placement and optimization. DTDP: slack is a direct placement objective

Logic moved closer together for shorter nets

Cells upsized for optimal drive/speed

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Clock Tree Synthesis

1. Set the clock tree options/exceptions

2. Run the clock_opt command

Builds the clock trees Performs incremental logic and placement optimizations Runs clock tree optimizations Routes the clock nets

Optionally, clock_opt can Fix hold time violations Perform inter-clock balancing

Logical Data Physical Data place_opt clock_opt route_opt Analysis Outputclock_opt

clock_opt

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Routing

runs the routers: Global Route Track Assignment Detailed Route

Then performs numerous logic, placement, routing and crosstalk optimizations to produce the best routed design

Logical Data Physical Data place_opt clock_opt route_opt Analysis Outputroute_opt

route_opt

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Analysis

Examine the screen-outputs of place_opt and route_opt for design summaries: Utilization WNS – Worst Negative Slack TNS – Total Negative Slack Legality of cell placement Cell count and area Design rule violations

Use report_qor to see: WNS/TNS per path group (clock group) Other statistics

Logical Data Physical Data place_opt clock_opt route_opt Analysis OutputAnalysis

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Analysis – Details

Generate more detailed reports Show all violating path end points

report_constraint –all_violators Show details of the worst violating setup paths

report_timing Report physical design statistics (e.g. utilization)

report_design -physical Analyze the congestion

Congestion map (GUI) report_congestion

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Apply consistent naming

Imperative when exporting data always!

Save the design in the Milkyway database

Save as Verilog netlist

Save the floorplan only

change_names –hierarchy –rules verilog


write_def -output floorplan.def

write_floorplan floorplan.tcl

write -format verilog \-hierarchy -output routed.v

Output Logical Data Physical Data place_opt clock_opt route_opt Analysis OutputOutput

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Example “run” Script

lappend search_path ./design_data ../db ../tlupset link_library "* gates.db rams.db"set target_library "gates.db"create_mw_lib my_lib.mw \ –technology tech_file.tf \ –mw_reference_library "mwlib/gates mw_lib/rams“ \ -openimport_designs my_design.v \

-format verilog \-top MYDESIGN

set_tlu_plus_files \-max_tluplus abc_max.tlup \-min_tluplus abc_min.tlup \-tech2itf_map abc.map ; explained later…

read_sdc my_design.sdccheck_timing

read_def -allow_physical my_design.defcheck_physical_constraints



UNIX$ icc_shell –f run.tcl | tee myrun.log

run.tcl

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Local Disk Space Usage

When running a design through the IC Compiler flow, you will require local disk space to store the database. Example:

The above table shows the incremental disk space requirements for each step. So, to complete a 150K design, you need 56 + 62 + 120 = 238 MB.

Design size Milkyway database** size

(instances) place_opt clock_opt route_opt

---------------------------------------------------------------

150K 56MB 62MB 120MB

250K 150MB 178MB 303MB

400K 242MB 269MB 460MB

625K 277MB 325MB 569MB

700K 344MB 419MB 741MB

850K 917MB 950MB 1.5GB

** this includes all CEL/ROUTE/PARA/... views plus any CEL attachments

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Usage of the /tmp Directory

IC Compiler uses the /tmp directory for temporary data storage. This can be changed using a Unix env. variable:setenv $TMPDIR directory_name

Overall disk space required for the /tmp directory is 3x the physical RAM size For example, a machine with 16G of physical RAM

needs a minimum of 48G of disk space for the /tmp directory

You need to pay special attention to the RAM utilization when you run several large designs on the same machine, even with multiple CPUs

Designs of the same size but different constraints or levels of logic can require very different storage

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Static Timing Analysis

IC Compiler is set up very similarly to Design Compiler and PrimeTime

Before starting with IC Compiler, set up the libraries and operating conditions. Example:

set link_library "* abcmax.db"

set_operating_conditions \

–analysis_type on_chip_variation \

-max abc_wc -max_library abc_max

Using operating conditions ‘abc_wc' found in library ‘abc_max'.

report_timing –delay max|minMore Complex

Setup in Unit 4!

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Timing and Optimization Setup (1/2)

Timing and optimization in IC Compiler is controlled by many variables and commands. Exampleset enable_recovery_removal_arcs true

set timing_self_loops_no_skew true

set_cost_priority {max_delay max_capacitance}

set_ahfs_options -enable_port_punching true

Memorizing all these variables and commands can be a challenge – the GUI provides help!

Use the GUI to perform your timing and optimization setup, then copy the

variables / commands into your setup file

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Timing and Optimization Setup (2/2)

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Timing is Based on Cell and Net Delays

ICC calculates delay for every cell and every net

To calculate delays, ICC needs to know each net’s parasitic Rs and Cs

Cell Delay = (Input Transition Time, Cnet + Cpin)

Net Delay = (Rnet, Cnet + Cpin)

0.5 ns

CnetCpinRnet

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TLU+ Models

IC Compiler calculates C and R using the net geometry and the TLU+ look-up tables

UDSM process effects modeled

SingleProcess File

(ITF)

TLU+ICC, PC, Astro™ICC, PC, Astro™

nxtgrdStar-RCXT™Star-RCXT™

UDSM Process Effects Conformal Dielectric Metal Fill Shallow Trench Isolation Copper Dishing:

• Density Analysis• Width/Spacing

Trapezoid ConductorSee Appendix B for details



Trapezoid ConductorSee Appendix B for details

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Generating TLU+ Models

ITF (process file) provided by the vendor

TLU+ model is generally not provided

Generate TLU+ from ITF

Where: -itf2TLUPlus generates TLU+ instead of nxtgrd file -i is the ITF file-o is the output, binary TLU+ model

file

unix% grdgenxo -itf2TLUPlus -i <ITF file>

-o <TLU+ file>

Always use the latest Star-RCXT release to generate the models.

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set_tlu_plus_files \

-max_tluplus abc_max.tlup \

-min_tluplus abc_min.tlup \

-tech2itf_map abc.map

Loading TLU+ Models

IC Compiler searches search_path to find TLU+ files

Performs sanity check on TLU+ settings Execute this command after setting TLU+ to ensure

correct TLU+ and map file

check_tlu_plus_files

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Mapping file

The Mapping File maps the .tf (MW technology file) layer/via names to Star-RCXT .itf layer/via names.

Layer "METAL" {

layerNumber = 14

maskName = "metal1"

…

DIELECTRIC cm_extra3 { THICKNESS=0.06 ER=4.2 }

CONDUCTOR cm { THICKNESS=0.26 WMIN=0.16 …}

DIELECTRIC diel1d { THICKNESS=0.435 ER=4.2 }

…

abc.itfabc.tf

conducting_layers poly poly metal1 cm metal2 cm2

…

abc.map

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Calculating Cell and Net Delay

Now that R and C are known from TLU+, the delays can be calculated

For Cell Delays, only Ctotal / Ceff is needed

Calculating Net Delay is done using Delay Calculation algorithms: Elmore, Arnoldi

C1

R1

R2

R3C3

C4

U2

U1

C2

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PreRoute Delay Calculation Algorithm

Prior to routing, net geometry is estimated based on a Virtual Route

Since Virtual Routing is only an estimate,an Elmore model is used for delay calculation

Pin-to-pin timing

Virtual Route

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PostRoute Delay Calculation Algorithms

After routing, detailed nets are available and extraction can be more accurate

By default, Elmore is still used

Arnoldi can be turned on for postroute calculations

Detailed Route

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Basic Flow Summary

You should now be able to:

Create a Milkyway library to hold your design

Read all necessary files required to run IC Compiler, resolving common errors/warnings

Set up timing for analysis and optimizations

Execute the basic flow for placement, CTS and routing in IC Compiler

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45 minutes

Lab 1: Baseline flow for IC Compiler

Goals:

Setup design database and timing

Perform baseline place, cts & route operations with associated default optimizations

Create MW database with attached libraries

Create MW database with attached libraries

place_optplace_opt

clock_optclock_opt

route_optroute_opt

Analysis and OutputAnalysis and Output

Read design, constraints, floorplan

Read design, constraints, floorplan

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Appendix A

MW reference library preparation

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Migration from DB/PDB to MW: Terminology

DC / PC Terminology Milkyway Terminology

Library Compiler (compile library)

read_lib, write_lib

Milkyway tool (create/editMilkyway Library)

read_lef, read_plib, …

Database ( db )

Library db (timing)

PDB (physical)Design db/ddc

Milkyway Library

Library db (can be part of Ref Lib as LM view)

Reference LibraryDesign Library

Setup without using Milkyway:

search_pathlink_librarytarget_library

Setup using Milkyway library:

search_pathlink_librarytarget_library set_mw_lib_reference

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Reference Library Requirements

Logical libraries (.db)

Physical libraries (MW)

Libraries are provided by the ASIC vendor

Physical Library

Cell size

--------------------------

bufbd1 (1.6400, 3.6900)

sdbfb1 (14.7600, 3.6900)

filler (13.1200, 3.6900)

Logical Library

Cell Attribute

-----------------------

bufbd1

sdbfb1 t(mux_ff)

set target_library {art005.db} set_mw_lib_reference {art005}

libraries must match

• cell names

• pins

physical only cell

test cell

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icc_shell> check_physical_constraints...Physical Library: design_lib_orcaRouting layer : METAL width: 160 pitch: 410 space: 180Routing Layer : METAL Resistance : 6.4e-05 Capacitance : 4.19e-05Routing layer : METAL2 width: 200 pitch: 410 space: 210Routing Layer : METAL2 Resistance : 3.7e-05 Capacitance : 2.23e-05Routing layer : METAL3 width: 200 pitch: 515 space: 210Routing Layer : METAL3 Resistance : 3.7e-05 Capacitance : 1.39e-05Routing layer : METAL4 width: 440 pitch: 970 space: 460Routing Layer : METAL4 Resistance : 1.9e-05 Capacitance : 1.02e-05...

Physical Technology Data

pitch

width

spacing

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Convert LEF to Milkyway FRAM

Specify the MW library name

Specify the tech LEF, if one is available; unless the MW library has already been

prepared with a MW techfile.

Finally, specify you cell LEF files.

Command:read_lef

UNIX% Milkyway -galaxy

Press Apply: This converts the cells in the LEF file into FRAM views and adds them to the Milkyway library.

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Convert PLIB/PDB to Milkyway FRAM

Press Apply: This converts the cells in the pdb/plib file into FRAM views and adds them to the Milkyway library.

Specify the MW library name

Specify the tech pdb, if one is available; unless the MW library has already been

prepared with a MW techfile.

Finally, specify you cell PDB files.

Command:read_plib

UNIX% Milkyway -galaxy

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Appendix B

DSM Effects

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DSM Effects



Trapezoid Conductor



Trapezoid Conductor

Conformal DielectricConformal Dielectric

Chemical Mechanical Polishing (CMP)Chemical Mechanical Polishing (CMP)

STI - Not very relevant for routing modeling

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ICC1 200703 IG 01 Basicflow

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Transcript of ICC1 200703 IG 01 Basicflow